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/arch/arm/mach-ixp4xx/include/mach/entry-macro.S

https://github.com/AICP/kernel_google_msm
Assembly | 41 lines | 36 code | 5 blank | 0 comment | 2 complexity | 3200a7d1b77049723855570d9f8d30eb MD5 | raw file
 1/*
 2 * arch/arm/mach-ixp4xx/include/mach/entry-macro.S
 3 *
 4 * Low-level IRQ helper macros for IXP4xx-based platforms
 5 *
 6 * This file is licensed under  the terms of the GNU General Public
 7 * License version 2. This program is licensed "as is" without any
 8 * warranty of any kind, whether express or implied.
 9 */
10#include <mach/hardware.h>
11
12		.macro  get_irqnr_preamble, base, tmp
13		.endm
14
15		.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
16		ldr	\irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP_OFFSET)
17		ldr	\irqstat, [\irqstat]		@ get interrupts
18		cmp	\irqstat, #0
19		beq	1001f				@ upper IRQ?
20		clz     \irqnr, \irqstat
21		mov     \base, #31
22		sub     \irqnr, \base, \irqnr
23		b	1002f				@ lower IRQ being
24							@ handled
25
261001:
27		/*
28		 * IXP465/IXP435 has an upper IRQ status register
29		 */
30#if defined(CONFIG_CPU_IXP46X) || defined(CONFIG_CPU_IXP43X)
31		ldr	\irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP2_OFFSET)
32		ldr	\irqstat, [\irqstat]		@ get upper interrupts
33		mov	\irqnr, #63
34		clz	\irqstat, \irqstat
35 		cmp	\irqstat, #32
36		subne	\irqnr, \irqnr, \irqstat
37#endif
381002:
39		.endm
40
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