/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi

https://github.com/aicjofs/android_kernel_lge_v500_20d_f2fs · Device Tree · 357 lines · 286 code · 30 blank · 41 comment · 0 complexity · 74a4462c9e0c7fba586896573afb448b MD5 · raw file

  1. /*
  2. * P5020/5010 Silicon/SoC Device Tree Source (post include)
  3. *
  4. * Copyright 2011 Freescale Semiconductor Inc.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions are met:
  8. * * Redistributions of source code must retain the above copyright
  9. * notice, this list of conditions and the following disclaimer.
  10. * * Redistributions in binary form must reproduce the above copyright
  11. * notice, this list of conditions and the following disclaimer in the
  12. * documentation and/or other materials provided with the distribution.
  13. * * Neither the name of Freescale Semiconductor nor the
  14. * names of its contributors may be used to endorse or promote products
  15. * derived from this software without specific prior written permission.
  16. *
  17. *
  18. * ALTERNATIVELY, this software may be distributed under the terms of the
  19. * GNU General Public License ("GPL") as published by the Free Software
  20. * Foundation, either version 2 of that License or (at your option) any
  21. * later version.
  22. *
  23. * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  24. * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26. * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27. * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33. */
  34. &lbc {
  35. compatible = "fsl,p5020-elbc", "fsl,elbc", "simple-bus";
  36. interrupts = <25 2 0 0>;
  37. #address-cells = <2>;
  38. #size-cells = <1>;
  39. };
  40. /* controller at 0x200000 */
  41. &pci0 {
  42. compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
  43. device_type = "pci";
  44. #size-cells = <2>;
  45. #address-cells = <3>;
  46. bus-range = <0x0 0xff>;
  47. clock-frequency = <33333333>;
  48. interrupts = <16 2 1 15>;
  49. pcie@0 {
  50. reg = <0 0 0 0 0>;
  51. #interrupt-cells = <1>;
  52. #size-cells = <2>;
  53. #address-cells = <3>;
  54. device_type = "pci";
  55. interrupts = <16 2 1 15>;
  56. interrupt-map-mask = <0xf800 0 0 7>;
  57. interrupt-map = <
  58. /* IDSEL 0x0 */
  59. 0000 0 0 1 &mpic 40 1 0 0
  60. 0000 0 0 2 &mpic 1 1 0 0
  61. 0000 0 0 3 &mpic 2 1 0 0
  62. 0000 0 0 4 &mpic 3 1 0 0
  63. >;
  64. };
  65. };
  66. /* controller at 0x201000 */
  67. &pci1 {
  68. compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
  69. device_type = "pci";
  70. #size-cells = <2>;
  71. #address-cells = <3>;
  72. bus-range = <0 0xff>;
  73. clock-frequency = <33333333>;
  74. interrupts = <16 2 1 14>;
  75. pcie@0 {
  76. reg = <0 0 0 0 0>;
  77. #interrupt-cells = <1>;
  78. #size-cells = <2>;
  79. #address-cells = <3>;
  80. device_type = "pci";
  81. interrupts = <16 2 1 14>;
  82. interrupt-map-mask = <0xf800 0 0 7>;
  83. interrupt-map = <
  84. /* IDSEL 0x0 */
  85. 0000 0 0 1 &mpic 41 1 0 0
  86. 0000 0 0 2 &mpic 5 1 0 0
  87. 0000 0 0 3 &mpic 6 1 0 0
  88. 0000 0 0 4 &mpic 7 1 0 0
  89. >;
  90. };
  91. };
  92. /* controller at 0x202000 */
  93. &pci2 {
  94. compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
  95. device_type = "pci";
  96. #size-cells = <2>;
  97. #address-cells = <3>;
  98. bus-range = <0x0 0xff>;
  99. clock-frequency = <33333333>;
  100. interrupts = <16 2 1 13>;
  101. pcie@0 {
  102. reg = <0 0 0 0 0>;
  103. #interrupt-cells = <1>;
  104. #size-cells = <2>;
  105. #address-cells = <3>;
  106. device_type = "pci";
  107. interrupts = <16 2 1 13>;
  108. interrupt-map-mask = <0xf800 0 0 7>;
  109. interrupt-map = <
  110. /* IDSEL 0x0 */
  111. 0000 0 0 1 &mpic 42 1 0 0
  112. 0000 0 0 2 &mpic 9 1 0 0
  113. 0000 0 0 3 &mpic 10 1 0 0
  114. 0000 0 0 4 &mpic 11 1 0 0
  115. >;
  116. };
  117. };
  118. /* controller at 0x203000 */
  119. &pci3 {
  120. compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
  121. device_type = "pci";
  122. #size-cells = <2>;
  123. #address-cells = <3>;
  124. bus-range = <0x0 0xff>;
  125. clock-frequency = <33333333>;
  126. interrupts = <16 2 1 12>;
  127. pcie@0 {
  128. reg = <0 0 0 0 0>;
  129. #interrupt-cells = <1>;
  130. #size-cells = <2>;
  131. #address-cells = <3>;
  132. device_type = "pci";
  133. interrupts = <16 2 1 12>;
  134. interrupt-map-mask = <0xf800 0 0 7>;
  135. interrupt-map = <
  136. /* IDSEL 0x0 */
  137. 0000 0 0 1 &mpic 43 1 0 0
  138. 0000 0 0 2 &mpic 0 1 0 0
  139. 0000 0 0 3 &mpic 4 1 0 0
  140. 0000 0 0 4 &mpic 8 1 0 0
  141. >;
  142. };
  143. };
  144. &rio {
  145. compatible = "fsl,srio";
  146. interrupts = <16 2 1 11>;
  147. #address-cells = <2>;
  148. #size-cells = <2>;
  149. ranges;
  150. port1 {
  151. #address-cells = <2>;
  152. #size-cells = <2>;
  153. cell-index = <1>;
  154. };
  155. port2 {
  156. #address-cells = <2>;
  157. #size-cells = <2>;
  158. cell-index = <2>;
  159. };
  160. };
  161. &dcsr {
  162. #address-cells = <1>;
  163. #size-cells = <1>;
  164. compatible = "fsl,dcsr", "simple-bus";
  165. dcsr-epu@0 {
  166. compatible = "fsl,dcsr-epu";
  167. interrupts = <52 2 0 0
  168. 84 2 0 0
  169. 85 2 0 0>;
  170. reg = <0x0 0x1000>;
  171. };
  172. dcsr-npc {
  173. compatible = "fsl,dcsr-npc";
  174. reg = <0x1000 0x1000 0x1000000 0x8000>;
  175. };
  176. dcsr-nxc@2000 {
  177. compatible = "fsl,dcsr-nxc";
  178. reg = <0x2000 0x1000>;
  179. };
  180. dcsr-corenet {
  181. compatible = "fsl,dcsr-corenet";
  182. reg = <0x8000 0x1000 0xB0000 0x1000>;
  183. };
  184. dcsr-dpaa@9000 {
  185. compatible = "fsl,p5020-dcsr-dpaa", "fsl,dcsr-dpaa";
  186. reg = <0x9000 0x1000>;
  187. };
  188. dcsr-ocn@11000 {
  189. compatible = "fsl,p5020-dcsr-ocn", "fsl,dcsr-ocn";
  190. reg = <0x11000 0x1000>;
  191. };
  192. dcsr-ddr@12000 {
  193. compatible = "fsl,dcsr-ddr";
  194. dev-handle = <&ddr1>;
  195. reg = <0x12000 0x1000>;
  196. };
  197. dcsr-ddr@13000 {
  198. compatible = "fsl,dcsr-ddr";
  199. dev-handle = <&ddr2>;
  200. reg = <0x13000 0x1000>;
  201. };
  202. dcsr-nal@18000 {
  203. compatible = "fsl,p5020-dcsr-nal", "fsl,dcsr-nal";
  204. reg = <0x18000 0x1000>;
  205. };
  206. dcsr-rcpm@22000 {
  207. compatible = "fsl,p5020-dcsr-rcpm", "fsl,dcsr-rcpm";
  208. reg = <0x22000 0x1000>;
  209. };
  210. dcsr-cpu-sb-proxy@40000 {
  211. compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  212. cpu-handle = <&cpu0>;
  213. reg = <0x40000 0x1000>;
  214. };
  215. dcsr-cpu-sb-proxy@41000 {
  216. compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  217. cpu-handle = <&cpu1>;
  218. reg = <0x41000 0x1000>;
  219. };
  220. };
  221. &soc {
  222. #address-cells = <1>;
  223. #size-cells = <1>;
  224. device_type = "soc";
  225. compatible = "simple-bus";
  226. soc-sram-error {
  227. compatible = "fsl,soc-sram-error";
  228. interrupts = <16 2 1 29>;
  229. };
  230. corenet-law@0 {
  231. compatible = "fsl,corenet-law";
  232. reg = <0x0 0x1000>;
  233. fsl,num-laws = <32>;
  234. };
  235. ddr1: memory-controller@8000 {
  236. compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
  237. reg = <0x8000 0x1000>;
  238. interrupts = <16 2 1 23>;
  239. };
  240. ddr2: memory-controller@9000 {
  241. compatible = "fsl,qoriq-memory-controller-v4.5","fsl,qoriq-memory-controller";
  242. reg = <0x9000 0x1000>;
  243. interrupts = <16 2 1 22>;
  244. };
  245. cpc: l3-cache-controller@10000 {
  246. compatible = "fsl,p5020-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
  247. reg = <0x10000 0x1000
  248. 0x11000 0x1000>;
  249. interrupts = <16 2 1 27
  250. 16 2 1 26>;
  251. };
  252. corenet-cf@18000 {
  253. compatible = "fsl,corenet-cf";
  254. reg = <0x18000 0x1000>;
  255. interrupts = <16 2 1 31>;
  256. fsl,ccf-num-csdids = <32>;
  257. fsl,ccf-num-snoopids = <32>;
  258. };
  259. iommu@20000 {
  260. compatible = "fsl,pamu-v1.0", "fsl,pamu";
  261. reg = <0x20000 0x4000>;
  262. interrupts = <
  263. 24 2 0 0
  264. 16 2 1 30>;
  265. };
  266. /include/ "qoriq-mpic.dtsi"
  267. guts: global-utilities@e0000 {
  268. compatible = "fsl,qoriq-device-config-1.0";
  269. reg = <0xe0000 0xe00>;
  270. fsl,has-rstcr;
  271. #sleep-cells = <1>;
  272. fsl,liodn-bits = <12>;
  273. };
  274. pins: global-utilities@e0e00 {
  275. compatible = "fsl,qoriq-pin-control-1.0";
  276. reg = <0xe0e00 0x200>;
  277. #sleep-cells = <2>;
  278. };
  279. clockgen: global-utilities@e1000 {
  280. compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
  281. reg = <0xe1000 0x1000>;
  282. clock-frequency = <0>;
  283. };
  284. rcpm: global-utilities@e2000 {
  285. compatible = "fsl,qoriq-rcpm-1.0";
  286. reg = <0xe2000 0x1000>;
  287. #sleep-cells = <1>;
  288. };
  289. sfp: sfp@e8000 {
  290. compatible = "fsl,p5020-sfp", "fsl,qoriq-sfp-1.0";
  291. reg = <0xe8000 0x1000>;
  292. };
  293. serdes: serdes@ea000 {
  294. compatible = "fsl,p5020-serdes";
  295. reg = <0xea000 0x1000>;
  296. };
  297. /include/ "qoriq-dma-0.dtsi"
  298. /include/ "qoriq-dma-1.dtsi"
  299. /include/ "qoriq-espi-0.dtsi"
  300. spi@110000 {
  301. fsl,espi-num-chipselects = <4>;
  302. };
  303. /include/ "qoriq-esdhc-0.dtsi"
  304. sdhc@114000 {
  305. sdhci,auto-cmd12;
  306. };
  307. /include/ "qoriq-i2c-0.dtsi"
  308. /include/ "qoriq-i2c-1.dtsi"
  309. /include/ "qoriq-duart-0.dtsi"
  310. /include/ "qoriq-duart-1.dtsi"
  311. /include/ "qoriq-gpio-0.dtsi"
  312. /include/ "qoriq-usb2-mph-0.dtsi"
  313. usb0: usb@210000 {
  314. compatible = "fsl-usb2-mph-v1.6", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
  315. phy_type = "utmi";
  316. port0;
  317. };
  318. /include/ "qoriq-usb2-dr-0.dtsi"
  319. usb1: usb@211000 {
  320. compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
  321. dr_mode = "host";
  322. phy_type = "utmi";
  323. };
  324. /include/ "qoriq-sata2-0.dtsi"
  325. /include/ "qoriq-sata2-1.dtsi"
  326. /include/ "qoriq-sec4.2-0.dtsi"
  327. };