/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi

https://github.com/aicjofs/android_kernel_lge_v500_20d · Device Tree · 246 lines · 174 code · 29 blank · 43 comment · 0 complexity · 90a2e9bff21ec9b2f0e0b60d7023974c MD5 · raw file

  1. /*
  2. * P1022/P1013 Silicon/SoC Device Tree Source (post include)
  3. *
  4. * Copyright 2011 Freescale Semiconductor Inc.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions are met:
  8. * * Redistributions of source code must retain the above copyright
  9. * notice, this list of conditions and the following disclaimer.
  10. * * Redistributions in binary form must reproduce the above copyright
  11. * notice, this list of conditions and the following disclaimer in the
  12. * documentation and/or other materials provided with the distribution.
  13. * * Neither the name of Freescale Semiconductor nor the
  14. * names of its contributors may be used to endorse or promote products
  15. * derived from this software without specific prior written permission.
  16. *
  17. *
  18. * ALTERNATIVELY, this software may be distributed under the terms of the
  19. * GNU General Public License ("GPL") as published by the Free Software
  20. * Foundation, either version 2 of that License or (at your option) any
  21. * later version.
  22. *
  23. * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  24. * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26. * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27. * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33. */
  34. &lbc {
  35. #address-cells = <2>;
  36. #size-cells = <1>;
  37. /*
  38. * The localbus on the P1022 is not a simple-bus because of the eLBC
  39. * pin muxing when the DIU is enabled.
  40. */
  41. compatible = "fsl,p1022-elbc", "fsl,elbc";
  42. interrupts = <19 2 0 0>;
  43. };
  44. /* controller at 0x9000 */
  45. &pci0 {
  46. compatible = "fsl,p1022-pcie";
  47. device_type = "pci";
  48. #size-cells = <2>;
  49. #address-cells = <3>;
  50. bus-range = <0 255>;
  51. clock-frequency = <33333333>;
  52. interrupts = <16 2 0 0>;
  53. pcie@0 {
  54. reg = <0 0 0 0 0>;
  55. #interrupt-cells = <1>;
  56. #size-cells = <2>;
  57. #address-cells = <3>;
  58. device_type = "pci";
  59. interrupts = <16 2 0 0>;
  60. interrupt-map-mask = <0xf800 0 0 7>;
  61. interrupt-map = <
  62. /* IDSEL 0x0 */
  63. 0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
  64. 0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
  65. 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
  66. 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
  67. >;
  68. };
  69. };
  70. /* controller at 0xa000 */
  71. &pci1 {
  72. compatible = "fsl,p1022-pcie";
  73. device_type = "pci";
  74. #size-cells = <2>;
  75. #address-cells = <3>;
  76. bus-range = <0 255>;
  77. clock-frequency = <33333333>;
  78. interrupts = <16 2 0 0>;
  79. pcie@0 {
  80. reg = <0 0 0 0 0>;
  81. #interrupt-cells = <1>;
  82. #size-cells = <2>;
  83. #address-cells = <3>;
  84. device_type = "pci";
  85. interrupts = <16 2 0 0>;
  86. interrupt-map-mask = <0xf800 0 0 7>;
  87. interrupt-map = <
  88. /* IDSEL 0x0 */
  89. 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
  90. 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
  91. 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
  92. 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
  93. >;
  94. };
  95. };
  96. /* controller at 0xb000 */
  97. &pci2 {
  98. compatible = "fsl,p1022-pcie";
  99. device_type = "pci";
  100. #size-cells = <2>;
  101. #address-cells = <3>;
  102. bus-range = <0 255>;
  103. clock-frequency = <33333333>;
  104. interrupts = <16 2 0 0>;
  105. pcie@0 {
  106. reg = <0 0 0 0 0>;
  107. #interrupt-cells = <1>;
  108. #size-cells = <2>;
  109. #address-cells = <3>;
  110. device_type = "pci";
  111. interrupts = <16 2 0 0>;
  112. interrupt-map-mask = <0xf800 0 0 7>;
  113. interrupt-map = <
  114. /* IDSEL 0x0 */
  115. 0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0
  116. 0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0
  117. 0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0
  118. 0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0
  119. >;
  120. };
  121. };
  122. &soc {
  123. #address-cells = <1>;
  124. #size-cells = <1>;
  125. device_type = "soc";
  126. compatible = "fsl,p1022-immr", "simple-bus";
  127. bus-frequency = <0>; // Filled out by uboot.
  128. ecm-law@0 {
  129. compatible = "fsl,ecm-law";
  130. reg = <0x0 0x1000>;
  131. fsl,num-laws = <12>;
  132. };
  133. ecm@1000 {
  134. compatible = "fsl,p1022-ecm", "fsl,ecm";
  135. reg = <0x1000 0x1000>;
  136. interrupts = <16 2 0 0>;
  137. };
  138. memory-controller@2000 {
  139. compatible = "fsl,p1022-memory-controller";
  140. reg = <0x2000 0x1000>;
  141. interrupts = <16 2 0 0>;
  142. };
  143. /include/ "pq3-i2c-0.dtsi"
  144. /include/ "pq3-i2c-1.dtsi"
  145. /include/ "pq3-duart-0.dtsi"
  146. /include/ "pq3-espi-0.dtsi"
  147. spi@7000 {
  148. fsl,espi-num-chipselects = <4>;
  149. };
  150. /include/ "pq3-dma-1.dtsi"
  151. dma@c300 {
  152. dma00: dma-channel@0 {
  153. compatible = "fsl,ssi-dma-channel";
  154. };
  155. dma01: dma-channel@80 {
  156. compatible = "fsl,ssi-dma-channel";
  157. };
  158. };
  159. /include/ "pq3-gpio-0.dtsi"
  160. display@10000 {
  161. compatible = "fsl,diu", "fsl,p1022-diu";
  162. reg = <0x10000 1000>;
  163. interrupts = <64 2 0 0>;
  164. };
  165. ssi@15000 {
  166. compatible = "fsl,mpc8610-ssi";
  167. cell-index = <0>;
  168. reg = <0x15000 0x100>;
  169. interrupts = <75 2 0 0>;
  170. fsl,playback-dma = <&dma00>;
  171. fsl,capture-dma = <&dma01>;
  172. fsl,fifo-depth = <15>;
  173. };
  174. /include/ "pq3-sata2-0.dtsi"
  175. /include/ "pq3-sata2-1.dtsi"
  176. L2: l2-cache-controller@20000 {
  177. compatible = "fsl,p1022-l2-cache-controller";
  178. reg = <0x20000 0x1000>;
  179. cache-line-size = <32>; // 32 bytes
  180. cache-size = <0x40000>; // L2,256K
  181. interrupts = <16 2 0 0>;
  182. };
  183. /include/ "pq3-dma-0.dtsi"
  184. /include/ "pq3-usb2-dr-0.dtsi"
  185. usb@22000 {
  186. compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
  187. };
  188. /include/ "pq3-usb2-dr-1.dtsi"
  189. usb@23000 {
  190. compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
  191. };
  192. /include/ "pq3-esdhc-0.dtsi"
  193. sdhc@2e000 {
  194. compatible = "fsl,p1022-esdhc", "fsl,esdhc";
  195. sdhci,auto-cmd12;
  196. };
  197. /include/ "pq3-sec3.3-0.dtsi"
  198. /include/ "pq3-mpic.dtsi"
  199. /include/ "pq3-mpic-timer-B.dtsi"
  200. /include/ "pq3-etsec2-0.dtsi"
  201. enet0: enet0_grp2: ethernet@b0000 {
  202. };
  203. /include/ "pq3-etsec2-1.dtsi"
  204. enet1: enet1_grp2: ethernet@b1000 {
  205. };
  206. global-utilities@e0000 {
  207. compatible = "fsl,p1022-guts";
  208. reg = <0xe0000 0x1000>;
  209. fsl,has-rstcr;
  210. };
  211. power@e0070{
  212. compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc";
  213. reg = <0xe0070 0x20>;
  214. };
  215. };
  216. /include/ "pq3-etsec2-grp2-0.dtsi"
  217. /include/ "pq3-etsec2-grp2-1.dtsi"