/arch/arm/mach-kirkwood/common.c

https://github.com/AICP/kernel_google_msm · C · 549 lines · 365 code · 85 blank · 99 comment · 61 complexity · 18532e4dbe9635e34af5cb660b6fc280 MD5 · raw file

  1. /*
  2. * arch/arm/mach-kirkwood/common.c
  3. *
  4. * Core functions for Marvell Kirkwood SoCs
  5. *
  6. * This file is licensed under the terms of the GNU General Public
  7. * License version 2. This program is licensed "as is" without any
  8. * warranty of any kind, whether express or implied.
  9. */
  10. #include <linux/kernel.h>
  11. #include <linux/init.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/serial_8250.h>
  14. #include <linux/ata_platform.h>
  15. #include <linux/mtd/nand.h>
  16. #include <linux/dma-mapping.h>
  17. #include <net/dsa.h>
  18. #include <asm/page.h>
  19. #include <asm/timex.h>
  20. #include <asm/kexec.h>
  21. #include <asm/mach/map.h>
  22. #include <asm/mach/time.h>
  23. #include <mach/kirkwood.h>
  24. #include <mach/bridge-regs.h>
  25. #include <plat/audio.h>
  26. #include <plat/cache-feroceon-l2.h>
  27. #include <plat/mvsdio.h>
  28. #include <plat/orion_nand.h>
  29. #include <plat/ehci-orion.h>
  30. #include <plat/common.h>
  31. #include <plat/time.h>
  32. #include <plat/addr-map.h>
  33. #include "common.h"
  34. /*****************************************************************************
  35. * I/O Address Mapping
  36. ****************************************************************************/
  37. static struct map_desc kirkwood_io_desc[] __initdata = {
  38. {
  39. .virtual = KIRKWOOD_PCIE_IO_VIRT_BASE,
  40. .pfn = __phys_to_pfn(KIRKWOOD_PCIE_IO_PHYS_BASE),
  41. .length = KIRKWOOD_PCIE_IO_SIZE,
  42. .type = MT_DEVICE,
  43. }, {
  44. .virtual = KIRKWOOD_PCIE1_IO_VIRT_BASE,
  45. .pfn = __phys_to_pfn(KIRKWOOD_PCIE1_IO_PHYS_BASE),
  46. .length = KIRKWOOD_PCIE1_IO_SIZE,
  47. .type = MT_DEVICE,
  48. }, {
  49. .virtual = KIRKWOOD_REGS_VIRT_BASE,
  50. .pfn = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),
  51. .length = KIRKWOOD_REGS_SIZE,
  52. .type = MT_DEVICE,
  53. },
  54. };
  55. void __init kirkwood_map_io(void)
  56. {
  57. iotable_init(kirkwood_io_desc, ARRAY_SIZE(kirkwood_io_desc));
  58. }
  59. /*
  60. * Default clock control bits. Any bit _not_ set in this variable
  61. * will be cleared from the hardware after platform devices have been
  62. * registered. Some reserved bits must be set to 1.
  63. */
  64. unsigned int kirkwood_clk_ctrl = CGC_DUNIT | CGC_RESERVED;
  65. /*****************************************************************************
  66. * EHCI0
  67. ****************************************************************************/
  68. void __init kirkwood_ehci_init(void)
  69. {
  70. kirkwood_clk_ctrl |= CGC_USB0;
  71. orion_ehci_init(USB_PHYS_BASE, IRQ_KIRKWOOD_USB, EHCI_PHY_NA);
  72. }
  73. /*****************************************************************************
  74. * GE00
  75. ****************************************************************************/
  76. void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data)
  77. {
  78. kirkwood_clk_ctrl |= CGC_GE0;
  79. orion_ge00_init(eth_data,
  80. GE00_PHYS_BASE, IRQ_KIRKWOOD_GE00_SUM,
  81. IRQ_KIRKWOOD_GE00_ERR, kirkwood_tclk);
  82. }
  83. /*****************************************************************************
  84. * GE01
  85. ****************************************************************************/
  86. void __init kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data)
  87. {
  88. kirkwood_clk_ctrl |= CGC_GE1;
  89. orion_ge01_init(eth_data,
  90. GE01_PHYS_BASE, IRQ_KIRKWOOD_GE01_SUM,
  91. IRQ_KIRKWOOD_GE01_ERR, kirkwood_tclk);
  92. }
  93. /*****************************************************************************
  94. * Ethernet switch
  95. ****************************************************************************/
  96. void __init kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq)
  97. {
  98. orion_ge00_switch_init(d, irq);
  99. }
  100. /*****************************************************************************
  101. * NAND flash
  102. ****************************************************************************/
  103. static struct resource kirkwood_nand_resource = {
  104. .flags = IORESOURCE_MEM,
  105. .start = KIRKWOOD_NAND_MEM_PHYS_BASE,
  106. .end = KIRKWOOD_NAND_MEM_PHYS_BASE +
  107. KIRKWOOD_NAND_MEM_SIZE - 1,
  108. };
  109. static struct orion_nand_data kirkwood_nand_data = {
  110. .cle = 0,
  111. .ale = 1,
  112. .width = 8,
  113. };
  114. static struct platform_device kirkwood_nand_flash = {
  115. .name = "orion_nand",
  116. .id = -1,
  117. .dev = {
  118. .platform_data = &kirkwood_nand_data,
  119. },
  120. .resource = &kirkwood_nand_resource,
  121. .num_resources = 1,
  122. };
  123. void __init kirkwood_nand_init(struct mtd_partition *parts, int nr_parts,
  124. int chip_delay)
  125. {
  126. kirkwood_clk_ctrl |= CGC_RUNIT;
  127. kirkwood_nand_data.parts = parts;
  128. kirkwood_nand_data.nr_parts = nr_parts;
  129. kirkwood_nand_data.chip_delay = chip_delay;
  130. platform_device_register(&kirkwood_nand_flash);
  131. }
  132. void __init kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts,
  133. int (*dev_ready)(struct mtd_info *))
  134. {
  135. kirkwood_clk_ctrl |= CGC_RUNIT;
  136. kirkwood_nand_data.parts = parts;
  137. kirkwood_nand_data.nr_parts = nr_parts;
  138. kirkwood_nand_data.dev_ready = dev_ready;
  139. platform_device_register(&kirkwood_nand_flash);
  140. }
  141. /*****************************************************************************
  142. * SoC RTC
  143. ****************************************************************************/
  144. static void __init kirkwood_rtc_init(void)
  145. {
  146. orion_rtc_init(RTC_PHYS_BASE, IRQ_KIRKWOOD_RTC);
  147. }
  148. /*****************************************************************************
  149. * SATA
  150. ****************************************************************************/
  151. void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data)
  152. {
  153. kirkwood_clk_ctrl |= CGC_SATA0;
  154. if (sata_data->n_ports > 1)
  155. kirkwood_clk_ctrl |= CGC_SATA1;
  156. orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_KIRKWOOD_SATA);
  157. }
  158. /*****************************************************************************
  159. * SD/SDIO/MMC
  160. ****************************************************************************/
  161. static struct resource mvsdio_resources[] = {
  162. [0] = {
  163. .start = SDIO_PHYS_BASE,
  164. .end = SDIO_PHYS_BASE + SZ_1K - 1,
  165. .flags = IORESOURCE_MEM,
  166. },
  167. [1] = {
  168. .start = IRQ_KIRKWOOD_SDIO,
  169. .end = IRQ_KIRKWOOD_SDIO,
  170. .flags = IORESOURCE_IRQ,
  171. },
  172. };
  173. static u64 mvsdio_dmamask = DMA_BIT_MASK(32);
  174. static struct platform_device kirkwood_sdio = {
  175. .name = "mvsdio",
  176. .id = -1,
  177. .dev = {
  178. .dma_mask = &mvsdio_dmamask,
  179. .coherent_dma_mask = DMA_BIT_MASK(32),
  180. },
  181. .num_resources = ARRAY_SIZE(mvsdio_resources),
  182. .resource = mvsdio_resources,
  183. };
  184. void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data)
  185. {
  186. u32 dev, rev;
  187. kirkwood_pcie_id(&dev, &rev);
  188. if (rev == 0 && dev != MV88F6282_DEV_ID) /* catch all Kirkwood Z0's */
  189. mvsdio_data->clock = 100000000;
  190. else
  191. mvsdio_data->clock = 200000000;
  192. kirkwood_clk_ctrl |= CGC_SDIO;
  193. kirkwood_sdio.dev.platform_data = mvsdio_data;
  194. platform_device_register(&kirkwood_sdio);
  195. }
  196. /*****************************************************************************
  197. * SPI
  198. ****************************************************************************/
  199. void __init kirkwood_spi_init()
  200. {
  201. kirkwood_clk_ctrl |= CGC_RUNIT;
  202. orion_spi_init(SPI_PHYS_BASE, kirkwood_tclk);
  203. }
  204. /*****************************************************************************
  205. * I2C
  206. ****************************************************************************/
  207. void __init kirkwood_i2c_init(void)
  208. {
  209. orion_i2c_init(I2C_PHYS_BASE, IRQ_KIRKWOOD_TWSI, 8);
  210. }
  211. /*****************************************************************************
  212. * UART0
  213. ****************************************************************************/
  214. void __init kirkwood_uart0_init(void)
  215. {
  216. orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
  217. IRQ_KIRKWOOD_UART_0, kirkwood_tclk);
  218. }
  219. /*****************************************************************************
  220. * UART1
  221. ****************************************************************************/
  222. void __init kirkwood_uart1_init(void)
  223. {
  224. orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
  225. IRQ_KIRKWOOD_UART_1, kirkwood_tclk);
  226. }
  227. /*****************************************************************************
  228. * Cryptographic Engines and Security Accelerator (CESA)
  229. ****************************************************************************/
  230. void __init kirkwood_crypto_init(void)
  231. {
  232. kirkwood_clk_ctrl |= CGC_CRYPTO;
  233. orion_crypto_init(CRYPTO_PHYS_BASE, KIRKWOOD_SRAM_PHYS_BASE,
  234. KIRKWOOD_SRAM_SIZE, IRQ_KIRKWOOD_CRYPTO);
  235. }
  236. /*****************************************************************************
  237. * XOR0
  238. ****************************************************************************/
  239. void __init kirkwood_xor0_init(void)
  240. {
  241. kirkwood_clk_ctrl |= CGC_XOR0;
  242. orion_xor0_init(XOR0_PHYS_BASE, XOR0_HIGH_PHYS_BASE,
  243. IRQ_KIRKWOOD_XOR_00, IRQ_KIRKWOOD_XOR_01);
  244. }
  245. /*****************************************************************************
  246. * XOR1
  247. ****************************************************************************/
  248. void __init kirkwood_xor1_init(void)
  249. {
  250. kirkwood_clk_ctrl |= CGC_XOR1;
  251. orion_xor1_init(XOR1_PHYS_BASE, XOR1_HIGH_PHYS_BASE,
  252. IRQ_KIRKWOOD_XOR_10, IRQ_KIRKWOOD_XOR_11);
  253. }
  254. /*****************************************************************************
  255. * Watchdog
  256. ****************************************************************************/
  257. void __init kirkwood_wdt_init(void)
  258. {
  259. orion_wdt_init(kirkwood_tclk);
  260. }
  261. /*****************************************************************************
  262. * Time handling
  263. ****************************************************************************/
  264. void __init kirkwood_init_early(void)
  265. {
  266. orion_time_set_base(TIMER_VIRT_BASE);
  267. }
  268. int kirkwood_tclk;
  269. static int __init kirkwood_find_tclk(void)
  270. {
  271. u32 dev, rev;
  272. kirkwood_pcie_id(&dev, &rev);
  273. if (dev == MV88F6281_DEV_ID || dev == MV88F6282_DEV_ID)
  274. if (((readl(SAMPLE_AT_RESET) >> 21) & 1) == 0)
  275. return 200000000;
  276. return 166666667;
  277. }
  278. static void __init kirkwood_timer_init(void)
  279. {
  280. kirkwood_tclk = kirkwood_find_tclk();
  281. orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
  282. IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk);
  283. }
  284. struct sys_timer kirkwood_timer = {
  285. .init = kirkwood_timer_init,
  286. };
  287. /*****************************************************************************
  288. * Audio
  289. ****************************************************************************/
  290. static struct resource kirkwood_i2s_resources[] = {
  291. [0] = {
  292. .start = AUDIO_PHYS_BASE,
  293. .end = AUDIO_PHYS_BASE + SZ_16K - 1,
  294. .flags = IORESOURCE_MEM,
  295. },
  296. [1] = {
  297. .start = IRQ_KIRKWOOD_I2S,
  298. .end = IRQ_KIRKWOOD_I2S,
  299. .flags = IORESOURCE_IRQ,
  300. },
  301. };
  302. static struct kirkwood_asoc_platform_data kirkwood_i2s_data = {
  303. .burst = 128,
  304. };
  305. static struct platform_device kirkwood_i2s_device = {
  306. .name = "kirkwood-i2s",
  307. .id = -1,
  308. .num_resources = ARRAY_SIZE(kirkwood_i2s_resources),
  309. .resource = kirkwood_i2s_resources,
  310. .dev = {
  311. .platform_data = &kirkwood_i2s_data,
  312. },
  313. };
  314. static struct platform_device kirkwood_pcm_device = {
  315. .name = "kirkwood-pcm-audio",
  316. .id = -1,
  317. };
  318. void __init kirkwood_audio_init(void)
  319. {
  320. kirkwood_clk_ctrl |= CGC_AUDIO;
  321. platform_device_register(&kirkwood_i2s_device);
  322. platform_device_register(&kirkwood_pcm_device);
  323. }
  324. /*****************************************************************************
  325. * General
  326. ****************************************************************************/
  327. /*
  328. * Identify device ID and revision.
  329. */
  330. char * __init kirkwood_id(void)
  331. {
  332. u32 dev, rev;
  333. kirkwood_pcie_id(&dev, &rev);
  334. if (dev == MV88F6281_DEV_ID) {
  335. if (rev == MV88F6281_REV_Z0)
  336. return "MV88F6281-Z0";
  337. else if (rev == MV88F6281_REV_A0)
  338. return "MV88F6281-A0";
  339. else if (rev == MV88F6281_REV_A1)
  340. return "MV88F6281-A1";
  341. else
  342. return "MV88F6281-Rev-Unsupported";
  343. } else if (dev == MV88F6192_DEV_ID) {
  344. if (rev == MV88F6192_REV_Z0)
  345. return "MV88F6192-Z0";
  346. else if (rev == MV88F6192_REV_A0)
  347. return "MV88F6192-A0";
  348. else if (rev == MV88F6192_REV_A1)
  349. return "MV88F6192-A1";
  350. else
  351. return "MV88F6192-Rev-Unsupported";
  352. } else if (dev == MV88F6180_DEV_ID) {
  353. if (rev == MV88F6180_REV_A0)
  354. return "MV88F6180-Rev-A0";
  355. else if (rev == MV88F6180_REV_A1)
  356. return "MV88F6180-Rev-A1";
  357. else
  358. return "MV88F6180-Rev-Unsupported";
  359. } else if (dev == MV88F6282_DEV_ID) {
  360. if (rev == MV88F6282_REV_A0)
  361. return "MV88F6282-Rev-A0";
  362. else if (rev == MV88F6282_REV_A1)
  363. return "MV88F6282-Rev-A1";
  364. else
  365. return "MV88F6282-Rev-Unsupported";
  366. } else {
  367. return "Device-Unknown";
  368. }
  369. }
  370. void __init kirkwood_l2_init(void)
  371. {
  372. #ifdef CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH
  373. writel(readl(L2_CONFIG_REG) | L2_WRITETHROUGH, L2_CONFIG_REG);
  374. feroceon_l2_init(1);
  375. #else
  376. writel(readl(L2_CONFIG_REG) & ~L2_WRITETHROUGH, L2_CONFIG_REG);
  377. feroceon_l2_init(0);
  378. #endif
  379. }
  380. void __init kirkwood_init(void)
  381. {
  382. printk(KERN_INFO "Kirkwood: %s, TCLK=%d.\n",
  383. kirkwood_id(), kirkwood_tclk);
  384. /*
  385. * Disable propagation of mbus errors to the CPU local bus,
  386. * as this causes mbus errors (which can occur for example
  387. * for PCI aborts) to throw CPU aborts, which we're not set
  388. * up to deal with.
  389. */
  390. writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG);
  391. kirkwood_setup_cpu_mbus();
  392. #ifdef CONFIG_CACHE_FEROCEON_L2
  393. kirkwood_l2_init();
  394. #endif
  395. /* internal devices that every board has */
  396. kirkwood_rtc_init();
  397. kirkwood_wdt_init();
  398. kirkwood_xor0_init();
  399. kirkwood_xor1_init();
  400. kirkwood_crypto_init();
  401. #ifdef CONFIG_KEXEC
  402. kexec_reinit = kirkwood_enable_pcie;
  403. #endif
  404. }
  405. static int __init kirkwood_clock_gate(void)
  406. {
  407. unsigned int curr = readl(CLOCK_GATING_CTRL);
  408. u32 dev, rev;
  409. kirkwood_pcie_id(&dev, &rev);
  410. printk(KERN_DEBUG "Gating clock of unused units\n");
  411. printk(KERN_DEBUG "before: 0x%08x\n", curr);
  412. /* Make sure those units are accessible */
  413. writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0 | CGC_PEX1, CLOCK_GATING_CTRL);
  414. /* For SATA: first shutdown the phy */
  415. if (!(kirkwood_clk_ctrl & CGC_SATA0)) {
  416. /* Disable PLL and IVREF */
  417. writel(readl(SATA0_PHY_MODE_2) & ~0xf, SATA0_PHY_MODE_2);
  418. /* Disable PHY */
  419. writel(readl(SATA0_IF_CTRL) | 0x200, SATA0_IF_CTRL);
  420. }
  421. if (!(kirkwood_clk_ctrl & CGC_SATA1)) {
  422. /* Disable PLL and IVREF */
  423. writel(readl(SATA1_PHY_MODE_2) & ~0xf, SATA1_PHY_MODE_2);
  424. /* Disable PHY */
  425. writel(readl(SATA1_IF_CTRL) | 0x200, SATA1_IF_CTRL);
  426. }
  427. /* For PCIe: first shutdown the phy */
  428. if (!(kirkwood_clk_ctrl & CGC_PEX0)) {
  429. writel(readl(PCIE_LINK_CTRL) | 0x10, PCIE_LINK_CTRL);
  430. while (1)
  431. if (readl(PCIE_STATUS) & 0x1)
  432. break;
  433. writel(readl(PCIE_LINK_CTRL) & ~0x10, PCIE_LINK_CTRL);
  434. }
  435. /* For PCIe 1: first shutdown the phy */
  436. if (dev == MV88F6282_DEV_ID) {
  437. if (!(kirkwood_clk_ctrl & CGC_PEX1)) {
  438. writel(readl(PCIE1_LINK_CTRL) | 0x10, PCIE1_LINK_CTRL);
  439. while (1)
  440. if (readl(PCIE1_STATUS) & 0x1)
  441. break;
  442. writel(readl(PCIE1_LINK_CTRL) & ~0x10, PCIE1_LINK_CTRL);
  443. }
  444. } else /* keep this bit set for devices that don't have PCIe1 */
  445. kirkwood_clk_ctrl |= CGC_PEX1;
  446. /* Now gate clock the required units */
  447. writel(kirkwood_clk_ctrl, CLOCK_GATING_CTRL);
  448. printk(KERN_DEBUG " after: 0x%08x\n", readl(CLOCK_GATING_CTRL));
  449. return 0;
  450. }
  451. late_initcall(kirkwood_clock_gate);
  452. void kirkwood_restart(char mode, const char *cmd)
  453. {
  454. /*
  455. * Enable soft reset to assert RSTOUTn.
  456. */
  457. writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
  458. /*
  459. * Assert soft reset.
  460. */
  461. writel(SOFT_RESET, SYSTEM_SOFT_RESET);
  462. while (1)
  463. ;
  464. }