/arch/arm/mach-omap2/sdram-qimonda-hyb18m512160af-6.h

https://github.com/AICP/kernel_asus_grouper · C Header · 54 lines · 37 code · 4 blank · 13 comment · 0 complexity · 944a6690f5c17f0d6bd2348fcf4e3281 MD5 · raw file 

    

  1. /*
    2. 

  2.  * SDRC register values for the Qimonda HYB18M512160AF-6
    3. 

  3.  *
    4. 

  4.  * Copyright (C) 2008-2009 Texas Instruments, Inc.
    5. 

  5.  * Copyright (C) 2008-2009 Nokia Corporation
    6. 

  6.  *
    7. 

  7.  * Paul Walmsley
    8. 

  8.  *
    9. 

  9.  * This program is free software; you can redistribute it and/or modify
    10. 

  10.  * it under the terms of the GNU General Public License version 2 as
    11. 

  11.  * published by the Free Software Foundation.
    12. 

  12.  */
    13. 

  13. 

  14. #ifndef ARCH_ARM_MACH_OMAP2_SDRAM_QIMONDA_HYB18M512160AF6
    15. 

  15. #define ARCH_ARM_MACH_OMAP2_SDRAM_QIMONDA_HYB18M512160AF6
    16. 

  16. 

  17. #include <plat/sdrc.h>
    18. 

  18. 

  19. /* Qimonda HYB18M512160AF-6 */
    20. 

  20. static struct omap_sdrc_params hyb18m512160af6_sdrc_params[] = {
    21. 

  21. 	[0] = {
    22. 

  22. 		.rate	     = 166000000,
    23. 

  23. 		.actim_ctrla = 0x629db4c6,
    24. 

  24. 		.actim_ctrlb = 0x00012214,
    25. 

  25. 		.rfr_ctrl    = 0x0004dc01,
    26. 

  26. 		.mr	     = 0x00000032,
    27. 

  27. 	},
    28. 

  28. 	[1] = {
    29. 

  29. 		.rate	     = 165941176,
    30. 

  30. 		.actim_ctrla = 0x629db4c6,
    31. 

  31. 		.actim_ctrlb = 0x00012214,
    32. 

  32. 		.rfr_ctrl    = 0x0004dc01,
    33. 

  33. 		.mr	     = 0x00000032,
    34. 

  34. 	},
    35. 

  35. 	[2] = {
    36. 

  36. 		.rate	     = 83000000,
    37. 

  37. 		.actim_ctrla = 0x31512283,
    38. 

  38. 		.actim_ctrlb = 0x0001220a,
    39. 

  39. 		.rfr_ctrl    = 0x00025501,
    40. 

  40. 		.mr	     = 0x00000022,
    41. 

  41. 	},
    42. 

  42. 	[3] = {
    43. 

  43. 		.rate	     = 82970588,
    44. 

  44. 		.actim_ctrla = 0x31512283,
    45. 

  45. 		.actim_ctrlb = 0x0001220a,
    46. 

  46. 		.rfr_ctrl    = 0x00025501,
    47. 

  47. 		.mr	     = 0x00000022,
    48. 

  48. 	},
    49. 

  49. 	[4] = {
    50. 

  50. 		.rate	     = 0
    51. 

  51. 	},
    52. 

  52. };
    53. 

  53. 

  54. #endif
    55.