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/arch/arm/mach-orion5x/include/mach/bridge-regs.h

https://github.com/AICP/kernel_asus_grouper
C Header | 39 lines | 16 code | 14 blank | 9 comment | 0 complexity | ebcc738e954ebabf1c8aa435cf18574d MD5 | raw file
 1/*
 2 * arch/arm/mach-orion5x/include/mach/bridge-regs.h
 3 *
 4 * Orion CPU Bridge Registers
 5 *
 6 * This file is licensed under the terms of the GNU General Public
 7 * License version 2. This program is licensed "as is" without any
 8 * warranty of any kind, whether express or implied.
 9 */
10
11#ifndef __ASM_ARCH_BRIDGE_REGS_H
12#define __ASM_ARCH_BRIDGE_REGS_H
13
14#include <mach/orion5x.h>
15
16#define CPU_CONF		(ORION5X_BRIDGE_VIRT_BASE | 0x100)
17
18#define CPU_CTRL		(ORION5X_BRIDGE_VIRT_BASE | 0x104)
19
20#define RSTOUTn_MASK		(ORION5X_BRIDGE_VIRT_BASE | 0x108)
21#define WDT_RESET_OUT_EN	0x0002
22
23#define CPU_SOFT_RESET		(ORION5X_BRIDGE_VIRT_BASE | 0x10c)
24
25#define BRIDGE_CAUSE		(ORION5X_BRIDGE_VIRT_BASE | 0x110)
26
27#define POWER_MNG_CTRL_REG	(ORION5X_BRIDGE_VIRT_BASE | 0x11C)
28
29#define WDT_INT_REQ		0x0008
30
31#define BRIDGE_INT_TIMER1_CLR	(~0x0004)
32
33#define MAIN_IRQ_CAUSE		(ORION5X_BRIDGE_VIRT_BASE | 0x200)
34
35#define MAIN_IRQ_MASK		(ORION5X_BRIDGE_VIRT_BASE | 0x204)
36
37#define TIMER_VIRT_BASE		(ORION5X_BRIDGE_VIRT_BASE | 0x300)
38
39#endif