/arch/arm/mach-msm/acpuclock-7x30.c

https://github.com/AICP/kernel_google_msm · C · 510 lines · 355 code · 79 blank · 76 comment · 83 complexity · 71cbd884d3b7b94e42b57df6f15200bf MD5 · raw file

  1. /*
  2. *
  3. * Copyright (C) 2007 Google, Inc.
  4. * Copyright (c) 2007-2012, The Linux Foundation. All rights reserved.
  5. *
  6. * This software is licensed under the terms of the GNU General Public
  7. * License version 2, as published by the Free Software Foundation, and
  8. * may be copied, distributed, and modified under those terms.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. */
  16. #include <linux/version.h>
  17. #include <linux/kernel.h>
  18. #include <linux/module.h>
  19. #include <linux/init.h>
  20. #include <linux/errno.h>
  21. #include <linux/string.h>
  22. #include <linux/delay.h>
  23. #include <linux/clk.h>
  24. #include <linux/cpufreq.h>
  25. #include <linux/mutex.h>
  26. #include <linux/io.h>
  27. #include <linux/sort.h>
  28. #include <linux/platform_device.h>
  29. #include <mach/board.h>
  30. #include <mach/msm_iomap.h>
  31. #include <asm/mach-types.h>
  32. #include "smd_private.h"
  33. #include "acpuclock.h"
  34. #include "spm.h"
  35. #define SCSS_CLK_CTL_ADDR (MSM_ACC0_BASE + 0x04)
  36. #define SCSS_CLK_SEL_ADDR (MSM_ACC0_BASE + 0x08)
  37. #define PLL2_L_VAL_ADDR (MSM_CLK_CTL_BASE + 0x33C)
  38. #define PLL2_M_VAL_ADDR (MSM_CLK_CTL_BASE + 0x340)
  39. #define PLL2_N_VAL_ADDR (MSM_CLK_CTL_BASE + 0x344)
  40. #define PLL2_CONFIG_ADDR (MSM_CLK_CTL_BASE + 0x34C)
  41. #define VREF_SEL 1 /* 0: 0.625V (50mV step), 1: 0.3125V (25mV step). */
  42. #define V_STEP (25 * (2 - VREF_SEL)) /* Minimum voltage step size. */
  43. #define VREG_DATA (VREG_CONFIG | (VREF_SEL << 5))
  44. #define VREG_CONFIG (BIT(7) | BIT(6)) /* Enable VREG, pull-down if disabled. */
  45. /* Cause a compile error if the voltage is not a multiple of the step size. */
  46. #define MV(mv) ((mv) / (!((mv) % V_STEP)))
  47. /* mv = (750mV + (raw * 25mV)) * (2 - VREF_SEL) */
  48. #define VDD_RAW(mv) (((MV(mv) / V_STEP) - 30) | VREG_DATA)
  49. #define MAX_AXI_KHZ 192000
  50. struct clock_state {
  51. struct clkctl_acpu_speed *current_speed;
  52. struct mutex lock;
  53. struct clk *ebi1_clk;
  54. };
  55. struct pll {
  56. unsigned int l;
  57. unsigned int m;
  58. unsigned int n;
  59. unsigned int pre_div;
  60. };
  61. struct clkctl_acpu_speed {
  62. unsigned int use_for_scaling;
  63. unsigned int acpu_clk_khz;
  64. int src;
  65. unsigned int acpu_src_sel;
  66. unsigned int acpu_src_div;
  67. unsigned int axi_clk_hz;
  68. unsigned int vdd_mv;
  69. unsigned int vdd_raw;
  70. struct pll *pll_rate;
  71. unsigned long lpj; /* loops_per_jiffy */
  72. };
  73. static struct clock_state drv_state = { 0 };
  74. /* Switch to this when reprogramming PLL2 */
  75. static struct clkctl_acpu_speed *backup_s;
  76. static struct pll pll2_tbl[] = {
  77. { 42, 0, 1, 0 }, /* 806 MHz */
  78. { 53, 1, 3, 0 }, /* 1024 MHz */
  79. { 125, 0, 1, 1 }, /* 1200 MHz */
  80. { 73, 0, 1, 0 }, /* 1401 MHz */
  81. };
  82. /* Use negative numbers for sources that can't be enabled/disabled */
  83. enum acpuclk_source {
  84. LPXO = -2,
  85. AXI = -1,
  86. PLL_0 = 0,
  87. PLL_1,
  88. PLL_2,
  89. PLL_3,
  90. MAX_SOURCE
  91. };
  92. static struct clk *acpuclk_sources[MAX_SOURCE];
  93. /*
  94. * Each ACPU frequency has a certain minimum MSMC1 voltage requirement
  95. * that is implicitly met by voting for a specific minimum AXI frequency.
  96. * Do NOT change the AXI frequency unless you are _absoulutely_ sure you
  97. * know all the h/w requirements.
  98. */
  99. static struct clkctl_acpu_speed acpu_freq_tbl[] = {
  100. { 0, 24576, LPXO, 0, 0, 30720000, 900, VDD_RAW(900) },
  101. { 0, 61440, PLL_3, 5, 11, 61440000, 900, VDD_RAW(900) },
  102. { 1, 122880, PLL_3, 5, 5, 61440000, 900, VDD_RAW(900) },
  103. { 0, 184320, PLL_3, 5, 4, 61440000, 900, VDD_RAW(900) },
  104. { 0, MAX_AXI_KHZ, AXI, 1, 0, 61440000, 900, VDD_RAW(900) },
  105. { 1, 245760, PLL_3, 5, 2, 61440000, 900, VDD_RAW(900) },
  106. { 1, 368640, PLL_3, 5, 1, 122800000, 900, VDD_RAW(900) },
  107. /* AXI has MSMC1 implications. See above. */
  108. { 1, 768000, PLL_1, 2, 0, 153600000, 1050, VDD_RAW(1050) },
  109. /*
  110. * AXI has MSMC1 implications. See above.
  111. */
  112. { 1, 806400, PLL_2, 3, 0, UINT_MAX, 1100, VDD_RAW(1100), &pll2_tbl[0]},
  113. { 1, 1024000, PLL_2, 3, 0, UINT_MAX, 1200, VDD_RAW(1200), &pll2_tbl[1]},
  114. { 1, 1200000, PLL_2, 3, 0, UINT_MAX, 1200, VDD_RAW(1200), &pll2_tbl[2]},
  115. { 1, 1401600, PLL_2, 3, 0, UINT_MAX, 1250, VDD_RAW(1250), &pll2_tbl[3]},
  116. { 0 }
  117. };
  118. static int acpuclk_set_acpu_vdd(struct clkctl_acpu_speed *s)
  119. {
  120. int ret = msm_spm_set_vdd(0, s->vdd_raw);
  121. if (ret)
  122. return ret;
  123. /* Wait for voltage to stabilize. */
  124. udelay(62);
  125. return 0;
  126. }
  127. /* Assumes PLL2 is off and the acpuclock isn't sourced from PLL2 */
  128. static void acpuclk_config_pll2(struct pll *pll)
  129. {
  130. uint32_t config = readl_relaxed(PLL2_CONFIG_ADDR);
  131. /* Make sure write to disable PLL_2 has completed
  132. * before reconfiguring that PLL. */
  133. mb();
  134. writel_relaxed(pll->l, PLL2_L_VAL_ADDR);
  135. writel_relaxed(pll->m, PLL2_M_VAL_ADDR);
  136. writel_relaxed(pll->n, PLL2_N_VAL_ADDR);
  137. if (pll->pre_div)
  138. config |= BIT(15);
  139. else
  140. config &= ~BIT(15);
  141. writel_relaxed(config, PLL2_CONFIG_ADDR);
  142. /* Make sure PLL is programmed before returning. */
  143. mb();
  144. }
  145. /* Set clock source and divider given a clock speed */
  146. static void acpuclk_set_src(const struct clkctl_acpu_speed *s)
  147. {
  148. uint32_t reg_clksel, reg_clkctl, src_sel;
  149. reg_clksel = readl_relaxed(SCSS_CLK_SEL_ADDR);
  150. /* CLK_SEL_SRC1NO */
  151. src_sel = reg_clksel & 1;
  152. /* Program clock source and divider. */
  153. reg_clkctl = readl_relaxed(SCSS_CLK_CTL_ADDR);
  154. reg_clkctl &= ~(0xFF << (8 * src_sel));
  155. reg_clkctl |= s->acpu_src_sel << (4 + 8 * src_sel);
  156. reg_clkctl |= s->acpu_src_div << (0 + 8 * src_sel);
  157. writel_relaxed(reg_clkctl, SCSS_CLK_CTL_ADDR);
  158. /* Toggle clock source. */
  159. reg_clksel ^= 1;
  160. /* Program clock source selection. */
  161. writel_relaxed(reg_clksel, SCSS_CLK_SEL_ADDR);
  162. /* Make sure switch to new source is complete. */
  163. mb();
  164. }
  165. static int acpuclk_7x30_set_rate(int cpu, unsigned long rate,
  166. enum setrate_reason reason)
  167. {
  168. struct clkctl_acpu_speed *tgt_s, *strt_s;
  169. int res, rc = 0;
  170. if (reason == SETRATE_CPUFREQ)
  171. mutex_lock(&drv_state.lock);
  172. strt_s = drv_state.current_speed;
  173. if (rate == strt_s->acpu_clk_khz)
  174. goto out;
  175. for (tgt_s = acpu_freq_tbl; tgt_s->acpu_clk_khz != 0; tgt_s++) {
  176. if (tgt_s->acpu_clk_khz == rate)
  177. break;
  178. }
  179. if (tgt_s->acpu_clk_khz == 0) {
  180. rc = -EINVAL;
  181. goto out;
  182. }
  183. if (reason == SETRATE_CPUFREQ) {
  184. /* Increase VDD if needed. */
  185. if (tgt_s->vdd_mv > strt_s->vdd_mv) {
  186. rc = acpuclk_set_acpu_vdd(tgt_s);
  187. if (rc < 0) {
  188. pr_err("ACPU VDD increase to %d mV failed "
  189. "(%d)\n", tgt_s->vdd_mv, rc);
  190. goto out;
  191. }
  192. }
  193. }
  194. pr_debug("Switching from ACPU rate %u KHz -> %u KHz\n",
  195. strt_s->acpu_clk_khz, tgt_s->acpu_clk_khz);
  196. /* Increase the AXI bus frequency if needed. This must be done before
  197. * increasing the ACPU frequency, since voting for high AXI rates
  198. * implicitly takes care of increasing the MSMC1 voltage, as needed. */
  199. if (tgt_s->axi_clk_hz > strt_s->axi_clk_hz) {
  200. rc = clk_set_rate(drv_state.ebi1_clk, tgt_s->axi_clk_hz);
  201. if (rc < 0) {
  202. pr_err("Setting AXI min rate failed (%d)\n", rc);
  203. goto out;
  204. }
  205. }
  206. /* Move off of PLL2 if we're reprogramming it */
  207. if (tgt_s->src == PLL_2 && strt_s->src == PLL_2) {
  208. clk_enable(acpuclk_sources[backup_s->src]);
  209. acpuclk_set_src(backup_s);
  210. clk_disable(acpuclk_sources[strt_s->src]);
  211. }
  212. /* Reconfigure PLL2 if we're moving to it */
  213. if (tgt_s->src == PLL_2)
  214. acpuclk_config_pll2(tgt_s->pll_rate);
  215. /* Make sure target PLL is on. */
  216. if ((strt_s->src != tgt_s->src && tgt_s->src >= 0) ||
  217. (tgt_s->src == PLL_2 && strt_s->src == PLL_2)) {
  218. pr_debug("Enabling PLL %d\n", tgt_s->src);
  219. clk_enable(acpuclk_sources[tgt_s->src]);
  220. }
  221. /* Perform the frequency switch */
  222. acpuclk_set_src(tgt_s);
  223. drv_state.current_speed = tgt_s;
  224. loops_per_jiffy = tgt_s->lpj;
  225. if (tgt_s->src == PLL_2 && strt_s->src == PLL_2)
  226. clk_disable(acpuclk_sources[backup_s->src]);
  227. /* Nothing else to do for SWFI. */
  228. if (reason == SETRATE_SWFI)
  229. goto out;
  230. /* Turn off previous PLL if not used. */
  231. if (strt_s->src != tgt_s->src && strt_s->src >= 0) {
  232. pr_debug("Disabling PLL %d\n", strt_s->src);
  233. clk_disable(acpuclk_sources[strt_s->src]);
  234. }
  235. /* Decrease the AXI bus frequency if we can. */
  236. if (tgt_s->axi_clk_hz < strt_s->axi_clk_hz) {
  237. res = clk_set_rate(drv_state.ebi1_clk, tgt_s->axi_clk_hz);
  238. if (res < 0)
  239. pr_warning("Setting AXI min rate failed (%d)\n", res);
  240. }
  241. /* Nothing else to do for power collapse. */
  242. if (reason == SETRATE_PC)
  243. goto out;
  244. /* Drop VDD level if we can. */
  245. if (tgt_s->vdd_mv < strt_s->vdd_mv) {
  246. res = acpuclk_set_acpu_vdd(tgt_s);
  247. if (res)
  248. pr_warning("ACPU VDD decrease to %d mV failed (%d)\n",
  249. tgt_s->vdd_mv, res);
  250. }
  251. pr_debug("ACPU speed change complete\n");
  252. out:
  253. if (reason == SETRATE_CPUFREQ)
  254. mutex_unlock(&drv_state.lock);
  255. return rc;
  256. }
  257. static unsigned long acpuclk_7x30_get_rate(int cpu)
  258. {
  259. WARN_ONCE(drv_state.current_speed == NULL,
  260. "acpuclk_get_rate: not initialized\n");
  261. if (drv_state.current_speed)
  262. return drv_state.current_speed->acpu_clk_khz;
  263. else
  264. return 0;
  265. }
  266. /*----------------------------------------------------------------------------
  267. * Clock driver initialization
  268. *---------------------------------------------------------------------------*/
  269. static void __devinit acpuclk_hw_init(void)
  270. {
  271. struct clkctl_acpu_speed *s;
  272. uint32_t div, sel, src_num;
  273. uint32_t reg_clksel, reg_clkctl;
  274. int res;
  275. u8 pll2_l = readl_relaxed(PLL2_L_VAL_ADDR) & 0xFF;
  276. drv_state.ebi1_clk = clk_get(NULL, "ebi1_clk");
  277. BUG_ON(IS_ERR(drv_state.ebi1_clk));
  278. reg_clksel = readl_relaxed(SCSS_CLK_SEL_ADDR);
  279. /* Determine the ACPU clock rate. */
  280. switch ((reg_clksel >> 1) & 0x3) {
  281. case 0: /* Running off the output of the raw clock source mux. */
  282. reg_clkctl = readl_relaxed(SCSS_CLK_CTL_ADDR);
  283. src_num = reg_clksel & 0x1;
  284. sel = (reg_clkctl >> (12 - (8 * src_num))) & 0x7;
  285. div = (reg_clkctl >> (8 - (8 * src_num))) & 0xF;
  286. /* Check frequency table for matching sel/div pair. */
  287. for (s = acpu_freq_tbl; s->acpu_clk_khz != 0; s++) {
  288. if (s->acpu_src_sel == sel && s->acpu_src_div == div)
  289. break;
  290. }
  291. if (s->acpu_clk_khz == 0) {
  292. pr_err("Error - ACPU clock reports invalid speed\n");
  293. return;
  294. }
  295. break;
  296. case 2: /* Running off of the SCPLL selected through the core mux. */
  297. /* Switch to run off of the SCPLL selected through the raw
  298. * clock source mux. */
  299. for (s = acpu_freq_tbl; s->acpu_clk_khz != 0
  300. && s->src != PLL_2 && s->acpu_src_div == 0; s++)
  301. ;
  302. if (s->acpu_clk_khz != 0) {
  303. /* Program raw clock source mux. */
  304. acpuclk_set_src(s);
  305. /* Switch to raw clock source input of the core mux. */
  306. reg_clksel = readl_relaxed(SCSS_CLK_SEL_ADDR);
  307. reg_clksel &= ~(0x3 << 1);
  308. writel_relaxed(reg_clksel, SCSS_CLK_SEL_ADDR);
  309. break;
  310. }
  311. /* else fall through */
  312. default:
  313. pr_err("Error - ACPU clock reports invalid source\n");
  314. return;
  315. }
  316. /* Look at PLL2's L val to determine what speed PLL2 is running at */
  317. if (s->src == PLL_2)
  318. for ( ; s->acpu_clk_khz; s++)
  319. if (s->pll_rate && s->pll_rate->l == pll2_l)
  320. break;
  321. /* Set initial ACPU VDD. */
  322. acpuclk_set_acpu_vdd(s);
  323. drv_state.current_speed = s;
  324. /* Initialize current PLL's reference count. */
  325. if (s->src >= 0)
  326. clk_enable(acpuclk_sources[s->src]);
  327. res = clk_set_rate(drv_state.ebi1_clk, s->axi_clk_hz);
  328. if (res < 0)
  329. pr_warning("Setting AXI min rate failed!\n");
  330. pr_info("ACPU running at %d KHz\n", s->acpu_clk_khz);
  331. return;
  332. }
  333. /* Initalize the lpj field in the acpu_freq_tbl. */
  334. static void __devinit lpj_init(void)
  335. {
  336. int i;
  337. const struct clkctl_acpu_speed *base_clk = drv_state.current_speed;
  338. for (i = 0; acpu_freq_tbl[i].acpu_clk_khz; i++) {
  339. acpu_freq_tbl[i].lpj = cpufreq_scale(loops_per_jiffy,
  340. base_clk->acpu_clk_khz,
  341. acpu_freq_tbl[i].acpu_clk_khz);
  342. }
  343. }
  344. #ifdef CONFIG_CPU_FREQ_MSM
  345. static struct cpufreq_frequency_table cpufreq_tbl[ARRAY_SIZE(acpu_freq_tbl)];
  346. static void setup_cpufreq_table(void)
  347. {
  348. unsigned i = 0;
  349. const struct clkctl_acpu_speed *speed;
  350. for (speed = acpu_freq_tbl; speed->acpu_clk_khz; speed++)
  351. if (speed->use_for_scaling) {
  352. cpufreq_tbl[i].index = i;
  353. cpufreq_tbl[i].frequency = speed->acpu_clk_khz;
  354. i++;
  355. }
  356. cpufreq_tbl[i].frequency = CPUFREQ_TABLE_END;
  357. cpufreq_frequency_table_get_attr(cpufreq_tbl, smp_processor_id());
  358. }
  359. #else
  360. static inline void setup_cpufreq_table(void) { }
  361. #endif
  362. /*
  363. * Truncate the frequency table at the current PLL2 rate and determine the
  364. * backup PLL to use when scaling PLL2.
  365. */
  366. void __devinit pll2_fixup(void)
  367. {
  368. struct clkctl_acpu_speed *speed = acpu_freq_tbl;
  369. u8 pll2_l = readl_relaxed(PLL2_L_VAL_ADDR) & 0xFF;
  370. for ( ; speed->acpu_clk_khz; speed++) {
  371. if (speed->src != PLL_2)
  372. backup_s = speed;
  373. if (speed->pll_rate && speed->pll_rate->l == pll2_l) {
  374. speed++;
  375. speed->acpu_clk_khz = 0;
  376. return;
  377. }
  378. }
  379. pr_err("Unknown PLL2 lval %d\n", pll2_l);
  380. BUG();
  381. }
  382. #define RPM_BYPASS_MASK (1 << 3)
  383. #define PMIC_MODE_MASK (1 << 4)
  384. static void __devinit populate_plls(void)
  385. {
  386. acpuclk_sources[PLL_1] = clk_get_sys("acpu", "pll1_clk");
  387. BUG_ON(IS_ERR(acpuclk_sources[PLL_1]));
  388. acpuclk_sources[PLL_2] = clk_get_sys("acpu", "pll2_clk");
  389. BUG_ON(IS_ERR(acpuclk_sources[PLL_2]));
  390. acpuclk_sources[PLL_3] = clk_get_sys("acpu", "pll3_clk");
  391. BUG_ON(IS_ERR(acpuclk_sources[PLL_3]));
  392. /*
  393. * Prepare all the PLLs because we enable/disable them
  394. * from atomic context and can't always ensure they're
  395. * all prepared in non-atomic context.
  396. */
  397. BUG_ON(clk_prepare(acpuclk_sources[PLL_1]));
  398. BUG_ON(clk_prepare(acpuclk_sources[PLL_2]));
  399. BUG_ON(clk_prepare(acpuclk_sources[PLL_3]));
  400. }
  401. static struct acpuclk_data acpuclk_7x30_data = {
  402. .set_rate = acpuclk_7x30_set_rate,
  403. .get_rate = acpuclk_7x30_get_rate,
  404. .power_collapse_khz = MAX_AXI_KHZ,
  405. .wait_for_irq_khz = MAX_AXI_KHZ,
  406. .switch_time_us = 50,
  407. };
  408. static int __devinit acpuclk_7x30_probe(struct platform_device *pdev)
  409. {
  410. pr_info("%s()\n", __func__);
  411. mutex_init(&drv_state.lock);
  412. pll2_fixup();
  413. populate_plls();
  414. acpuclk_hw_init();
  415. lpj_init();
  416. setup_cpufreq_table();
  417. acpuclk_register(&acpuclk_7x30_data);
  418. return 0;
  419. }
  420. static struct platform_driver acpuclk_7x30_driver = {
  421. .probe = acpuclk_7x30_probe,
  422. .driver = {
  423. .name = "acpuclk-7x30",
  424. .owner = THIS_MODULE,
  425. },
  426. };
  427. static int __init acpuclk_7x30_init(void)
  428. {
  429. return platform_driver_register(&acpuclk_7x30_driver);
  430. }
  431. postcore_initcall(acpuclk_7x30_init);