/arch/arm/mach-msm/acpuclock-8930.c

https://github.com/AICP/kernel_google_msm · C · 254 lines · 223 code · 18 blank · 13 comment · 2 complexity · d1da0fafb36a8596800c8ce5a2d225e8 MD5 · raw file

  1. /*
  2. * Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 and
  6. * only version 2 as published by the Free Software Foundation.
  7. *
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. */
  13. #include <linux/kernel.h>
  14. #include <linux/module.h>
  15. #include <linux/platform_device.h>
  16. #include <mach/rpm-regulator.h>
  17. #include <mach/msm_bus_board.h>
  18. #include <mach/msm_bus.h>
  19. #include "acpuclock.h"
  20. #include "acpuclock-krait.h"
  21. /* Corner type vreg VDD values */
  22. #define LVL_NONE RPM_VREG_CORNER_NONE
  23. #define LVL_LOW RPM_VREG_CORNER_LOW
  24. #define LVL_NOM RPM_VREG_CORNER_NOMINAL
  25. #define LVL_HIGH RPM_VREG_CORNER_HIGH
  26. static struct hfpll_data hfpll_data __initdata = {
  27. .mode_offset = 0x00,
  28. .l_offset = 0x08,
  29. .m_offset = 0x0C,
  30. .n_offset = 0x10,
  31. .config_offset = 0x04,
  32. .config_val = 0x7845C665,
  33. .has_droop_ctl = true,
  34. .droop_offset = 0x14,
  35. .droop_val = 0x0108C000,
  36. .low_vdd_l_max = 22,
  37. .nom_vdd_l_max = 42,
  38. .vdd[HFPLL_VDD_NONE] = LVL_NONE,
  39. .vdd[HFPLL_VDD_LOW] = LVL_LOW,
  40. .vdd[HFPLL_VDD_NOM] = LVL_NOM,
  41. .vdd[HFPLL_VDD_HIGH] = LVL_HIGH,
  42. };
  43. static struct scalable scalable_pm8917[] __initdata = {
  44. [CPU0] = {
  45. .hfpll_phys_base = 0x00903200,
  46. .aux_clk_sel_phys = 0x02088014,
  47. .aux_clk_sel = 3,
  48. .sec_clk_sel = 2,
  49. .l2cpmr_iaddr = 0x4501,
  50. .vreg[VREG_CORE] = { "krait0", 1300000 },
  51. .vreg[VREG_MEM] = { "krait0_mem", 1150000 },
  52. .vreg[VREG_DIG] = { "krait0_dig", 1150000 },
  53. .vreg[VREG_HFPLL_A] = { "krait0_s8", 2050000 },
  54. .vreg[VREG_HFPLL_B] = { "krait0_l23", 1800000 },
  55. },
  56. [CPU1] = {
  57. .hfpll_phys_base = 0x00903300,
  58. .aux_clk_sel_phys = 0x02098014,
  59. .aux_clk_sel = 3,
  60. .sec_clk_sel = 2,
  61. .l2cpmr_iaddr = 0x5501,
  62. .vreg[VREG_CORE] = { "krait1", 1300000 },
  63. .vreg[VREG_MEM] = { "krait1_mem", 1150000 },
  64. .vreg[VREG_DIG] = { "krait1_dig", 1150000 },
  65. .vreg[VREG_HFPLL_A] = { "krait1_s8", 2050000 },
  66. .vreg[VREG_HFPLL_B] = { "krait1_l23", 1800000 },
  67. },
  68. [L2] = {
  69. .hfpll_phys_base = 0x00903400,
  70. .aux_clk_sel_phys = 0x02011028,
  71. .aux_clk_sel = 3,
  72. .sec_clk_sel = 2,
  73. .l2cpmr_iaddr = 0x0500,
  74. .vreg[VREG_HFPLL_A] = { "l2_s8", 2050000 },
  75. .vreg[VREG_HFPLL_B] = { "l2_l23", 1800000 },
  76. },
  77. };
  78. static struct scalable scalable[] __initdata = {
  79. [CPU0] = {
  80. .hfpll_phys_base = 0x00903200,
  81. .aux_clk_sel_phys = 0x02088014,
  82. .aux_clk_sel = 3,
  83. .sec_clk_sel = 2,
  84. .l2cpmr_iaddr = 0x4501,
  85. .vreg[VREG_CORE] = { "krait0", 1300000 },
  86. .vreg[VREG_MEM] = { "krait0_mem", 1150000 },
  87. .vreg[VREG_DIG] = { "krait0_dig", 1150000 },
  88. .vreg[VREG_HFPLL_A] = { "krait0_hfpll", 1800000 },
  89. },
  90. [CPU1] = {
  91. .hfpll_phys_base = 0x00903300,
  92. .aux_clk_sel_phys = 0x02098014,
  93. .aux_clk_sel = 3,
  94. .sec_clk_sel = 2,
  95. .l2cpmr_iaddr = 0x5501,
  96. .vreg[VREG_CORE] = { "krait1", 1300000 },
  97. .vreg[VREG_MEM] = { "krait1_mem", 1150000 },
  98. .vreg[VREG_DIG] = { "krait1_dig", 1150000 },
  99. .vreg[VREG_HFPLL_A] = { "krait1_hfpll", 1800000 },
  100. },
  101. [L2] = {
  102. .hfpll_phys_base = 0x00903400,
  103. .aux_clk_sel_phys = 0x02011028,
  104. .aux_clk_sel = 3,
  105. .sec_clk_sel = 2,
  106. .l2cpmr_iaddr = 0x0500,
  107. .vreg[VREG_HFPLL_A] = { "l2_hfpll", 1800000 },
  108. },
  109. };
  110. static struct msm_bus_paths bw_level_tbl[] __initdata = {
  111. [0] = BW_MBPS(640), /* At least 80 MHz on bus. */
  112. [1] = BW_MBPS(1064), /* At least 133 MHz on bus. */
  113. [2] = BW_MBPS(1600), /* At least 200 MHz on bus. */
  114. [3] = BW_MBPS(2128), /* At least 266 MHz on bus. */
  115. [4] = BW_MBPS(3200), /* At least 400 MHz on bus. */
  116. [5] = BW_MBPS(3600), /* At least 450 MHz on bus. */
  117. [6] = BW_MBPS(3936), /* At least 492 MHz on bus. */
  118. [7] = BW_MBPS(4264), /* At least 533 MHz on bus. */
  119. };
  120. static struct msm_bus_scale_pdata bus_scale_data __initdata = {
  121. .usecase = bw_level_tbl,
  122. .num_usecases = ARRAY_SIZE(bw_level_tbl),
  123. .active_only = 1,
  124. .name = "acpuclk-8930",
  125. };
  126. static struct l2_level l2_freq_tbl[] __initdata = {
  127. [0] = { { 384000, PLL_8, 0, 0x00 }, LVL_LOW, 1050000, 1 },
  128. [1] = { { 432000, HFPLL, 2, 0x20 }, LVL_NOM, 1050000, 2 },
  129. [2] = { { 486000, HFPLL, 2, 0x24 }, LVL_NOM, 1050000, 2 },
  130. [3] = { { 540000, HFPLL, 2, 0x28 }, LVL_NOM, 1050000, 2 },
  131. [4] = { { 594000, HFPLL, 1, 0x16 }, LVL_NOM, 1050000, 2 },
  132. [5] = { { 648000, HFPLL, 1, 0x18 }, LVL_NOM, 1050000, 4 },
  133. [6] = { { 702000, HFPLL, 1, 0x1A }, LVL_NOM, 1050000, 4 },
  134. [7] = { { 756000, HFPLL, 1, 0x1C }, LVL_HIGH, 1150000, 4 },
  135. [8] = { { 810000, HFPLL, 1, 0x1E }, LVL_HIGH, 1150000, 4 },
  136. [9] = { { 864000, HFPLL, 1, 0x20 }, LVL_HIGH, 1150000, 4 },
  137. [10] = { { 918000, HFPLL, 1, 0x22 }, LVL_HIGH, 1150000, 7 },
  138. [11] = { { 972000, HFPLL, 1, 0x24 }, LVL_HIGH, 1150000, 7 },
  139. [12] = { { 1026000, HFPLL, 1, 0x26 }, LVL_HIGH, 1150000, 7 },
  140. [13] = { { 1080000, HFPLL, 1, 0x28 }, LVL_HIGH, 1150000, 7 },
  141. [14] = { { 1134000, HFPLL, 1, 0x2A }, LVL_HIGH, 1150000, 7 },
  142. [15] = { { 1188000, HFPLL, 1, 0x2C }, LVL_HIGH, 1150000, 7 },
  143. { }
  144. };
  145. static struct acpu_level acpu_freq_tbl_slow[] __initdata = {
  146. { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 },
  147. { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 975000 },
  148. { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 975000 },
  149. { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 1000000 },
  150. { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 1000000 },
  151. { 0, { 648000, HFPLL, 1, 0x18 }, L2(5), 1025000 },
  152. { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 1025000 },
  153. { 0, { 756000, HFPLL, 1, 0x1C }, L2(10), 1075000 },
  154. { 1, { 810000, HFPLL, 1, 0x1E }, L2(10), 1075000 },
  155. { 0, { 864000, HFPLL, 1, 0x20 }, L2(10), 1100000 },
  156. { 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 1100000 },
  157. { 0, { 972000, HFPLL, 1, 0x24 }, L2(10), 1125000 },
  158. { 1, { 1026000, HFPLL, 1, 0x26 }, L2(10), 1125000 },
  159. { 0, { 1080000, HFPLL, 1, 0x28 }, L2(15), 1175000 },
  160. { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1175000 },
  161. { 1, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1200000 },
  162. { 0, { 0 } }
  163. };
  164. static struct acpu_level acpu_freq_tbl_nom[] __initdata = {
  165. { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 925000 },
  166. { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 950000 },
  167. { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 950000 },
  168. { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 975000 },
  169. { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 975000 },
  170. { 0, { 648000, HFPLL, 1, 0x18 }, L2(5), 1000000 },
  171. { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 1000000 },
  172. { 0, { 756000, HFPLL, 1, 0x1C }, L2(10), 1050000 },
  173. { 1, { 810000, HFPLL, 1, 0x1E }, L2(10), 1050000 },
  174. { 0, { 864000, HFPLL, 1, 0x20 }, L2(10), 1075000 },
  175. { 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 1075000 },
  176. { 0, { 972000, HFPLL, 1, 0x24 }, L2(10), 1100000 },
  177. { 1, { 1026000, HFPLL, 1, 0x26 }, L2(10), 1100000 },
  178. { 0, { 1080000, HFPLL, 1, 0x28 }, L2(15), 1150000 },
  179. { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1150000 },
  180. { 1, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1175000 },
  181. { 0, { 0 } }
  182. };
  183. static struct acpu_level acpu_freq_tbl_fast[] __initdata = {
  184. { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 },
  185. { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 900000 },
  186. { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 900000 },
  187. { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 925000 },
  188. { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 925000 },
  189. { 0, { 648000, HFPLL, 1, 0x18 }, L2(5), 950000 },
  190. { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 950000 },
  191. { 0, { 756000, HFPLL, 1, 0x1C }, L2(10), 1000000 },
  192. { 1, { 810000, HFPLL, 1, 0x1E }, L2(10), 1000000 },
  193. { 0, { 864000, HFPLL, 1, 0x20 }, L2(10), 1025000 },
  194. { 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 1025000 },
  195. { 0, { 972000, HFPLL, 1, 0x24 }, L2(10), 1050000 },
  196. { 1, { 1026000, HFPLL, 1, 0x26 }, L2(10), 1050000 },
  197. { 0, { 1080000, HFPLL, 1, 0x28 }, L2(15), 1100000 },
  198. { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1100000 },
  199. { 1, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1125000 },
  200. { 0, { 0 } }
  201. };
  202. static struct pvs_table pvs_tables[NUM_SPEED_BINS][NUM_PVS] __initdata = {
  203. [0][PVS_SLOW] = { acpu_freq_tbl_slow, sizeof(acpu_freq_tbl_slow), 0 },
  204. [0][PVS_NOMINAL] = { acpu_freq_tbl_nom, sizeof(acpu_freq_tbl_nom), 25000 },
  205. [0][PVS_FAST] = { acpu_freq_tbl_fast, sizeof(acpu_freq_tbl_fast), 25000 },
  206. };
  207. static struct acpuclk_krait_params acpuclk_8930_params __initdata = {
  208. .scalable = scalable,
  209. .scalable_size = sizeof(scalable),
  210. .hfpll_data = &hfpll_data,
  211. .pvs_tables = pvs_tables,
  212. .l2_freq_tbl = l2_freq_tbl,
  213. .l2_freq_tbl_size = sizeof(l2_freq_tbl),
  214. .bus_scale = &bus_scale_data,
  215. .pte_efuse_phys = 0x007000C0,
  216. .stby_khz = 384000,
  217. };
  218. static int __init acpuclk_8930_probe(struct platform_device *pdev)
  219. {
  220. struct acpuclk_platform_data *pdata = pdev->dev.platform_data;
  221. if (pdata && pdata->uses_pm8917)
  222. acpuclk_8930_params.scalable = scalable_pm8917;
  223. return acpuclk_krait_init(&pdev->dev, &acpuclk_8930_params);
  224. }
  225. static struct platform_driver acpuclk_8930_driver = {
  226. .driver = {
  227. .name = "acpuclk-8930",
  228. .owner = THIS_MODULE,
  229. },
  230. };
  231. static int __init acpuclk_8930_init(void)
  232. {
  233. return platform_driver_probe(&acpuclk_8930_driver,
  234. acpuclk_8930_probe);
  235. }
  236. device_initcall(acpuclk_8930_init);