/arch/arm/mach-msm/acpuclock-8930.c
C | 254 lines | 223 code | 18 blank | 13 comment | 2 complexity | d1da0fafb36a8596800c8ce5a2d225e8 MD5 | raw file
1/* 2 * Copyright (c) 2011-2012, The Linux Foundation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 and 6 * only version 2 as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14#include <linux/kernel.h> 15#include <linux/module.h> 16#include <linux/platform_device.h> 17#include <mach/rpm-regulator.h> 18#include <mach/msm_bus_board.h> 19#include <mach/msm_bus.h> 20 21#include "acpuclock.h" 22#include "acpuclock-krait.h" 23 24/* Corner type vreg VDD values */ 25#define LVL_NONE RPM_VREG_CORNER_NONE 26#define LVL_LOW RPM_VREG_CORNER_LOW 27#define LVL_NOM RPM_VREG_CORNER_NOMINAL 28#define LVL_HIGH RPM_VREG_CORNER_HIGH 29 30static struct hfpll_data hfpll_data __initdata = { 31 .mode_offset = 0x00, 32 .l_offset = 0x08, 33 .m_offset = 0x0C, 34 .n_offset = 0x10, 35 .config_offset = 0x04, 36 .config_val = 0x7845C665, 37 .has_droop_ctl = true, 38 .droop_offset = 0x14, 39 .droop_val = 0x0108C000, 40 .low_vdd_l_max = 22, 41 .nom_vdd_l_max = 42, 42 .vdd[HFPLL_VDD_NONE] = LVL_NONE, 43 .vdd[HFPLL_VDD_LOW] = LVL_LOW, 44 .vdd[HFPLL_VDD_NOM] = LVL_NOM, 45 .vdd[HFPLL_VDD_HIGH] = LVL_HIGH, 46}; 47 48static struct scalable scalable_pm8917[] __initdata = { 49 [CPU0] = { 50 .hfpll_phys_base = 0x00903200, 51 .aux_clk_sel_phys = 0x02088014, 52 .aux_clk_sel = 3, 53 .sec_clk_sel = 2, 54 .l2cpmr_iaddr = 0x4501, 55 .vreg[VREG_CORE] = { "krait0", 1300000 }, 56 .vreg[VREG_MEM] = { "krait0_mem", 1150000 }, 57 .vreg[VREG_DIG] = { "krait0_dig", 1150000 }, 58 .vreg[VREG_HFPLL_A] = { "krait0_s8", 2050000 }, 59 .vreg[VREG_HFPLL_B] = { "krait0_l23", 1800000 }, 60 }, 61 [CPU1] = { 62 .hfpll_phys_base = 0x00903300, 63 .aux_clk_sel_phys = 0x02098014, 64 .aux_clk_sel = 3, 65 .sec_clk_sel = 2, 66 .l2cpmr_iaddr = 0x5501, 67 .vreg[VREG_CORE] = { "krait1", 1300000 }, 68 .vreg[VREG_MEM] = { "krait1_mem", 1150000 }, 69 .vreg[VREG_DIG] = { "krait1_dig", 1150000 }, 70 .vreg[VREG_HFPLL_A] = { "krait1_s8", 2050000 }, 71 .vreg[VREG_HFPLL_B] = { "krait1_l23", 1800000 }, 72 }, 73 [L2] = { 74 .hfpll_phys_base = 0x00903400, 75 .aux_clk_sel_phys = 0x02011028, 76 .aux_clk_sel = 3, 77 .sec_clk_sel = 2, 78 .l2cpmr_iaddr = 0x0500, 79 .vreg[VREG_HFPLL_A] = { "l2_s8", 2050000 }, 80 .vreg[VREG_HFPLL_B] = { "l2_l23", 1800000 }, 81 }, 82}; 83 84static struct scalable scalable[] __initdata = { 85 [CPU0] = { 86 .hfpll_phys_base = 0x00903200, 87 .aux_clk_sel_phys = 0x02088014, 88 .aux_clk_sel = 3, 89 .sec_clk_sel = 2, 90 .l2cpmr_iaddr = 0x4501, 91 .vreg[VREG_CORE] = { "krait0", 1300000 }, 92 .vreg[VREG_MEM] = { "krait0_mem", 1150000 }, 93 .vreg[VREG_DIG] = { "krait0_dig", 1150000 }, 94 .vreg[VREG_HFPLL_A] = { "krait0_hfpll", 1800000 }, 95 }, 96 [CPU1] = { 97 .hfpll_phys_base = 0x00903300, 98 .aux_clk_sel_phys = 0x02098014, 99 .aux_clk_sel = 3, 100 .sec_clk_sel = 2, 101 .l2cpmr_iaddr = 0x5501, 102 .vreg[VREG_CORE] = { "krait1", 1300000 }, 103 .vreg[VREG_MEM] = { "krait1_mem", 1150000 }, 104 .vreg[VREG_DIG] = { "krait1_dig", 1150000 }, 105 .vreg[VREG_HFPLL_A] = { "krait1_hfpll", 1800000 }, 106 }, 107 [L2] = { 108 .hfpll_phys_base = 0x00903400, 109 .aux_clk_sel_phys = 0x02011028, 110 .aux_clk_sel = 3, 111 .sec_clk_sel = 2, 112 .l2cpmr_iaddr = 0x0500, 113 .vreg[VREG_HFPLL_A] = { "l2_hfpll", 1800000 }, 114 }, 115}; 116 117static struct msm_bus_paths bw_level_tbl[] __initdata = { 118 [0] = BW_MBPS(640), /* At least 80 MHz on bus. */ 119 [1] = BW_MBPS(1064), /* At least 133 MHz on bus. */ 120 [2] = BW_MBPS(1600), /* At least 200 MHz on bus. */ 121 [3] = BW_MBPS(2128), /* At least 266 MHz on bus. */ 122 [4] = BW_MBPS(3200), /* At least 400 MHz on bus. */ 123 [5] = BW_MBPS(3600), /* At least 450 MHz on bus. */ 124 [6] = BW_MBPS(3936), /* At least 492 MHz on bus. */ 125 [7] = BW_MBPS(4264), /* At least 533 MHz on bus. */ 126}; 127 128static struct msm_bus_scale_pdata bus_scale_data __initdata = { 129 .usecase = bw_level_tbl, 130 .num_usecases = ARRAY_SIZE(bw_level_tbl), 131 .active_only = 1, 132 .name = "acpuclk-8930", 133}; 134 135static struct l2_level l2_freq_tbl[] __initdata = { 136 [0] = { { 384000, PLL_8, 0, 0x00 }, LVL_LOW, 1050000, 1 }, 137 [1] = { { 432000, HFPLL, 2, 0x20 }, LVL_NOM, 1050000, 2 }, 138 [2] = { { 486000, HFPLL, 2, 0x24 }, LVL_NOM, 1050000, 2 }, 139 [3] = { { 540000, HFPLL, 2, 0x28 }, LVL_NOM, 1050000, 2 }, 140 [4] = { { 594000, HFPLL, 1, 0x16 }, LVL_NOM, 1050000, 2 }, 141 [5] = { { 648000, HFPLL, 1, 0x18 }, LVL_NOM, 1050000, 4 }, 142 [6] = { { 702000, HFPLL, 1, 0x1A }, LVL_NOM, 1050000, 4 }, 143 [7] = { { 756000, HFPLL, 1, 0x1C }, LVL_HIGH, 1150000, 4 }, 144 [8] = { { 810000, HFPLL, 1, 0x1E }, LVL_HIGH, 1150000, 4 }, 145 [9] = { { 864000, HFPLL, 1, 0x20 }, LVL_HIGH, 1150000, 4 }, 146 [10] = { { 918000, HFPLL, 1, 0x22 }, LVL_HIGH, 1150000, 7 }, 147 [11] = { { 972000, HFPLL, 1, 0x24 }, LVL_HIGH, 1150000, 7 }, 148 [12] = { { 1026000, HFPLL, 1, 0x26 }, LVL_HIGH, 1150000, 7 }, 149 [13] = { { 1080000, HFPLL, 1, 0x28 }, LVL_HIGH, 1150000, 7 }, 150 [14] = { { 1134000, HFPLL, 1, 0x2A }, LVL_HIGH, 1150000, 7 }, 151 [15] = { { 1188000, HFPLL, 1, 0x2C }, LVL_HIGH, 1150000, 7 }, 152 { } 153}; 154 155static struct acpu_level acpu_freq_tbl_slow[] __initdata = { 156 { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 }, 157 { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 975000 }, 158 { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 975000 }, 159 { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 1000000 }, 160 { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 1000000 }, 161 { 0, { 648000, HFPLL, 1, 0x18 }, L2(5), 1025000 }, 162 { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 1025000 }, 163 { 0, { 756000, HFPLL, 1, 0x1C }, L2(10), 1075000 }, 164 { 1, { 810000, HFPLL, 1, 0x1E }, L2(10), 1075000 }, 165 { 0, { 864000, HFPLL, 1, 0x20 }, L2(10), 1100000 }, 166 { 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 1100000 }, 167 { 0, { 972000, HFPLL, 1, 0x24 }, L2(10), 1125000 }, 168 { 1, { 1026000, HFPLL, 1, 0x26 }, L2(10), 1125000 }, 169 { 0, { 1080000, HFPLL, 1, 0x28 }, L2(15), 1175000 }, 170 { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1175000 }, 171 { 1, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1200000 }, 172 { 0, { 0 } } 173}; 174 175static struct acpu_level acpu_freq_tbl_nom[] __initdata = { 176 { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 925000 }, 177 { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 950000 }, 178 { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 950000 }, 179 { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 975000 }, 180 { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 975000 }, 181 { 0, { 648000, HFPLL, 1, 0x18 }, L2(5), 1000000 }, 182 { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 1000000 }, 183 { 0, { 756000, HFPLL, 1, 0x1C }, L2(10), 1050000 }, 184 { 1, { 810000, HFPLL, 1, 0x1E }, L2(10), 1050000 }, 185 { 0, { 864000, HFPLL, 1, 0x20 }, L2(10), 1075000 }, 186 { 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 1075000 }, 187 { 0, { 972000, HFPLL, 1, 0x24 }, L2(10), 1100000 }, 188 { 1, { 1026000, HFPLL, 1, 0x26 }, L2(10), 1100000 }, 189 { 0, { 1080000, HFPLL, 1, 0x28 }, L2(15), 1150000 }, 190 { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1150000 }, 191 { 1, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1175000 }, 192 { 0, { 0 } } 193}; 194 195static struct acpu_level acpu_freq_tbl_fast[] __initdata = { 196 { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 }, 197 { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 900000 }, 198 { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 900000 }, 199 { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 925000 }, 200 { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 925000 }, 201 { 0, { 648000, HFPLL, 1, 0x18 }, L2(5), 950000 }, 202 { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 950000 }, 203 { 0, { 756000, HFPLL, 1, 0x1C }, L2(10), 1000000 }, 204 { 1, { 810000, HFPLL, 1, 0x1E }, L2(10), 1000000 }, 205 { 0, { 864000, HFPLL, 1, 0x20 }, L2(10), 1025000 }, 206 { 1, { 918000, HFPLL, 1, 0x22 }, L2(10), 1025000 }, 207 { 0, { 972000, HFPLL, 1, 0x24 }, L2(10), 1050000 }, 208 { 1, { 1026000, HFPLL, 1, 0x26 }, L2(10), 1050000 }, 209 { 0, { 1080000, HFPLL, 1, 0x28 }, L2(15), 1100000 }, 210 { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1100000 }, 211 { 1, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1125000 }, 212 { 0, { 0 } } 213}; 214 215static struct pvs_table pvs_tables[NUM_SPEED_BINS][NUM_PVS] __initdata = { 216[0][PVS_SLOW] = { acpu_freq_tbl_slow, sizeof(acpu_freq_tbl_slow), 0 }, 217[0][PVS_NOMINAL] = { acpu_freq_tbl_nom, sizeof(acpu_freq_tbl_nom), 25000 }, 218[0][PVS_FAST] = { acpu_freq_tbl_fast, sizeof(acpu_freq_tbl_fast), 25000 }, 219}; 220 221static struct acpuclk_krait_params acpuclk_8930_params __initdata = { 222 .scalable = scalable, 223 .scalable_size = sizeof(scalable), 224 .hfpll_data = &hfpll_data, 225 .pvs_tables = pvs_tables, 226 .l2_freq_tbl = l2_freq_tbl, 227 .l2_freq_tbl_size = sizeof(l2_freq_tbl), 228 .bus_scale = &bus_scale_data, 229 .pte_efuse_phys = 0x007000C0, 230 .stby_khz = 384000, 231}; 232 233static int __init acpuclk_8930_probe(struct platform_device *pdev) 234{ 235 struct acpuclk_platform_data *pdata = pdev->dev.platform_data; 236 if (pdata && pdata->uses_pm8917) 237 acpuclk_8930_params.scalable = scalable_pm8917; 238 239 return acpuclk_krait_init(&pdev->dev, &acpuclk_8930_params); 240} 241 242static struct platform_driver acpuclk_8930_driver = { 243 .driver = { 244 .name = "acpuclk-8930", 245 .owner = THIS_MODULE, 246 }, 247}; 248 249static int __init acpuclk_8930_init(void) 250{ 251 return platform_driver_probe(&acpuclk_8930_driver, 252 acpuclk_8930_probe); 253} 254device_initcall(acpuclk_8930_init);