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/include/linux/mfd/ezx-pcap.h

https://github.com/airy09/android_kernel_sony_apq8064
C Header | 252 lines | 216 code | 23 blank | 13 comment | 0 complexity | 7aa828d1db935636405fcfdb3965522f MD5 | raw file
  1/*
  2 * Copyright 2009 Daniel Ribeiro <drwyrm@gmail.com>
  3 *
  4 * For further information, please see http://wiki.openezx.org/PCAP2
  5 */
  6
  7#ifndef EZX_PCAP_H
  8#define EZX_PCAP_H
  9
 10struct pcap_subdev {
 11	int id;
 12	const char *name;
 13	void *platform_data;
 14};
 15
 16struct pcap_platform_data {
 17	unsigned int irq_base;
 18	unsigned int config;
 19	void (*init) (void *);	/* board specific init */
 20	int num_subdevs;
 21	struct pcap_subdev *subdevs;
 22};
 23
 24struct pcap_chip;
 25
 26int ezx_pcap_write(struct pcap_chip *, u8, u32);
 27int ezx_pcap_read(struct pcap_chip *, u8, u32 *);
 28int ezx_pcap_set_bits(struct pcap_chip *, u8, u32, u32);
 29int pcap_to_irq(struct pcap_chip *, int);
 30int irq_to_pcap(struct pcap_chip *, int);
 31int pcap_adc_async(struct pcap_chip *, u8, u32, u8[], void *, void *);
 32int pcap_adc_sync(struct pcap_chip *, u8, u32, u8[], u16[]);
 33void pcap_set_ts_bits(struct pcap_chip *, u32);
 34
 35#define PCAP_SECOND_PORT	1
 36#define PCAP_CS_AH		2
 37
 38#define PCAP_REGISTER_WRITE_OP_BIT	0x80000000
 39#define PCAP_REGISTER_READ_OP_BIT	0x00000000
 40
 41#define PCAP_REGISTER_VALUE_MASK	0x01ffffff
 42#define PCAP_REGISTER_ADDRESS_MASK	0x7c000000
 43#define PCAP_REGISTER_ADDRESS_SHIFT	26
 44#define PCAP_REGISTER_NUMBER		32
 45#define PCAP_CLEAR_INTERRUPT_REGISTER	0x01ffffff
 46#define PCAP_MASK_ALL_INTERRUPT		0x01ffffff
 47
 48/* registers accessible by both pcap ports */
 49#define PCAP_REG_ISR		0x0	/* Interrupt Status */
 50#define PCAP_REG_MSR		0x1	/* Interrupt Mask */
 51#define PCAP_REG_PSTAT		0x2	/* Processor Status */
 52#define PCAP_REG_VREG2		0x6	/* Regulator Bank 2 Control */
 53#define PCAP_REG_AUXVREG	0x7	/* Auxiliary Regulator Control */
 54#define PCAP_REG_BATT		0x8	/* Battery Control */
 55#define PCAP_REG_ADC		0x9	/* AD Control */
 56#define PCAP_REG_ADR		0xa	/* AD Result */
 57#define PCAP_REG_CODEC		0xb	/* Audio Codec Control */
 58#define PCAP_REG_RX_AMPS	0xc	/* RX Audio Amplifiers Control */
 59#define PCAP_REG_ST_DAC		0xd	/* Stereo DAC Control */
 60#define PCAP_REG_BUSCTRL	0x14	/* Connectivity Control */
 61#define PCAP_REG_PERIPH		0x15	/* Peripheral Control */
 62#define PCAP_REG_LOWPWR		0x18	/* Regulator Low Power Control */
 63#define PCAP_REG_TX_AMPS	0x1a	/* TX Audio Amplifiers Control */
 64#define PCAP_REG_GP		0x1b	/* General Purpose */
 65#define PCAP_REG_TEST1		0x1c
 66#define PCAP_REG_TEST2		0x1d
 67#define PCAP_REG_VENDOR_TEST1	0x1e
 68#define PCAP_REG_VENDOR_TEST2	0x1f
 69
 70/* registers accessible by pcap port 1 only (a1200, e2 & e6) */
 71#define PCAP_REG_INT_SEL	0x3	/* Interrupt Select */
 72#define PCAP_REG_SWCTRL		0x4	/* Switching Regulator Control */
 73#define PCAP_REG_VREG1		0x5	/* Regulator Bank 1 Control */
 74#define PCAP_REG_RTC_TOD	0xe	/* RTC Time of Day */
 75#define PCAP_REG_RTC_TODA	0xf	/* RTC Time of Day Alarm */
 76#define PCAP_REG_RTC_DAY	0x10	/* RTC Day */
 77#define PCAP_REG_RTC_DAYA	0x11	/* RTC Day Alarm */
 78#define PCAP_REG_MTRTMR		0x12	/* AD Monitor Timer */
 79#define PCAP_REG_PWR		0x13	/* Power Control */
 80#define PCAP_REG_AUXVREG_MASK	0x16	/* Auxiliary Regulator Mask */
 81#define PCAP_REG_VENDOR_REV	0x17
 82#define PCAP_REG_PERIPH_MASK	0x19	/* Peripheral Mask */
 83
 84/* PCAP2 Interrupts */
 85#define PCAP_NIRQS		23
 86#define PCAP_IRQ_ADCDONE	0	/* ADC done port 1 */
 87#define PCAP_IRQ_TS		1	/* Touch Screen */
 88#define PCAP_IRQ_1HZ		2	/* 1HZ timer */
 89#define PCAP_IRQ_WH		3	/* ADC above high limit */
 90#define PCAP_IRQ_WL		4	/* ADC below low limit */
 91#define PCAP_IRQ_TODA		5	/* Time of day alarm */
 92#define PCAP_IRQ_USB4V		6	/* USB above 4V */
 93#define PCAP_IRQ_ONOFF		7	/* On/Off button */
 94#define PCAP_IRQ_ONOFF2		8	/* On/Off button 2 */
 95#define PCAP_IRQ_USB1V		9	/* USB above 1V */
 96#define PCAP_IRQ_MOBPORT	10
 97#define PCAP_IRQ_MIC		11	/* Mic attach/HS button */
 98#define PCAP_IRQ_HS		12	/* Headset attach */
 99#define PCAP_IRQ_ST		13
100#define PCAP_IRQ_PC		14	/* Power Cut */
101#define PCAP_IRQ_WARM		15
102#define PCAP_IRQ_EOL		16	/* Battery End Of Life */
103#define PCAP_IRQ_CLK		17
104#define PCAP_IRQ_SYSRST		18	/* System Reset */
105#define PCAP_IRQ_DUMMY		19
106#define PCAP_IRQ_ADCDONE2	20	/* ADC done port 2 */
107#define PCAP_IRQ_SOFTRESET	21
108#define PCAP_IRQ_MNEXB		22
109
110/* voltage regulators */
111#define V1		0
112#define V2		1
113#define V3		2
114#define V4		3
115#define V5		4
116#define V6		5
117#define V7		6
118#define V8		7
119#define V9		8
120#define V10		9
121#define VAUX1		10
122#define VAUX2		11
123#define VAUX3		12
124#define VAUX4		13
125#define VSIM		14
126#define VSIM2		15
127#define VVIB		16
128#define SW1		17
129#define SW2		18
130#define SW3		19
131#define SW1S		20
132#define SW2S		21
133
134#define PCAP_BATT_DAC_MASK		0x000000ff
135#define PCAP_BATT_DAC_SHIFT		0
136#define PCAP_BATT_B_FDBK		(1 << 8)
137#define PCAP_BATT_EXT_ISENSE		(1 << 9)
138#define PCAP_BATT_V_COIN_MASK		0x00003c00
139#define PCAP_BATT_V_COIN_SHIFT		10
140#define PCAP_BATT_I_COIN		(1 << 14)
141#define PCAP_BATT_COIN_CH_EN		(1 << 15)
142#define PCAP_BATT_EOL_SEL_MASK		0x000e0000
143#define PCAP_BATT_EOL_SEL_SHIFT		17
144#define PCAP_BATT_EOL_CMP_EN		(1 << 20)
145#define PCAP_BATT_BATT_DET_EN		(1 << 21)
146#define PCAP_BATT_THERMBIAS_CTRL	(1 << 22)
147
148#define PCAP_ADC_ADEN			(1 << 0)
149#define PCAP_ADC_RAND			(1 << 1)
150#define PCAP_ADC_AD_SEL1		(1 << 2)
151#define PCAP_ADC_AD_SEL2		(1 << 3)
152#define PCAP_ADC_ADA1_MASK		0x00000070
153#define PCAP_ADC_ADA1_SHIFT		4
154#define PCAP_ADC_ADA2_MASK		0x00000380
155#define PCAP_ADC_ADA2_SHIFT		7
156#define PCAP_ADC_ATO_MASK		0x00003c00
157#define PCAP_ADC_ATO_SHIFT		10
158#define PCAP_ADC_ATOX			(1 << 14)
159#define PCAP_ADC_MTR1			(1 << 15)
160#define PCAP_ADC_MTR2			(1 << 16)
161#define PCAP_ADC_TS_M_MASK		0x000e0000
162#define PCAP_ADC_TS_M_SHIFT		17
163#define PCAP_ADC_TS_REF_LOWPWR		(1 << 20)
164#define PCAP_ADC_TS_REFENB		(1 << 21)
165#define PCAP_ADC_BATT_I_POLARITY	(1 << 22)
166#define PCAP_ADC_BATT_I_ADC		(1 << 23)
167
168#define PCAP_ADC_BANK_0			0
169#define PCAP_ADC_BANK_1			1
170/* ADC bank 0 */
171#define PCAP_ADC_CH_COIN		0
172#define PCAP_ADC_CH_BATT		1
173#define PCAP_ADC_CH_BPLUS		2
174#define PCAP_ADC_CH_MOBPORTB		3
175#define PCAP_ADC_CH_TEMPERATURE		4
176#define PCAP_ADC_CH_CHARGER_ID		5
177#define PCAP_ADC_CH_AD6			6
178/* ADC bank 1 */
179#define PCAP_ADC_CH_AD7			0
180#define PCAP_ADC_CH_AD8			1
181#define PCAP_ADC_CH_AD9			2
182#define PCAP_ADC_CH_TS_X1		3
183#define PCAP_ADC_CH_TS_X2		4
184#define PCAP_ADC_CH_TS_Y1		5
185#define PCAP_ADC_CH_TS_Y2		6
186
187#define PCAP_ADC_T_NOW			0
188#define PCAP_ADC_T_IN_BURST		1
189#define PCAP_ADC_T_OUT_BURST		2
190
191#define PCAP_ADC_ATO_IN_BURST		6
192#define PCAP_ADC_ATO_OUT_BURST		0
193
194#define PCAP_ADC_TS_M_XY		1
195#define PCAP_ADC_TS_M_PRESSURE		2
196#define PCAP_ADC_TS_M_PLATE_X		3
197#define PCAP_ADC_TS_M_PLATE_Y		4
198#define PCAP_ADC_TS_M_STANDBY		5
199#define PCAP_ADC_TS_M_NONTS		6
200
201#define PCAP_ADR_ADD1_MASK		0x000003ff
202#define PCAP_ADR_ADD1_SHIFT		0
203#define PCAP_ADR_ADD2_MASK		0x000ffc00
204#define PCAP_ADR_ADD2_SHIFT		10
205#define PCAP_ADR_ADINC1			(1 << 20)
206#define PCAP_ADR_ADINC2			(1 << 21)
207#define PCAP_ADR_ASC			(1 << 22)
208#define PCAP_ADR_ONESHOT		(1 << 23)
209
210#define PCAP_BUSCTRL_FSENB		(1 << 0)
211#define PCAP_BUSCTRL_USB_SUSPEND	(1 << 1)
212#define PCAP_BUSCTRL_USB_PU		(1 << 2)
213#define PCAP_BUSCTRL_USB_PD		(1 << 3)
214#define PCAP_BUSCTRL_VUSB_EN		(1 << 4)
215#define PCAP_BUSCTRL_USB_PS		(1 << 5)
216#define PCAP_BUSCTRL_VUSB_MSTR_EN	(1 << 6)
217#define PCAP_BUSCTRL_VBUS_PD_ENB	(1 << 7)
218#define PCAP_BUSCTRL_CURRLIM		(1 << 8)
219#define PCAP_BUSCTRL_RS232ENB		(1 << 9)
220#define PCAP_BUSCTRL_RS232_DIR		(1 << 10)
221#define PCAP_BUSCTRL_SE0_CONN		(1 << 11)
222#define PCAP_BUSCTRL_USB_PDM		(1 << 12)
223#define PCAP_BUSCTRL_BUS_PRI_ADJ	(1 << 24)
224
225/* leds */
226#define PCAP_LED0		0
227#define PCAP_LED1		1
228#define PCAP_BL0		2
229#define PCAP_BL1		3
230#define PCAP_LED_3MA		0
231#define PCAP_LED_4MA		1
232#define PCAP_LED_5MA		2
233#define PCAP_LED_9MA		3
234#define PCAP_LED_T_MASK		0xf
235#define PCAP_LED_C_MASK		0x3
236#define PCAP_BL_MASK		0x1f
237#define PCAP_BL0_SHIFT		0
238#define PCAP_LED0_EN		(1 << 5)
239#define PCAP_LED1_EN		(1 << 6)
240#define PCAP_LED0_T_SHIFT	7
241#define PCAP_LED1_T_SHIFT	11
242#define PCAP_LED0_C_SHIFT	15
243#define PCAP_LED1_C_SHIFT	17
244#define PCAP_BL1_SHIFT		20
245
246/* RTC */
247#define PCAP_RTC_DAY_MASK	0x3fff
248#define PCAP_RTC_TOD_MASK	0xffff
249#define PCAP_RTC_PC_MASK	0x7
250#define SEC_PER_DAY		86400
251
252#endif