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/arch/powerpc/include/asm/ipic.h

https://github.com/aicjofs/android_kernel_lge_v500_20d_f2fs
C Header | 84 lines | 62 code | 8 blank | 14 comment | 0 complexity | f3a1444b5be8a99b919ecb6a5f4843c0 MD5 | raw file
 1/*
 2 * IPIC external definitions and structure.
 3 *
 4 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
 5 *
 6 * Copyright 2005 Freescale Semiconductor, Inc
 7 *
 8 * This program is free software; you can redistribute  it and/or modify it
 9 * under  the terms of  the GNU General  Public License as published by the
10 * Free Software Foundation;  either version 2 of the  License, or (at your
11 * option) any later version.
12 */
13#ifdef __KERNEL__
14#ifndef __ASM_IPIC_H__
15#define __ASM_IPIC_H__
16
17#include <linux/irq.h>
18
19/* Flags when we init the IPIC */
20#define IPIC_SPREADMODE_GRP_A	0x00000001
21#define IPIC_SPREADMODE_GRP_B	0x00000002
22#define IPIC_SPREADMODE_GRP_C	0x00000004
23#define IPIC_SPREADMODE_GRP_D	0x00000008
24#define IPIC_SPREADMODE_MIX_A	0x00000010
25#define IPIC_SPREADMODE_MIX_B	0x00000020
26#define IPIC_DISABLE_MCP_OUT	0x00000040
27#define IPIC_IRQ0_MCP		0x00000080
28
29/* IPIC registers offsets */
30#define IPIC_SICFR	0x00	/* System Global Interrupt Configuration Register */
31#define IPIC_SIVCR	0x04	/* System Global Interrupt Vector Register */
32#define IPIC_SIPNR_H	0x08	/* System Internal Interrupt Pending Register (HIGH) */
33#define IPIC_SIPNR_L	0x0C	/* System Internal Interrupt Pending Register (LOW) */
34#define IPIC_SIPRR_A	0x10	/* System Internal Interrupt group A Priority Register */
35#define IPIC_SIPRR_B	0x14	/* System Internal Interrupt group B Priority Register */
36#define IPIC_SIPRR_C	0x18	/* System Internal Interrupt group C Priority Register */
37#define IPIC_SIPRR_D	0x1C	/* System Internal Interrupt group D Priority Register */
38#define IPIC_SIMSR_H	0x20	/* System Internal Interrupt Mask Register (HIGH) */
39#define IPIC_SIMSR_L	0x24	/* System Internal Interrupt Mask Register (LOW) */
40#define IPIC_SICNR	0x28	/* System Internal Interrupt Control Register */
41#define IPIC_SEPNR	0x2C	/* System External Interrupt Pending Register */
42#define IPIC_SMPRR_A	0x30	/* System Mixed Interrupt group A Priority Register */
43#define IPIC_SMPRR_B	0x34	/* System Mixed Interrupt group B Priority Register */
44#define IPIC_SEMSR	0x38	/* System External Interrupt Mask Register */
45#define IPIC_SECNR	0x3C	/* System External Interrupt Control Register */
46#define IPIC_SERSR	0x40	/* System Error Status Register */
47#define IPIC_SERMR	0x44	/* System Error Mask Register */
48#define IPIC_SERCR	0x48	/* System Error Control Register */
49#define IPIC_SIFCR_H	0x50	/* System Internal Interrupt Force Register (HIGH) */
50#define IPIC_SIFCR_L	0x54	/* System Internal Interrupt Force Register (LOW) */
51#define IPIC_SEFCR	0x58	/* System External Interrupt Force Register */
52#define IPIC_SERFR	0x5C	/* System Error Force Register */
53#define IPIC_SCVCR	0x60	/* System Critical Interrupt Vector Register */
54#define IPIC_SMVCR	0x64	/* System Management Interrupt Vector Register */
55
56enum ipic_prio_grp {
57	IPIC_INT_GRP_A = IPIC_SIPRR_A,
58	IPIC_INT_GRP_D = IPIC_SIPRR_D,
59	IPIC_MIX_GRP_A = IPIC_SMPRR_A,
60	IPIC_MIX_GRP_B = IPIC_SMPRR_B,
61};
62
63enum ipic_mcp_irq {
64	IPIC_MCP_IRQ0 = 0,
65	IPIC_MCP_WDT  = 1,
66	IPIC_MCP_SBA  = 2,
67	IPIC_MCP_PCI1 = 5,
68	IPIC_MCP_PCI2 = 6,
69	IPIC_MCP_MU   = 7,
70};
71
72extern int ipic_set_priority(unsigned int irq, unsigned int priority);
73extern void ipic_set_highest_priority(unsigned int irq);
74extern void ipic_set_default_priority(void);
75extern void ipic_enable_mcp(enum ipic_mcp_irq mcp_irq);
76extern void ipic_disable_mcp(enum ipic_mcp_irq mcp_irq);
77extern u32 ipic_get_mcp_status(void);
78extern void ipic_clear_mcp_status(u32 mask);
79
80extern struct ipic * ipic_init(struct device_node *node, unsigned int flags);
81extern unsigned int ipic_get_irq(void);
82
83#endif /* __ASM_IPIC_H__ */
84#endif /* __KERNEL__ */