/arch/arm/mach-msm/board-8930-display.c

  1/* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
  2 *
  3 * This program is free software; you can redistribute it and/or modify
  4 * it under the terms of the GNU General Public License version 2 and
  5 * only version 2 as published by the Free Software Foundation.
  6 *
  7 * This program is distributed in the hope that it will be useful,
  8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 10 * GNU General Public License for more details.
 11 *
 12 */
 13
 14#include <linux/init.h>
 15#include <linux/ioport.h>
 16#include <linux/platform_device.h>
 17#include <linux/bootmem.h>
 18#include <linux/gpio.h>
 19#include <asm/mach-types.h>
 20#include <mach/msm_bus_board.h>
 21#include <mach/msm_memtypes.h>
 22#include <mach/board.h>
 23#include <mach/gpiomux.h>
 24#include <mach/socinfo.h>
 25#include <linux/msm_ion.h>
 26#include <mach/ion.h>
 27
 28#include "devices.h"
 29#include "board-8930.h"
 30
 31#ifdef CONFIG_FB_MSM_TRIPLE_BUFFER
 32#define MSM_FB_PRIM_BUF_SIZE \
 33		(roundup((1920 * 1088 * 4), 4096) * 3) /* 4 bpp x 3 pages */
 34#else
 35#define MSM_FB_PRIM_BUF_SIZE \
 36		(roundup((1920 * 1088 * 4), 4096) * 2) /* 4 bpp x 2 pages */
 37#endif
 38/* Note: must be multiple of 4096 */
 39#define MSM_FB_SIZE roundup(MSM_FB_PRIM_BUF_SIZE, 4096)
 40
 41#ifdef CONFIG_FB_MSM_OVERLAY0_WRITEBACK
 42#define MSM_FB_OVERLAY0_WRITEBACK_SIZE roundup((1376 * 768 * 3 * 2), 4096)
 43#else
 44#define MSM_FB_OVERLAY0_WRITEBACK_SIZE (0)
 45#endif  /* CONFIG_FB_MSM_OVERLAY0_WRITEBACK */
 46
 47#ifdef CONFIG_FB_MSM_OVERLAY1_WRITEBACK
 48#define MSM_FB_OVERLAY1_WRITEBACK_SIZE roundup((1920 * 1088 * 3 * 2), 4096)
 49#else
 50#define MSM_FB_OVERLAY1_WRITEBACK_SIZE (0)
 51#endif  /* CONFIG_FB_MSM_OVERLAY1_WRITEBACK */
 52
 53#define MDP_VSYNC_GPIO 0
 54
 55#define MIPI_CMD_NOVATEK_QHD_PANEL_NAME	"mipi_cmd_novatek_qhd"
 56#define MIPI_VIDEO_NOVATEK_QHD_PANEL_NAME	"mipi_video_novatek_qhd"
 57#define MIPI_VIDEO_TOSHIBA_WSVGA_PANEL_NAME	"mipi_video_toshiba_wsvga"
 58#define MIPI_VIDEO_CHIMEI_WXGA_PANEL_NAME	"mipi_video_chimei_wxga"
 59#define MIPI_VIDEO_SIMULATOR_VGA_PANEL_NAME	"mipi_video_simulator_vga"
 60#define MIPI_CMD_RENESAS_FWVGA_PANEL_NAME	"mipi_cmd_renesas_fwvga"
 61#define HDMI_PANEL_NAME	"hdmi_msm"
 62#define TVOUT_PANEL_NAME	"tvout_msm"
 63
 64static struct resource msm_fb_resources[] = {
 65	{
 66		.flags = IORESOURCE_DMA,
 67	}
 68};
 69
 70static int msm_fb_detect_panel(const char *name)
 71{
 72	if (!strncmp(name, MIPI_CMD_NOVATEK_QHD_PANEL_NAME,
 73			strnlen(MIPI_CMD_NOVATEK_QHD_PANEL_NAME,
 74				PANEL_NAME_MAX_LEN)))
 75		return 0;
 76
 77#if !defined(CONFIG_FB_MSM_LVDS_MIPI_PANEL_DETECT) && \
 78	!defined(CONFIG_FB_MSM_MIPI_PANEL_DETECT)
 79	if (!strncmp(name, MIPI_VIDEO_NOVATEK_QHD_PANEL_NAME,
 80			strnlen(MIPI_VIDEO_NOVATEK_QHD_PANEL_NAME,
 81				PANEL_NAME_MAX_LEN)))
 82		return 0;
 83
 84	if (!strncmp(name, MIPI_VIDEO_TOSHIBA_WSVGA_PANEL_NAME,
 85			strnlen(MIPI_VIDEO_TOSHIBA_WSVGA_PANEL_NAME,
 86				PANEL_NAME_MAX_LEN)))
 87		return 0;
 88
 89	if (!strncmp(name, MIPI_VIDEO_SIMULATOR_VGA_PANEL_NAME,
 90			strnlen(MIPI_VIDEO_SIMULATOR_VGA_PANEL_NAME,
 91				PANEL_NAME_MAX_LEN)))
 92		return 0;
 93
 94	if (!strncmp(name, MIPI_CMD_RENESAS_FWVGA_PANEL_NAME,
 95			strnlen(MIPI_CMD_RENESAS_FWVGA_PANEL_NAME,
 96				PANEL_NAME_MAX_LEN)))
 97		return 0;
 98#endif
 99
100	if (!strncmp(name, HDMI_PANEL_NAME,
101			strnlen(HDMI_PANEL_NAME,
102				PANEL_NAME_MAX_LEN)))
103		return 0;
104
105	if (!strncmp(name, TVOUT_PANEL_NAME,
106			strnlen(TVOUT_PANEL_NAME,
107				PANEL_NAME_MAX_LEN)))
108		return 0;
109
110	pr_warning("%s: not supported '%s'", __func__, name);
111	return -ENODEV;
112}
113
114static struct msm_fb_platform_data msm_fb_pdata = {
115	.detect_client = msm_fb_detect_panel,
116};
117
118static struct platform_device msm_fb_device = {
119	.name   = "msm_fb",
120	.id     = 0,
121	.num_resources     = ARRAY_SIZE(msm_fb_resources),
122	.resource          = msm_fb_resources,
123	.dev.platform_data = &msm_fb_pdata,
124};
125
126static bool dsi_power_on;
127static struct mipi_dsi_panel_platform_data novatek_pdata;
128static void pm8917_gpio_set_backlight(int bl_level)
129{
130	int gpio24 = PM8917_GPIO_PM_TO_SYS(24);
131	if (bl_level > 0)
132		gpio_set_value_cansleep(gpio24, 1);
133	else
134		gpio_set_value_cansleep(gpio24, 0);
135}
136
137/*
138 * TODO: When physical 8930/PM8038 hardware becomes
139 * available, replace mipi_dsi_cdp_panel_power with
140 * appropriate function.
141 */
142#define DISP_RST_GPIO 58
143#define DISP_3D_2D_MODE 1
144static int mipi_dsi_cdp_panel_power(int on)
145{
146	static struct regulator *reg_l8, *reg_l23, *reg_l2;
147	/* Control backlight GPIO (24) directly when using PM8917 */
148	int gpio24 = PM8917_GPIO_PM_TO_SYS(24);
149	int rc;
150
151	pr_debug("%s: state : %d\n", __func__, on);
152
153	if (!dsi_power_on) {
154
155		reg_l8 = regulator_get(&msm_mipi_dsi1_device.dev,
156				"dsi_vdc");
157		if (IS_ERR(reg_l8)) {
158			pr_err("could not get 8038_l8, rc = %ld\n",
159				PTR_ERR(reg_l8));
160			return -ENODEV;
161		}
162		reg_l23 = regulator_get(&msm_mipi_dsi1_device.dev,
163				"dsi_vddio");
164		if (IS_ERR(reg_l23)) {
165			pr_err("could not get 8038_l23, rc = %ld\n",
166				PTR_ERR(reg_l23));
167			return -ENODEV;
168		}
169		reg_l2 = regulator_get(&msm_mipi_dsi1_device.dev,
170				"dsi_vdda");
171		if (IS_ERR(reg_l2)) {
172			pr_err("could not get 8038_l2, rc = %ld\n",
173				PTR_ERR(reg_l2));
174			return -ENODEV;
175		}
176		rc = regulator_set_voltage(reg_l8, 2800000, 3000000);
177		if (rc) {
178			pr_err("set_voltage l8 failed, rc=%d\n", rc);
179			return -EINVAL;
180		}
181		rc = regulator_set_voltage(reg_l23, 1800000, 1800000);
182		if (rc) {
183			pr_err("set_voltage l23 failed, rc=%d\n", rc);
184			return -EINVAL;
185		}
186		rc = regulator_set_voltage(reg_l2, 1200000, 1200000);
187		if (rc) {
188			pr_err("set_voltage l2 failed, rc=%d\n", rc);
189			return -EINVAL;
190		}
191		rc = gpio_request(DISP_RST_GPIO, "disp_rst_n");
192		if (rc) {
193			pr_err("request gpio DISP_RST_GPIO failed, rc=%d\n",
194				rc);
195			gpio_free(DISP_RST_GPIO);
196			return -ENODEV;
197		}
198		rc = gpio_request(DISP_3D_2D_MODE, "disp_3d_2d");
199		if (rc) {
200			pr_err("request gpio DISP_3D_2D_MODE failed, rc=%d\n",
201				 rc);
202			gpio_free(DISP_3D_2D_MODE);
203			return -ENODEV;
204		}
205		rc = gpio_direction_output(DISP_3D_2D_MODE, 0);
206		if (rc) {
207			pr_err("gpio_direction_output failed for %d gpio rc=%d\n",
208			DISP_3D_2D_MODE, rc);
209			return -ENODEV;
210		}
211		if (socinfo_get_pmic_model() == PMIC_MODEL_PM8917) {
212			rc = gpio_request(gpio24, "disp_bl");
213			if (rc) {
214				pr_err("request for gpio 24 failed, rc=%d\n",
215					rc);
216				return -ENODEV;
217			}
218			gpio_set_value_cansleep(gpio24, 0);
219			novatek_pdata.gpio_set_backlight =
220				pm8917_gpio_set_backlight;
221		}
222		dsi_power_on = true;
223	}
224
225	if (on) {
226		rc = regulator_set_optimum_mode(reg_l8, 100000);
227		if (rc < 0) {
228			pr_err("set_optimum_mode l8 failed, rc=%d\n", rc);
229			return -EINVAL;
230		}
231		rc = regulator_set_optimum_mode(reg_l23, 100000);
232		if (rc < 0) {
233			pr_err("set_optimum_mode l23 failed, rc=%d\n", rc);
234			return -EINVAL;
235		}
236		rc = regulator_set_optimum_mode(reg_l2, 100000);
237		if (rc < 0) {
238			pr_err("set_optimum_mode l2 failed, rc=%d\n", rc);
239			return -EINVAL;
240		}
241		rc = regulator_enable(reg_l8);
242		if (rc) {
243			pr_err("enable l8 failed, rc=%d\n", rc);
244			return -ENODEV;
245		}
246		rc = regulator_enable(reg_l23);
247		if (rc) {
248			pr_err("enable l8 failed, rc=%d\n", rc);
249			return -ENODEV;
250		}
251		rc = regulator_enable(reg_l2);
252		if (rc) {
253			pr_err("enable l2 failed, rc=%d\n", rc);
254			return -ENODEV;
255		}
256		usleep(10000);
257		gpio_set_value(DISP_RST_GPIO, 1);
258		usleep(10);
259		gpio_set_value(DISP_RST_GPIO, 0);
260		usleep(20);
261		gpio_set_value(DISP_RST_GPIO, 1);
262		gpio_set_value(DISP_3D_2D_MODE, 1);
263		usleep(20);
264	} else {
265
266		gpio_set_value(DISP_RST_GPIO, 0);
267
268		rc = regulator_disable(reg_l2);
269		if (rc) {
270			pr_err("disable reg_l2 failed, rc=%d\n", rc);
271			return -ENODEV;
272		}
273		rc = regulator_disable(reg_l8);
274		if (rc) {
275			pr_err("disable reg_l8 failed, rc=%d\n", rc);
276			return -ENODEV;
277		}
278		rc = regulator_disable(reg_l23);
279		if (rc) {
280			pr_err("disable reg_l23 failed, rc=%d\n", rc);
281			return -ENODEV;
282		}
283		rc = regulator_set_optimum_mode(reg_l8, 100);
284		if (rc < 0) {
285			pr_err("set_optimum_mode l8 failed, rc=%d\n", rc);
286			return -EINVAL;
287		}
288		rc = regulator_set_optimum_mode(reg_l23, 100);
289		if (rc < 0) {
290			pr_err("set_optimum_mode l23 failed, rc=%d\n", rc);
291			return -EINVAL;
292		}
293		rc = regulator_set_optimum_mode(reg_l2, 100);
294		if (rc < 0) {
295			pr_err("set_optimum_mode l2 failed, rc=%d\n", rc);
296			return -EINVAL;
297		}
298		gpio_set_value(DISP_3D_2D_MODE, 0);
299		usleep(20);
300	}
301	return 0;
302}
303
304static int mipi_dsi_panel_power(int on)
305{
306	pr_debug("%s: on=%d\n", __func__, on);
307
308	return mipi_dsi_cdp_panel_power(on);
309}
310
311static struct mipi_dsi_platform_data mipi_dsi_pdata = {
312	.vsync_gpio = MDP_VSYNC_GPIO,
313	.dsi_power_save = mipi_dsi_panel_power,
314};
315
316#ifdef CONFIG_MSM_BUS_SCALING
317
318static struct msm_bus_vectors mdp_init_vectors[] = {
319	{
320		.src = MSM_BUS_MASTER_MDP_PORT0,
321		.dst = MSM_BUS_SLAVE_EBI_CH0,
322		.ab = 0,
323		.ib = 0,
324	},
325};
326
327#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
328static struct msm_bus_vectors hdmi_as_primary_vectors[] = {
329	/* If HDMI is used as primary */
330	{
331		.src = MSM_BUS_MASTER_MDP_PORT0,
332		.dst = MSM_BUS_SLAVE_EBI_CH0,
333		.ab = 2000000000,
334		.ib = 2000000000,
335	},
336};
337static struct msm_bus_paths mdp_bus_scale_usecases[] = {
338	{
339		ARRAY_SIZE(mdp_init_vectors),
340		mdp_init_vectors,
341	},
342	{
343		ARRAY_SIZE(hdmi_as_primary_vectors),
344		hdmi_as_primary_vectors,
345	},
346	{
347		ARRAY_SIZE(hdmi_as_primary_vectors),
348		hdmi_as_primary_vectors,
349	},
350	{
351		ARRAY_SIZE(hdmi_as_primary_vectors),
352		hdmi_as_primary_vectors,
353	},
354	{
355		ARRAY_SIZE(hdmi_as_primary_vectors),
356		hdmi_as_primary_vectors,
357	},
358	{
359		ARRAY_SIZE(hdmi_as_primary_vectors),
360		hdmi_as_primary_vectors,
361	},
362};
363#else
364static struct msm_bus_vectors mdp_ui_vectors[] = {
365	{
366		.src = MSM_BUS_MASTER_MDP_PORT0,
367		.dst = MSM_BUS_SLAVE_EBI_CH0,
368		.ab = 216000000 * 2,
369		.ib = 270000000 * 2,
370	},
371};
372
373static struct msm_bus_vectors mdp_vga_vectors[] = {
374	/* VGA and less video */
375	{
376		.src = MSM_BUS_MASTER_MDP_PORT0,
377		.dst = MSM_BUS_SLAVE_EBI_CH0,
378		.ab = 216000000 * 2,
379		.ib = 270000000 * 2,
380	},
381};
382
383static struct msm_bus_vectors mdp_720p_vectors[] = {
384	/* 720p and less video */
385	{
386		.src = MSM_BUS_MASTER_MDP_PORT0,
387		.dst = MSM_BUS_SLAVE_EBI_CH0,
388		.ab = 230400000 * 2,
389		.ib = 288000000 * 2,
390	},
391};
392
393static struct msm_bus_vectors mdp_1080p_vectors[] = {
394	/* 1080p and less video */
395	{
396		.src = MSM_BUS_MASTER_MDP_PORT0,
397		.dst = MSM_BUS_SLAVE_EBI_CH0,
398		.ab = 334080000 * 2,
399		.ib = 417600000 * 2,
400	},
401};
402
403static struct msm_bus_paths mdp_bus_scale_usecases[] = {
404	{
405		ARRAY_SIZE(mdp_init_vectors),
406		mdp_init_vectors,
407	},
408	{
409		ARRAY_SIZE(mdp_ui_vectors),
410		mdp_ui_vectors,
411	},
412	{
413		ARRAY_SIZE(mdp_ui_vectors),
414		mdp_ui_vectors,
415	},
416	{
417		ARRAY_SIZE(mdp_vga_vectors),
418		mdp_vga_vectors,
419	},
420	{
421		ARRAY_SIZE(mdp_720p_vectors),
422		mdp_720p_vectors,
423	},
424	{
425		ARRAY_SIZE(mdp_1080p_vectors),
426		mdp_1080p_vectors,
427	},
428};
429#endif
430
431static struct msm_bus_scale_pdata mdp_bus_scale_pdata = {
432	mdp_bus_scale_usecases,
433	ARRAY_SIZE(mdp_bus_scale_usecases),
434	.name = "mdp",
435};
436
437#endif
438
439static struct msm_panel_common_pdata mdp_pdata = {
440	.gpio = MDP_VSYNC_GPIO,
441	.mdp_max_clk = 200000000,
442	.mdp_max_bw = 2000000000,
443	.mdp_bw_ab_factor = 115,
444	.mdp_bw_ib_factor = 125,
445#ifdef CONFIG_MSM_BUS_SCALING
446	.mdp_bus_scale_table = &mdp_bus_scale_pdata,
447#endif
448	.mdp_rev = MDP_REV_43,
449#ifdef CONFIG_MSM_MULTIMEDIA_USE_ION
450	.mem_hid = BIT(ION_CP_MM_HEAP_ID),
451#else
452	.mem_hid = MEMTYPE_EBI1,
453#endif
454	.mdp_iommu_split_domain = 0,
455};
456
457void __init msm8930_mdp_writeback(struct memtype_reserve* reserve_table)
458{
459	mdp_pdata.ov0_wb_size = MSM_FB_OVERLAY0_WRITEBACK_SIZE;
460	mdp_pdata.ov1_wb_size = MSM_FB_OVERLAY1_WRITEBACK_SIZE;
461#if defined(CONFIG_ANDROID_PMEM) && !defined(CONFIG_MSM_MULTIMEDIA_USE_ION)
462	reserve_table[mdp_pdata.mem_hid].size +=
463		mdp_pdata.ov0_wb_size;
464	reserve_table[mdp_pdata.mem_hid].size +=
465		mdp_pdata.ov1_wb_size;
466#endif
467}
468
469#define LPM_CHANNEL0 0
470static int toshiba_gpio[] = {LPM_CHANNEL0};
471
472static struct mipi_dsi_panel_platform_data toshiba_pdata = {
473	.gpio = toshiba_gpio,
474};
475
476static struct platform_device mipi_dsi_toshiba_panel_device = {
477	.name = "mipi_toshiba",
478	.id = 0,
479	.dev = {
480		.platform_data = &toshiba_pdata,
481	}
482};
483
484#define FPGA_3D_GPIO_CONFIG_ADDR	0xB5
485
486static struct mipi_dsi_phy_ctrl dsi_novatek_cmd_mode_phy_db = {
487
488/* DSI_BIT_CLK at 500MHz, 2 lane, RGB888 */
489	{0x09, 0x08, 0x05, 0x00, 0x20},	/* regulator */
490	/* timing   */
491	{0xab, 0x8a, 0x18, 0x00, 0x92, 0x97, 0x1b, 0x8c,
492	0x0c, 0x03, 0x04, 0xa0},
493	{0x5f, 0x00, 0x00, 0x10},	/* phy ctrl */
494	{0xff, 0x00, 0x06, 0x00},	/* strength */
495	/* pll control */
496	{0x0, 0xe, 0x30, 0xda, 0x00, 0x10, 0x0f, 0x61,
497	0x40, 0x07, 0x03,
498	0x00, 0x1a, 0x00, 0x00, 0x02, 0x00, 0x20, 0x00, 0x02},
499};
500
501static struct mipi_dsi_panel_platform_data novatek_pdata = {
502	.fpga_3d_config_addr  = FPGA_3D_GPIO_CONFIG_ADDR,
503	.fpga_ctrl_mode = FPGA_SPI_INTF,
504	.phy_ctrl_settings = &dsi_novatek_cmd_mode_phy_db,
505	.dlane_swap = 0x1,
506	.enable_wled_bl_ctrl = 0x1,
507};
508
509static struct platform_device mipi_dsi_novatek_panel_device = {
510	.name = "mipi_novatek",
511	.id = 0,
512	.dev = {
513		.platform_data = &novatek_pdata,
514	}
515};
516
517#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL
518static struct resource hdmi_msm_resources[] = {
519	{
520		.name  = "hdmi_msm_qfprom_addr",
521		.start = 0x00700000,
522		.end   = 0x007060FF,
523		.flags = IORESOURCE_MEM,
524	},
525	{
526		.name  = "hdmi_msm_hdmi_addr",
527		.start = 0x04A00000,
528		.end   = 0x04A00FFF,
529		.flags = IORESOURCE_MEM,
530	},
531	{
532		.name  = "hdmi_msm_irq",
533		.start = HDMI_IRQ,
534		.end   = HDMI_IRQ,
535		.flags = IORESOURCE_IRQ,
536	},
537};
538
539static int hdmi_enable_5v(int on);
540static int hdmi_core_power(int on, int show);
541static int hdmi_cec_power(int on);
542static int hdmi_gpio_config(int on);
543static int hdmi_panel_power(int on);
544
545static struct msm_hdmi_platform_data hdmi_msm_data = {
546	.irq = HDMI_IRQ,
547	.enable_5v = hdmi_enable_5v,
548	.core_power = hdmi_core_power,
549	.cec_power = hdmi_cec_power,
550	.panel_power = hdmi_panel_power,
551	.gpio_config = hdmi_gpio_config,
552};
553
554static struct platform_device hdmi_msm_device = {
555	.name = "hdmi_msm",
556	.id = 0,
557	.num_resources = ARRAY_SIZE(hdmi_msm_resources),
558	.resource = hdmi_msm_resources,
559	.dev.platform_data = &hdmi_msm_data,
560};
561#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL */
562
563#ifdef CONFIG_FB_MSM_WRITEBACK_MSM_PANEL
564static struct platform_device wfd_panel_device = {
565	.name = "wfd_panel",
566	.id = 0,
567	.dev.platform_data = NULL,
568};
569
570static struct platform_device wfd_device = {
571	.name          = "msm_wfd",
572	.id            = -1,
573};
574#endif
575
576#ifdef CONFIG_MSM_BUS_SCALING
577static struct msm_bus_vectors dtv_bus_init_vectors[] = {
578	{
579		.src = MSM_BUS_MASTER_MDP_PORT0,
580		.dst = MSM_BUS_SLAVE_EBI_CH0,
581		.ab = 0,
582		.ib = 0,
583	},
584};
585
586#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
587static struct msm_bus_vectors dtv_bus_def_vectors[] = {
588	{
589		.src = MSM_BUS_MASTER_MDP_PORT0,
590		.dst = MSM_BUS_SLAVE_EBI_CH0,
591		.ab = 2000000000,
592		.ib = 2000000000,
593	},
594};
595#else
596static struct msm_bus_vectors dtv_bus_def_vectors[] = {
597	{
598		.src = MSM_BUS_MASTER_MDP_PORT0,
599		.dst = MSM_BUS_SLAVE_EBI_CH0,
600		.ab = 566092800 * 2,
601		.ib = 707616000 * 2,
602	},
603};
604#endif
605
606static struct msm_bus_paths dtv_bus_scale_usecases[] = {
607	{
608		ARRAY_SIZE(dtv_bus_init_vectors),
609		dtv_bus_init_vectors,
610	},
611	{
612		ARRAY_SIZE(dtv_bus_def_vectors),
613		dtv_bus_def_vectors,
614	},
615};
616static struct msm_bus_scale_pdata dtv_bus_scale_pdata = {
617	dtv_bus_scale_usecases,
618	ARRAY_SIZE(dtv_bus_scale_usecases),
619	.name = "dtv",
620};
621
622static struct lcdc_platform_data dtv_pdata = {
623	.bus_scale_table = &dtv_bus_scale_pdata,
624	.lcdc_power_save = hdmi_panel_power,
625};
626
627static int hdmi_panel_power(int on)
628{
629	int rc;
630
631	pr_debug("%s: HDMI Core: %s\n", __func__, (on ? "ON" : "OFF"));
632	rc = hdmi_core_power(on, 1);
633	if (rc)
634		rc = hdmi_cec_power(on);
635
636	pr_debug("%s: HDMI Core: %s Success\n", __func__, (on ? "ON" : "OFF"));
637	return rc;
638}
639#endif
640
641#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL
642static int hdmi_enable_5v(int on)
643{
644	static struct regulator *reg_ext_5v;	/* HDMI_5V */
645	static int prev_on;
646	int rc;
647
648	if (on == prev_on)
649		return 0;
650
651	if (!reg_ext_5v) {
652		reg_ext_5v = regulator_get(&hdmi_msm_device.dev, "hdmi_mvs");
653		if (IS_ERR(reg_ext_5v)) {
654			pr_err("'%s' regulator not found, rc=%ld\n",
655				"hdmi_mvs", IS_ERR(reg_ext_5v));
656			reg_ext_5v = NULL;
657			return -ENODEV;
658		}
659	}
660
661	if (on) {
662		rc = regulator_enable(reg_ext_5v);
663		if (rc) {
664			pr_err("'%s' regulator enable failed, rc=%d\n",
665				"reg_ext_5v", rc);
666			return rc;
667		}
668		pr_debug("%s(on): success\n", __func__);
669	} else {
670		rc = regulator_disable(reg_ext_5v);
671		if (rc)
672			pr_warning("'%s' regulator disable failed, rc=%d\n",
673				"reg_ext_5v", rc);
674		pr_debug("%s(off): success\n", __func__);
675	}
676
677	prev_on = on;
678
679	return 0;
680}
681
682static int hdmi_core_power(int on, int show)
683{
684	/* Both HDMI "avdd" and "vcc" are powered by 8038_l23 regulator */
685	static struct regulator *reg_8038_l23;
686	static int prev_on;
687	int rc;
688
689	if (on == prev_on)
690		return 0;
691
692	if (!reg_8038_l23) {
693		reg_8038_l23 = regulator_get(&hdmi_msm_device.dev, "hdmi_avdd");
694		if (IS_ERR(reg_8038_l23)) {
695			pr_err("could not get reg_8038_l23, rc = %ld\n",
696				PTR_ERR(reg_8038_l23));
697			return -ENODEV;
698		}
699		rc = regulator_set_voltage(reg_8038_l23, 1800000, 1800000);
700		if (rc) {
701			pr_err("set_voltage failed for 8921_l23, rc=%d\n", rc);
702			return -EINVAL;
703		}
704	}
705
706	if (on) {
707		rc = regulator_set_optimum_mode(reg_8038_l23, 100000);
708		if (rc < 0) {
709			pr_err("set_optimum_mode l23 failed, rc=%d\n", rc);
710			return -EINVAL;
711		}
712		rc = regulator_enable(reg_8038_l23);
713		if (rc) {
714			pr_err("'%s' regulator enable failed, rc=%d\n",
715				"hdmi_avdd", rc);
716			return rc;
717		}
718		pr_debug("%s(on): success\n", __func__);
719	} else {
720		rc = regulator_disable(reg_8038_l23);
721		if (rc) {
722			pr_err("disable reg_8038_l23 failed, rc=%d\n", rc);
723			return -ENODEV;
724		}
725		rc = regulator_set_optimum_mode(reg_8038_l23, 100);
726		if (rc < 0) {
727			pr_err("set_optimum_mode l23 failed, rc=%d\n", rc);
728			return -EINVAL;
729		}
730		pr_debug("%s(off): success\n", __func__);
731	}
732
733	prev_on = on;
734
735	return 0;
736}
737
738static int hdmi_gpio_config(int on)
739{
740	int rc = 0;
741	static int prev_on;
742
743	if (on == prev_on)
744		return 0;
745
746	if (on) {
747		rc = gpio_request(100, "HDMI_DDC_CLK");
748		if (rc) {
749			pr_err("'%s'(%d) gpio_request failed, rc=%d\n",
750				"HDMI_DDC_CLK", 100, rc);
751			return rc;
752		}
753		rc = gpio_request(101, "HDMI_DDC_DATA");
754		if (rc) {
755			pr_err("'%s'(%d) gpio_request failed, rc=%d\n",
756				"HDMI_DDC_DATA", 101, rc);
757			goto error1;
758		}
759		rc = gpio_request(102, "HDMI_HPD");
760		if (rc) {
761			pr_err("'%s'(%d) gpio_request failed, rc=%d\n",
762				"HDMI_HPD", 102, rc);
763			goto error2;
764		}
765		pr_debug("%s(on): success\n", __func__);
766	} else {
767		gpio_free(100);
768		gpio_free(101);
769		gpio_free(102);
770		pr_debug("%s(off): success\n", __func__);
771	}
772
773	prev_on = on;
774	return 0;
775
776error2:
777	gpio_free(101);
778error1:
779	gpio_free(100);
780	return rc;
781}
782
783static int hdmi_cec_power(int on)
784{
785	static int prev_on;
786	int rc;
787
788	if (on == prev_on)
789		return 0;
790
791	if (on) {
792		rc = gpio_request(99, "HDMI_CEC_VAR");
793		if (rc) {
794			pr_err("'%s'(%d) gpio_request failed, rc=%d\n",
795				"HDMI_CEC_VAR", 99, rc);
796			goto error;
797		}
798		pr_debug("%s(on): success\n", __func__);
799	} else {
800		gpio_free(99);
801		pr_debug("%s(off): success\n", __func__);
802	}
803
804	prev_on = on;
805
806	return 0;
807error:
808	return rc;
809}
810#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL */
811
812void __init msm8930_init_fb(void)
813{
814	platform_device_register(&msm_fb_device);
815
816#ifdef CONFIG_FB_MSM_WRITEBACK_MSM_PANEL
817	platform_device_register(&wfd_panel_device);
818	platform_device_register(&wfd_device);
819#endif
820
821	platform_device_register(&mipi_dsi_novatek_panel_device);
822
823#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL
824	platform_device_register(&hdmi_msm_device);
825#endif
826
827	platform_device_register(&mipi_dsi_toshiba_panel_device);
828
829	msm_fb_register_device("mdp", &mdp_pdata);
830	msm_fb_register_device("mipi_dsi", &mipi_dsi_pdata);
831#ifdef CONFIG_MSM_BUS_SCALING
832	msm_fb_register_device("dtv", &dtv_pdata);
833#endif
834}
835
836void __init msm8930_allocate_fb_region(void)
837{
838	void *addr;
839	unsigned long size;
840
841	size = MSM_FB_SIZE;
842	addr = alloc_bootmem_align(size, 0x1000);
843	msm_fb_resources[0].start = __pa(addr);
844	msm_fb_resources[0].end = msm_fb_resources[0].start + size - 1;
845	pr_info("allocating %lu bytes at %p (%lx physical) for fb\n",
846			size, addr, __pa(addr));
847}