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/arch/powerpc/include/asm/lppaca.h

https://github.com/aicjofs/android_kernel_lge_v500_20d_f2fs
C Header | 217 lines | 111 code | 23 blank | 83 comment | 0 complexity | 0cdf18c6045b7ecf4ddf46d576e72ba1 MD5 | raw file
  1/*
  2 * lppaca.h
  3 * Copyright (C) 2001  Mike Corrigan IBM Corporation
  4 *
  5 * This program is free software; you can redistribute it and/or modify
  6 * it under the terms of the GNU General Public License as published by
  7 * the Free Software Foundation; either version 2 of the License, or
  8 * (at your option) any later version.
  9 *
 10 * This program is distributed in the hope that it will be useful,
 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 13 * GNU General Public License for more details.
 14 *
 15 * You should have received a copy of the GNU General Public License
 16 * along with this program; if not, write to the Free Software
 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 18 */
 19#ifndef _ASM_POWERPC_LPPACA_H
 20#define _ASM_POWERPC_LPPACA_H
 21#ifdef __KERNEL__
 22
 23/* These definitions relate to hypervisors that only exist when using
 24 * a server type processor
 25 */
 26#ifdef CONFIG_PPC_BOOK3S
 27
 28//=============================================================================
 29//
 30//	This control block contains the data that is shared between the
 31//	hypervisor (PLIC) and the OS.
 32//
 33//
 34//----------------------------------------------------------------------------
 35#include <linux/cache.h>
 36#include <linux/threads.h>
 37#include <asm/types.h>
 38#include <asm/mmu.h>
 39
 40/*
 41 * We only have to have statically allocated lppaca structs on
 42 * legacy iSeries, which supports at most 64 cpus.
 43 */
 44#define NR_LPPACAS	1
 45
 46
 47/* The Hypervisor barfs if the lppaca crosses a page boundary.  A 1k
 48 * alignment is sufficient to prevent this */
 49struct lppaca {
 50//=============================================================================
 51// CACHE_LINE_1 0x0000 - 0x007F Contains read-only data
 52// NOTE: The xDynXyz fields are fields that will be dynamically changed by
 53// PLIC when preparing to bring a processor online or when dispatching a
 54// virtual processor!
 55//=============================================================================
 56	u32	desc;			// Eye catcher 0xD397D781	x00-x03
 57	u16	size;			// Size of this struct		x04-x05
 58	u16	reserved1;		// Reserved			x06-x07
 59	u16	reserved2:14;		// Reserved			x08-x09
 60	u8	shared_proc:1;		// Shared processor indicator	...
 61	u8	secondary_thread:1;	// Secondary thread indicator	...
 62	volatile u8 dyn_proc_status:8;	// Dynamic Status of this proc	x0A-x0A
 63	u8	secondary_thread_count;	// Secondary thread count	x0B-x0B
 64	volatile u16 dyn_hv_phys_proc_index;// Dynamic HV Physical Proc Index0C-x0D
 65	volatile u16 dyn_hv_log_proc_index;// Dynamic HV Logical Proc Indexx0E-x0F
 66	u32	decr_val;   		// Value for Decr programming 	x10-x13
 67	u32	pmc_val;       		// Value for PMC regs         	x14-x17
 68	volatile u32 dyn_hw_node_id;	// Dynamic Hardware Node id	x18-x1B
 69	volatile u32 dyn_hw_proc_id;	// Dynamic Hardware Proc Id	x1C-x1F
 70	volatile u32 dyn_pir;		// Dynamic ProcIdReg value	x20-x23
 71	u32	dsei_data;           	// DSEI data                  	x24-x27
 72	u64	sprg3;               	// SPRG3 value                	x28-x2F
 73	u8	reserved3[40];		// Reserved			x30-x57
 74	volatile u8 vphn_assoc_counts[8]; // Virtual processor home node
 75					// associativity change counters x58-x5F
 76	u8	reserved4[32];		// Reserved			x60-x7F
 77
 78//=============================================================================
 79// CACHE_LINE_2 0x0080 - 0x00FF Contains local read-write data
 80//=============================================================================
 81	// This Dword contains a byte for each type of interrupt that can occur.
 82	// The IPI is a count while the others are just a binary 1 or 0.
 83	union {
 84		u64	any_int;
 85		struct {
 86			u16	reserved;	// Reserved - cleared by #mpasmbl
 87			u8	xirr_int;	// Indicates xXirrValue is valid or Immed IO
 88			u8	ipi_cnt;	// IPI Count
 89			u8	decr_int;	// DECR interrupt occurred
 90			u8	pdc_int;	// PDC interrupt occurred
 91			u8	quantum_int;	// Interrupt quantum reached
 92			u8	old_plic_deferred_ext_int;	// Old PLIC has a deferred XIRR pending
 93		} fields;
 94	} int_dword;
 95
 96	// Whenever any fields in this Dword are set then PLIC will defer the
 97	// processing of external interrupts.  Note that PLIC will store the
 98	// XIRR directly into the xXirrValue field so that another XIRR will
 99	// not be presented until this one clears.  The layout of the low
100	// 4-bytes of this Dword is up to SLIC - PLIC just checks whether the
101	// entire Dword is zero or not.  A non-zero value in the low order
102	// 2-bytes will result in SLIC being granted the highest thread
103	// priority upon return.  A 0 will return to SLIC as medium priority.
104	u64	plic_defer_ints_area;	// Entire Dword
105
106	// Used to pass the real SRR0/1 from PLIC to SLIC as well as to
107	// pass the target SRR0/1 from SLIC to PLIC on a SetAsrAndRfid.
108	u64	saved_srr0;		// Saved SRR0                   x10-x17
109	u64	saved_srr1;		// Saved SRR1                   x18-x1F
110
111	// Used to pass parms from the OS to PLIC for SetAsrAndRfid
112	u64	saved_gpr3;		// Saved GPR3                   x20-x27
113	u64	saved_gpr4;		// Saved GPR4                   x28-x2F
114	union {
115		u64	saved_gpr5;	/* Saved GPR5               x30-x37 */
116		struct {
117			u8	cede_latency_hint;  /*			x30 */
118			u8	reserved[7];        /*		    x31-x36 */
119		} fields;
120	} gpr5_dword;
121
122
123	u8	dtl_enable_mask;	// Dispatch Trace Log mask	x38-x38
124	u8	donate_dedicated_cpu;	// Donate dedicated CPU cycles  x39-x39
125	u8	fpregs_in_use;		// FP regs in use               x3A-x3A
126	u8	pmcregs_in_use;		// PMC regs in use              x3B-x3B
127	volatile u32 saved_decr;	// Saved Decr Value             x3C-x3F
128	volatile u64 emulated_time_base;// Emulated TB for this thread  x40-x47
129	volatile u64 cur_plic_latency;	// Unaccounted PLIC latency     x48-x4F
130	u64	tot_plic_latency;	// Accumulated PLIC latency     x50-x57
131	u64	wait_state_cycles;	// Wait cycles for this proc    x58-x5F
132	u64	end_of_quantum;		// TB at end of quantum         x60-x67
133	u64	pdc_saved_sprg1;	// Saved SPRG1 for PMC int      x68-x6F
134	u64	pdc_saved_srr0;		// Saved SRR0 for PMC int       x70-x77
135	volatile u32 virtual_decr;	// Virtual DECR for shared procsx78-x7B
136	u16	slb_count;		// # of SLBs to maintain        x7C-x7D
137	u8	idle;			// Indicate OS is idle          x7E
138	u8	vmxregs_in_use;		// VMX registers in use         x7F
139
140
141//=============================================================================
142// CACHE_LINE_3 0x0100 - 0x017F: This line is shared with other processors
143//=============================================================================
144	// This is the yield_count.  An "odd" value (low bit on) means that
145	// the processor is yielded (either because of an OS yield or a PLIC
146	// preempt).  An even value implies that the processor is currently
147	// executing.
148	// NOTE: This value will ALWAYS be zero for dedicated processors and
149	// will NEVER be zero for shared processors (ie, initialized to a 1).
150	volatile u32 yield_count;	// PLIC increments each dispatchx00-x03
151	volatile u32 dispersion_count;	// dispatch changed phys cpu    x04-x07
152	volatile u64 cmo_faults;	// CMO page fault count         x08-x0F
153	volatile u64 cmo_fault_time;	// CMO page fault time          x10-x17
154	u8	reserved7[104];		// Reserved                     x18-x7F
155
156//=============================================================================
157// CACHE_LINE_4-5 0x0180 - 0x027F Contains PMC interrupt data
158//=============================================================================
159	u32	page_ins;		// CMO Hint - # page ins by OS  x00-x03
160	u8	reserved8[148];		// Reserved                     x04-x97
161	volatile u64 dtl_idx;		// Dispatch Trace Log head idx	x98-x9F
162	u8	reserved9[96];		// Reserved                     xA0-xFF
163} __attribute__((__aligned__(0x400)));
164
165extern struct lppaca lppaca[];
166
167#define lppaca_of(cpu)	(*paca[cpu].lppaca_ptr)
168
169/*
170 * SLB shadow buffer structure as defined in the PAPR.  The save_area
171 * contains adjacent ESID and VSID pairs for each shadowed SLB.  The
172 * ESID is stored in the lower 64bits, then the VSID.
173 */
174struct slb_shadow {
175	u32	persistent;		// Number of persistent SLBs	x00-x03
176	u32	buffer_length;		// Total shadow buffer length	x04-x07
177	u64	reserved;		// Alignment			x08-x0f
178	struct	{
179		u64     esid;
180		u64	vsid;
181	} save_area[SLB_NUM_BOLTED];	//				x10-x40
182} ____cacheline_aligned;
183
184extern struct slb_shadow slb_shadow[];
185
186/*
187 * Layout of entries in the hypervisor's dispatch trace log buffer.
188 */
189struct dtl_entry {
190	u8	dispatch_reason;
191	u8	preempt_reason;
192	u16	processor_id;
193	u32	enqueue_to_dispatch_time;
194	u32	ready_to_enqueue_time;
195	u32	waiting_to_ready_time;
196	u64	timebase;
197	u64	fault_addr;
198	u64	srr0;
199	u64	srr1;
200};
201
202#define DISPATCH_LOG_BYTES	4096	/* bytes per cpu */
203#define N_DISPATCH_LOG		(DISPATCH_LOG_BYTES / sizeof(struct dtl_entry))
204
205extern struct kmem_cache *dtl_cache;
206
207/*
208 * When CONFIG_VIRT_CPU_ACCOUNTING = y, the cpu accounting code controls
209 * reading from the dispatch trace log.  If other code wants to consume
210 * DTL entries, it can set this pointer to a function that will get
211 * called once for each DTL entry that gets processed.
212 */
213extern void (*dtl_consumer)(struct dtl_entry *entry, u64 index);
214
215#endif /* CONFIG_PPC_BOOK3S */
216#endif /* __KERNEL__ */
217#endif /* _ASM_POWERPC_LPPACA_H */