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/arch/arm/mach-msm/board-8930.c

https://github.com/AICP/kernel_google_msm
C | 3041 lines | 2623 code | 296 blank | 122 comment | 97 complexity | c59f087fba96513c83752eb1769bb677 MD5 | raw file

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   1/* Copyright (c) 2011-2013, The Linux Foundation. All rights reserved.
   2 *
   3 * This program is free software; you can redistribute it and/or modify
   4 * it under the terms of the GNU General Public License version 2 and
   5 * only version 2 as published by the Free Software Foundation.
   6 *
   7 * This program is distributed in the hope that it will be useful,
   8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10 * GNU General Public License for more details.
  11 *
  12 */
  13#include <linux/kernel.h>
  14#include <linux/platform_device.h>
  15#include <linux/io.h>
  16#include <linux/irq.h>
  17#include <linux/i2c.h>
  18#include <linux/i2c/sx150x.h>
  19#include <linux/i2c/isl9519.h>
  20#include <linux/gpio.h>
  21#include <linux/msm_ssbi.h>
  22#include <linux/regulator/msm-gpio-regulator.h>
  23#include <linux/mfd/pm8xxx/pm8921.h>
  24#include <linux/mfd/pm8xxx/pm8xxx-adc.h>
  25#include <linux/regulator/consumer.h>
  26#include <linux/spi/spi.h>
  27#include <linux/slimbus/slimbus.h>
  28#include <linux/bootmem.h>
  29#ifdef CONFIG_ANDROID_PMEM
  30#include <linux/android_pmem.h>
  31#endif
  32#include <linux/dma-contiguous.h>
  33#include <linux/dma-mapping.h>
  34#include <linux/platform_data/qcom_crypto_device.h>
  35#include <linux/platform_data/qcom_wcnss_device.h>
  36#include <linux/leds.h>
  37#include <linux/leds-pm8xxx.h>
  38#include <linux/i2c/atmel_mxt_ts.h>
  39#include <linux/msm_tsens.h>
  40#include <linux/ks8851.h>
  41#include <linux/i2c/isa1200.h>
  42#include <linux/gpio_keys.h>
  43#include <linux/memory.h>
  44#include <linux/memblock.h>
  45#include <linux/msm_thermal.h>
  46
  47#include <linux/slimbus/slimbus.h>
  48#include <linux/mfd/wcd9xxx/core.h>
  49#include <linux/mfd/wcd9xxx/pdata.h>
  50
  51#ifdef CONFIG_STM_LIS3DH
  52#include <linux/input/lis3dh.h>
  53#endif
  54
  55#include <asm/mach-types.h>
  56#include <asm/mach/arch.h>
  57#include <asm/setup.h>
  58#include <asm/hardware/gic.h>
  59#include <asm/mach/mmc.h>
  60
  61#include <mach/board.h>
  62#include <mach/msm_iomap.h>
  63#include <mach/msm_spi.h>
  64#ifdef CONFIG_USB_MSM_OTG_72K
  65#include <mach/msm_hsusb.h>
  66#else
  67#include <linux/usb/msm_hsusb.h>
  68#endif
  69#include <linux/usb/android.h>
  70#include <mach/usbdiag.h>
  71#include <mach/socinfo.h>
  72#include <mach/rpm.h>
  73#include <mach/gpiomux.h>
  74#include <mach/msm_bus_board.h>
  75#include <mach/msm_memtypes.h>
  76#include <mach/dma.h>
  77#include <mach/msm_xo.h>
  78#include <mach/restart.h>
  79
  80#include <linux/msm_ion.h>
  81#include <mach/ion.h>
  82#include <mach/mdm2.h>
  83#include <mach/msm_rtb.h>
  84#include <linux/fmem.h>
  85#include <mach/msm_cache_dump.h>
  86
  87#include <mach/kgsl.h>
  88#ifdef CONFIG_INPUT_MPU3050
  89#include <linux/input/mpu3050.h>
  90#endif
  91
  92#include "timer.h"
  93#include "devices.h"
  94#include "devices-msm8x60.h"
  95#include "spm.h"
  96#include "pm.h"
  97#include <mach/cpuidle.h>
  98#include "rpm_resources.h"
  99#include <mach/mpm.h>
 100#include "clock.h"
 101#include "smd_private.h"
 102#include "pm-boot.h"
 103#include "msm_watchdog.h"
 104#include "board-8930.h"
 105#include "acpuclock-krait.h"
 106
 107static struct platform_device msm_fm_platform_init = {
 108	.name = "iris_fm",
 109	.id   = -1,
 110};
 111
 112#define KS8851_RST_GPIO		89
 113#define KS8851_IRQ_GPIO		90
 114#define HAP_SHIFT_LVL_OE_GPIO	47
 115
 116#define HDMI_MHL_MUX_GPIO       73
 117#define MHL_GPIO_INT            72
 118#define MHL_GPIO_RESET          71
 119#define MHL_GPIO_PWR_EN         5
 120
 121#if defined(CONFIG_GPIO_SX150X) || defined(CONFIG_GPIO_SX150X_MODULE)
 122
 123struct sx150x_platform_data msm8930_sx150x_data[] = {
 124	[SX150X_CAM] = {
 125		.gpio_base         = GPIO_CAM_EXPANDER_BASE,
 126		.oscio_is_gpo      = false,
 127		.io_pullup_ena     = 0x0,
 128		.io_pulldn_ena     = 0xc0,
 129		.io_open_drain_ena = 0x0,
 130		.irq_summary       = -1,
 131	},
 132};
 133
 134#endif
 135
 136#define MSM_PMEM_ADSP_SIZE         0x7800000
 137#define MSM_PMEM_AUDIO_SIZE        0x4CF000
 138#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
 139#define MSM_PMEM_SIZE 0x4000000 /* 64 Mbytes */
 140#else
 141#define MSM_PMEM_SIZE 0x2800000 /* 40 Mbytes */
 142#endif
 143#define MSM_LIQUID_PMEM_SIZE 0x4000000 /* 64 Mbytes */
 144
 145#ifdef CONFIG_MSM_MULTIMEDIA_USE_ION
 146#define HOLE_SIZE	0x20000
 147#define MSM_CONTIG_MEM_SIZE  0x65000
 148#ifdef CONFIG_MSM_IOMMU
 149#define MSM_ION_MM_SIZE            0x3800000 /* Need to be multiple of 64K */
 150#define MSM_ION_SF_SIZE            0x0
 151#define MSM_ION_QSECOM_SIZE	0x780000 /* (7.5MB) */
 152#define MSM_ION_HEAP_NUM	8
 153#else
 154#define MSM_ION_SF_SIZE		MSM_PMEM_SIZE
 155#define MSM_ION_MM_SIZE		MSM_PMEM_ADSP_SIZE
 156#define MSM_ION_QSECOM_SIZE	0x600000 /* (6MB) */
 157#define MSM_ION_HEAP_NUM	8
 158#endif
 159#define MSM_ION_MM_FW_SIZE	(0x200000 - HOLE_SIZE) /* 2MB - 128Kb */
 160#define MSM_ION_MFC_SIZE	SZ_8K
 161#define MSM_ION_AUDIO_SIZE	MSM_PMEM_AUDIO_SIZE
 162
 163#define MSM_LIQUID_ION_MM_SIZE (MSM_ION_MM_SIZE + 0x600000)
 164#define MSM_LIQUID_ION_SF_SIZE MSM_LIQUID_PMEM_SIZE
 165#define MSM_HDMI_PRIM_ION_SF_SIZE MSM_HDMI_PRIM_PMEM_SIZE
 166
 167#define MSM_MM_FW_SIZE	(0x200000 - HOLE_SIZE) /*2MB -128Kb */
 168#define MSM8930_FIXED_AREA_START (0xa0000000 - (MSM_ION_MM_FW_SIZE + \
 169								HOLE_SIZE))
 170#define MAX_FIXED_AREA_SIZE	0x10000000
 171#define MSM8930_FW_START	MSM8930_FIXED_AREA_START
 172#define MSM_ION_ADSP_SIZE	SZ_8M
 173
 174#else
 175#define MSM_CONTIG_MEM_SIZE  0x110C000
 176#define MSM_ION_HEAP_NUM	1
 177#endif
 178
 179#ifdef CONFIG_KERNEL_MSM_CONTIG_MEM_REGION
 180static unsigned msm_contig_mem_size = MSM_CONTIG_MEM_SIZE;
 181static int __init msm_contig_mem_size_setup(char *p)
 182{
 183	msm_contig_mem_size = memparse(p, NULL);
 184	return 0;
 185}
 186early_param("msm_contig_mem_size", msm_contig_mem_size_setup);
 187#endif
 188
 189#ifdef CONFIG_ANDROID_PMEM
 190static unsigned pmem_size = MSM_PMEM_SIZE;
 191static int __init pmem_size_setup(char *p)
 192{
 193	pmem_size = memparse(p, NULL);
 194	return 0;
 195}
 196early_param("pmem_size", pmem_size_setup);
 197
 198static unsigned pmem_adsp_size = MSM_PMEM_ADSP_SIZE;
 199
 200static int __init pmem_adsp_size_setup(char *p)
 201{
 202	pmem_adsp_size = memparse(p, NULL);
 203	return 0;
 204}
 205early_param("pmem_adsp_size", pmem_adsp_size_setup);
 206
 207static unsigned pmem_audio_size = MSM_PMEM_AUDIO_SIZE;
 208
 209static int __init pmem_audio_size_setup(char *p)
 210{
 211	pmem_audio_size = memparse(p, NULL);
 212	return 0;
 213}
 214early_param("pmem_audio_size", pmem_audio_size_setup);
 215#endif
 216
 217#ifdef CONFIG_ANDROID_PMEM
 218#ifndef CONFIG_MSM_MULTIMEDIA_USE_ION
 219static struct android_pmem_platform_data android_pmem_pdata = {
 220	.name = "pmem",
 221	.allocator_type = PMEM_ALLOCATORTYPE_ALLORNOTHING,
 222	.cached = 1,
 223	.memory_type = MEMTYPE_EBI1,
 224};
 225
 226static struct platform_device msm8930_android_pmem_device = {
 227	.name = "android_pmem",
 228	.id = 0,
 229	.dev = {.platform_data = &android_pmem_pdata},
 230};
 231
 232static struct android_pmem_platform_data android_pmem_adsp_pdata = {
 233	.name = "pmem_adsp",
 234	.allocator_type = PMEM_ALLOCATORTYPE_BITMAP,
 235	.cached = 0,
 236	.memory_type = MEMTYPE_EBI1,
 237};
 238static struct platform_device msm8930_android_pmem_adsp_device = {
 239	.name = "android_pmem",
 240	.id = 2,
 241	.dev = { .platform_data = &android_pmem_adsp_pdata },
 242};
 243
 244static struct android_pmem_platform_data android_pmem_audio_pdata = {
 245	.name = "pmem_audio",
 246	.allocator_type = PMEM_ALLOCATORTYPE_BITMAP,
 247	.cached = 0,
 248	.memory_type = MEMTYPE_EBI1,
 249};
 250
 251static struct platform_device msm8930_android_pmem_audio_device = {
 252	.name = "android_pmem",
 253	.id = 4,
 254	.dev = { .platform_data = &android_pmem_audio_pdata },
 255};
 256#endif /* CONFIG_MSM_MULTIMEDIA_USE_ION */
 257#endif /* CONFIG_ANDROID_PMEM */
 258
 259struct fmem_platform_data msm8930_fmem_pdata = {
 260};
 261
 262#define DSP_RAM_BASE_8960 0x8da00000
 263#define DSP_RAM_SIZE_8960 0x1800000
 264static int dspcrashd_pdata_8960 = 0xDEADDEAD;
 265
 266static struct resource resources_dspcrashd_8960[] = {
 267	{
 268		.name   = "msm_dspcrashd",
 269		.start  = DSP_RAM_BASE_8960,
 270		.end    = DSP_RAM_BASE_8960 + DSP_RAM_SIZE_8960,
 271		.flags  = IORESOURCE_DMA,
 272	},
 273};
 274
 275static struct platform_device msm_device_dspcrashd_8960 = {
 276	.name           = "msm_dspcrashd",
 277	.num_resources  = ARRAY_SIZE(resources_dspcrashd_8960),
 278	.resource       = resources_dspcrashd_8960,
 279	.dev = { .platform_data = &dspcrashd_pdata_8960 },
 280};
 281
 282static struct memtype_reserve msm8930_reserve_table[] __initdata = {
 283	[MEMTYPE_SMI] = {
 284	},
 285	[MEMTYPE_EBI0] = {
 286		.flags	=	MEMTYPE_FLAGS_1M_ALIGN,
 287	},
 288	[MEMTYPE_EBI1] = {
 289		.flags	=	MEMTYPE_FLAGS_1M_ALIGN,
 290	},
 291};
 292
 293
 294static void __init reserve_rtb_memory(void)
 295{
 296#if defined(CONFIG_MSM_RTB)
 297	msm8930_reserve_table[MEMTYPE_EBI1].size += msm8930_rtb_pdata.size;
 298#endif
 299}
 300
 301static void __init size_pmem_devices(void)
 302{
 303#ifdef CONFIG_ANDROID_PMEM
 304#ifndef CONFIG_MSM_MULTIMEDIA_USE_ION
 305	android_pmem_adsp_pdata.size = pmem_adsp_size;
 306	android_pmem_pdata.size = pmem_size;
 307	android_pmem_audio_pdata.size = MSM_PMEM_AUDIO_SIZE;
 308#endif /*CONFIG_MSM_MULTIMEDIA_USE_ION*/
 309#endif /*CONFIG_ANDROID_PMEM*/
 310}
 311
 312#ifdef CONFIG_ANDROID_PMEM
 313#ifndef CONFIG_MSM_MULTIMEDIA_USE_ION
 314static void __init reserve_memory_for(struct android_pmem_platform_data *p)
 315{
 316	msm8930_reserve_table[p->memory_type].size += p->size;
 317}
 318#endif /*CONFIG_MSM_MULTIMEDIA_USE_ION*/
 319#endif /*CONFIG_ANDROID_PMEM*/
 320
 321static void __init reserve_pmem_memory(void)
 322{
 323#ifdef CONFIG_ANDROID_PMEM
 324#ifndef CONFIG_MSM_MULTIMEDIA_USE_ION
 325	reserve_memory_for(&android_pmem_adsp_pdata);
 326	reserve_memory_for(&android_pmem_pdata);
 327	reserve_memory_for(&android_pmem_audio_pdata);
 328#endif /*CONFIG_MSM_MULTIMEDIA_USE_ION*/
 329	msm8930_reserve_table[MEMTYPE_EBI1].size += msm_contig_mem_size;
 330#endif /*CONFIG_ANDROID_PMEM*/
 331}
 332
 333static int msm8930_paddr_to_memtype(unsigned int paddr)
 334{
 335	return MEMTYPE_EBI1;
 336}
 337
 338#define FMEM_ENABLED 0
 339#ifdef CONFIG_ION_MSM
 340#ifdef CONFIG_MSM_MULTIMEDIA_USE_ION
 341static struct ion_cp_heap_pdata cp_mm_msm8930_ion_pdata = {
 342	.permission_type = IPT_TYPE_MM_CARVEOUT,
 343	.align = PAGE_SIZE,
 344	.reusable = FMEM_ENABLED,
 345	.mem_is_fmem = FMEM_ENABLED,
 346	.fixed_position = FIXED_MIDDLE,
 347	.is_cma	= 1,
 348	.no_nonsecure_alloc = 1,
 349};
 350
 351static struct ion_cp_heap_pdata cp_mfc_msm8930_ion_pdata = {
 352	.permission_type = IPT_TYPE_MFC_SHAREDMEM,
 353	.align = PAGE_SIZE,
 354	.reusable = 0,
 355	.mem_is_fmem = FMEM_ENABLED,
 356	.fixed_position = FIXED_HIGH,
 357	.no_nonsecure_alloc = 1,
 358};
 359
 360static struct ion_co_heap_pdata co_msm8930_ion_pdata = {
 361	.adjacent_mem_id = INVALID_HEAP_ID,
 362	.align = PAGE_SIZE,
 363	.mem_is_fmem = 0,
 364};
 365
 366static struct ion_co_heap_pdata fw_co_msm8930_ion_pdata = {
 367	.adjacent_mem_id = ION_CP_MM_HEAP_ID,
 368	.align = SZ_128K,
 369	.mem_is_fmem = FMEM_ENABLED,
 370	.fixed_position = FIXED_LOW,
 371};
 372#endif
 373
 374
 375static u64 msm_dmamask = DMA_BIT_MASK(32);
 376
 377static struct platform_device ion_mm_heap_device = {
 378	.name = "ion-mm-heap-device",
 379	.id = -1,
 380	.dev = {
 381		.dma_mask = &msm_dmamask,
 382		.coherent_dma_mask = DMA_BIT_MASK(32),
 383	}
 384};
 385
 386static struct platform_device ion_adsp_heap_device = {
 387	.name = "ion-adsp-heap-device",
 388	.id = -1,
 389	.dev = {
 390		.dma_mask = &msm_dmamask,
 391		.coherent_dma_mask = DMA_BIT_MASK(32),
 392	}
 393};
 394/**
 395 * These heaps are listed in the order they will be allocated. Due to
 396 * video hardware restrictions and content protection the FW heap has to
 397 * be allocated adjacent (below) the MM heap and the MFC heap has to be
 398 * allocated after the MM heap to ensure MFC heap is not more than 256MB
 399 * away from the base address of the FW heap.
 400 * However, the order of FW heap and MM heap doesn't matter since these
 401 * two heaps are taken care of by separate code to ensure they are adjacent
 402 * to each other.
 403 * Don't swap the order unless you know what you are doing!
 404 */
 405struct ion_platform_heap msm8930_heaps[] = {
 406		{
 407			.id	= ION_SYSTEM_HEAP_ID,
 408			.type	= ION_HEAP_TYPE_SYSTEM,
 409			.name	= ION_VMALLOC_HEAP_NAME,
 410		},
 411#ifdef CONFIG_MSM_MULTIMEDIA_USE_ION
 412		{
 413			.id	= ION_CP_MM_HEAP_ID,
 414			.type	= ION_HEAP_TYPE_CP,
 415			.name	= ION_MM_HEAP_NAME,
 416			.size	= MSM_ION_MM_SIZE,
 417			.memory_type = ION_EBI_TYPE,
 418			.extra_data = (void *) &cp_mm_msm8930_ion_pdata,
 419			.priv	= &ion_mm_heap_device.dev
 420		},
 421		{
 422			.id	= ION_MM_FIRMWARE_HEAP_ID,
 423			.type	= ION_HEAP_TYPE_CARVEOUT,
 424			.name	= ION_MM_FIRMWARE_HEAP_NAME,
 425			.size	= MSM_ION_MM_FW_SIZE,
 426			.memory_type = ION_EBI_TYPE,
 427			.extra_data = (void *) &fw_co_msm8930_ion_pdata,
 428		},
 429		{
 430			.id	= ION_CP_MFC_HEAP_ID,
 431			.type	= ION_HEAP_TYPE_CP,
 432			.name	= ION_MFC_HEAP_NAME,
 433			.size	= MSM_ION_MFC_SIZE,
 434			.memory_type = ION_EBI_TYPE,
 435			.extra_data = (void *) &cp_mfc_msm8930_ion_pdata,
 436		},
 437#ifndef CONFIG_MSM_IOMMU
 438		{
 439			.id	= ION_SF_HEAP_ID,
 440			.type	= ION_HEAP_TYPE_CARVEOUT,
 441			.name	= ION_SF_HEAP_NAME,
 442			.size	= MSM_ION_SF_SIZE,
 443			.memory_type = ION_EBI_TYPE,
 444			.extra_data = (void *) &co_msm8930_ion_pdata,
 445		},
 446#endif
 447		{
 448			.id	= ION_IOMMU_HEAP_ID,
 449			.type	= ION_HEAP_TYPE_IOMMU,
 450			.name	= ION_IOMMU_HEAP_NAME,
 451		},
 452		{
 453			.id	= ION_QSECOM_HEAP_ID,
 454			.type	= ION_HEAP_TYPE_CARVEOUT,
 455			.name	= ION_QSECOM_HEAP_NAME,
 456			.size	= MSM_ION_QSECOM_SIZE,
 457			.memory_type = ION_EBI_TYPE,
 458			.extra_data = (void *) &co_msm8930_ion_pdata,
 459		},
 460		{
 461			.id	= ION_AUDIO_HEAP_ID,
 462			.type	= ION_HEAP_TYPE_CARVEOUT,
 463			.name	= ION_AUDIO_HEAP_NAME,
 464			.size	= MSM_ION_AUDIO_SIZE,
 465			.memory_type = ION_EBI_TYPE,
 466			.extra_data = (void *) &co_msm8930_ion_pdata,
 467		},
 468		{
 469			.id	= ION_ADSP_HEAP_ID,
 470			.type	= ION_HEAP_TYPE_DMA,
 471			.name	= ION_ADSP_HEAP_NAME,
 472			.size	= MSM_ION_ADSP_SIZE,
 473			.memory_type = ION_EBI_TYPE,
 474			.extra_data = (void *) &co_msm8930_ion_pdata,
 475			.priv	= &ion_adsp_heap_device.dev,
 476		},
 477#endif
 478};
 479
 480static struct ion_platform_data msm8930_ion_pdata = {
 481	.nr = MSM_ION_HEAP_NUM,
 482	.heaps = msm8930_heaps,
 483
 484};
 485
 486static struct platform_device msm8930_ion_dev = {
 487	.name = "ion-msm",
 488	.id = 1,
 489	.dev = { .platform_data = &msm8930_ion_pdata },
 490};
 491#endif
 492
 493struct platform_device msm8930_fmem_device = {
 494	.name = "fmem",
 495	.id = 1,
 496	.dev = { .platform_data = &msm8930_fmem_pdata },
 497};
 498
 499static void __init reserve_mem_for_ion(enum ion_memory_types mem_type,
 500				      unsigned long size)
 501{
 502	msm8930_reserve_table[mem_type].size += size;
 503}
 504
 505static void __init msm8930_reserve_fixed_area(unsigned long fixed_area_size)
 506{
 507#if defined(CONFIG_ION_MSM) && defined(CONFIG_MSM_MULTIMEDIA_USE_ION)
 508	int ret;
 509
 510	if (fixed_area_size > MAX_FIXED_AREA_SIZE)
 511		panic("fixed area size is larger than %dM\n",
 512			MAX_FIXED_AREA_SIZE >> 20);
 513
 514	reserve_info->fixed_area_size = fixed_area_size;
 515	reserve_info->fixed_area_start = MSM8930_FW_START;
 516
 517	ret = memblock_remove(reserve_info->fixed_area_start,
 518		reserve_info->fixed_area_size);
 519	BUG_ON(ret);
 520#endif
 521}
 522
 523/**
 524 * Reserve memory for ION and calculate amount of reusable memory for fmem.
 525 * We only reserve memory for heaps that are not reusable. However, we only
 526 * support one reusable heap at the moment so we ignore the reusable flag for
 527 * other than the first heap with reusable flag set. Also handle special case
 528 * for video heaps (MM,FW, and MFC). Video requires heaps MM and MFC to be
 529 * at a higher address than FW in addition to not more than 256MB away from the
 530 * base address of the firmware. This means that if MM is reusable the other
 531 * two heaps must be allocated in the same region as FW. This is handled by the
 532 * mem_is_fmem flag in the platform data. In addition the MM heap must be
 533 * adjacent to the FW heap for content protection purposes.
 534 */
 535static void __init reserve_ion_memory(void)
 536{
 537#if defined(CONFIG_ION_MSM) && defined(CONFIG_MSM_MULTIMEDIA_USE_ION)
 538	unsigned int i;
 539	int ret;
 540	unsigned int fixed_size = 0;
 541	unsigned int fixed_low_size, fixed_middle_size, fixed_high_size;
 542	unsigned long fixed_low_start, fixed_middle_start, fixed_high_start;
 543	unsigned long cma_alignment;
 544	unsigned int low_use_cma = 0;
 545	unsigned int middle_use_cma = 0;
 546	unsigned int high_use_cma = 0;
 547
 548	fixed_low_size = 0;
 549	fixed_middle_size = 0;
 550	fixed_high_size = 0;
 551
 552	cma_alignment = PAGE_SIZE << max(MAX_ORDER, pageblock_order);
 553
 554	for (i = 0; i < msm8930_ion_pdata.nr; ++i) {
 555		struct ion_platform_heap *heap =
 556						&(msm8930_ion_pdata.heaps[i]);
 557
 558		int use_cma = 0;
 559
 560		if (heap->extra_data) {
 561			int fixed_position = NOT_FIXED;
 562
 563			switch ((int) heap->type) {
 564			case ION_HEAP_TYPE_CP:
 565				if (((struct ion_cp_heap_pdata *)
 566					heap->extra_data)->is_cma) {
 567					heap->size = ALIGN(heap->size,
 568						cma_alignment);
 569						use_cma = 1;
 570				}
 571				fixed_position = ((struct ion_cp_heap_pdata *)
 572					heap->extra_data)->fixed_position;
 573				break;
 574			case ION_HEAP_TYPE_DMA:
 575				use_cma = 1;
 576				/* Purposely fall through here */
 577			case ION_HEAP_TYPE_CARVEOUT:
 578				fixed_position = ((struct ion_co_heap_pdata *)
 579					heap->extra_data)->fixed_position;
 580				break;
 581			default:
 582				break;
 583			}
 584
 585			if (fixed_position != NOT_FIXED)
 586				fixed_size += heap->size;
 587			else
 588				reserve_mem_for_ion(MEMTYPE_EBI1, heap->size);
 589
 590			if (fixed_position == FIXED_LOW) {
 591				fixed_low_size += heap->size;
 592				low_use_cma = use_cma;
 593			} else if (fixed_position == FIXED_MIDDLE) {
 594				fixed_middle_size += heap->size;
 595				middle_use_cma = use_cma;
 596			} else if (fixed_position == FIXED_HIGH) {
 597				fixed_high_size += heap->size;
 598				high_use_cma = use_cma;
 599			} else if (use_cma) {
 600				/*
 601				 * Heaps that use CMA but are not part of the
 602				 * fixed set. Create wherever.
 603				 */
 604				dma_declare_contiguous(
 605					heap->priv,
 606					heap->size,
 607					0,
 608					0xb0000000);
 609			}
 610		}
 611	}
 612
 613	if (!fixed_size)
 614		return;
 615	/*
 616	 * Given the setup for the fixed area, we can't round up all sizes.
 617	 * Some sizes must be set up exactly and aligned correctly. Incorrect
 618	 * alignments are considered a configuration issue
 619	 */
 620
 621	fixed_low_start = MSM8930_FIXED_AREA_START;
 622	if (low_use_cma) {
 623		BUG_ON(!IS_ALIGNED(fixed_low_size + HOLE_SIZE, cma_alignment));
 624		BUG_ON(!IS_ALIGNED(fixed_low_start, cma_alignment));
 625	} else {
 626		BUG_ON(!IS_ALIGNED(fixed_low_size + HOLE_SIZE, SECTION_SIZE));
 627		ret = memblock_remove(fixed_low_start,
 628				      fixed_low_size + HOLE_SIZE);
 629		BUG_ON(ret);
 630	}
 631
 632	fixed_middle_start = fixed_low_start + fixed_low_size + HOLE_SIZE;
 633	if (middle_use_cma) {
 634		BUG_ON(!IS_ALIGNED(fixed_middle_start, cma_alignment));
 635		BUG_ON(!IS_ALIGNED(fixed_middle_size, cma_alignment));
 636	} else {
 637		BUG_ON(!IS_ALIGNED(fixed_middle_size, SECTION_SIZE));
 638		ret = memblock_remove(fixed_middle_start, fixed_middle_size);
 639		BUG_ON(ret);
 640	}
 641
 642	fixed_high_start = fixed_middle_start + fixed_middle_size;
 643	if (high_use_cma) {
 644		fixed_high_size = ALIGN(fixed_high_size, cma_alignment);
 645		BUG_ON(!IS_ALIGNED(fixed_high_start, cma_alignment));
 646	} else {
 647		/* This is the end of the fixed area so it's okay to round up */
 648		fixed_high_size = ALIGN(fixed_high_size, SECTION_SIZE);
 649		ret = memblock_remove(fixed_high_start, fixed_high_size);
 650		BUG_ON(ret);
 651	}
 652
 653	for (i = 0; i < msm8930_ion_pdata.nr; ++i) {
 654		struct ion_platform_heap *heap = &(msm8930_ion_pdata.heaps[i]);
 655
 656		if (heap->extra_data) {
 657			int fixed_position = NOT_FIXED;
 658			struct ion_cp_heap_pdata *pdata = NULL;
 659
 660			switch ((int) heap->type) {
 661			case ION_HEAP_TYPE_CP:
 662				pdata =
 663				(struct ion_cp_heap_pdata *)heap->extra_data;
 664				fixed_position = pdata->fixed_position;
 665				break;
 666			case ION_HEAP_TYPE_DMA:
 667			case ION_HEAP_TYPE_CARVEOUT:
 668				fixed_position = ((struct ion_co_heap_pdata *)
 669					heap->extra_data)->fixed_position;
 670				break;
 671			default:
 672				break;
 673			}
 674
 675			switch (fixed_position) {
 676			case FIXED_LOW:
 677				heap->base = fixed_low_start;
 678				break;
 679			case FIXED_MIDDLE:
 680				heap->base = fixed_middle_start;
 681				if (middle_use_cma)
 682					dma_declare_contiguous(
 683						&ion_mm_heap_device.dev,
 684						heap->size,
 685						fixed_middle_start,
 686						0xa0000000);
 687				pdata->secure_base = fixed_middle_start
 688							- HOLE_SIZE;
 689				pdata->secure_size = HOLE_SIZE + heap->size;
 690				break;
 691			case FIXED_HIGH:
 692				heap->base = fixed_high_start;
 693				break;
 694			default:
 695				break;
 696			}
 697		}
 698	}
 699#endif
 700}
 701
 702static void __init reserve_mdp_memory(void)
 703{
 704	msm8930_mdp_writeback(msm8930_reserve_table);
 705}
 706
 707#ifdef CONFIG_MSM_CACHE_DUMP
 708static void __init reserve_cache_dump_memory(void)
 709{
 710	unsigned int total;
 711
 712	total = msm8930_cache_dump_pdata.l1_size +
 713		msm8930_cache_dump_pdata.l2_size;
 714	msm8930_reserve_table[MEMTYPE_EBI1].size += total;
 715}
 716#else
 717static void __init reserve_cache_dump_memory(void) { }
 718#endif
 719
 720static void __init msm8930_calculate_reserve_sizes(void)
 721{
 722	size_pmem_devices();
 723	reserve_pmem_memory();
 724	reserve_ion_memory();
 725	reserve_mdp_memory();
 726	reserve_rtb_memory();
 727	reserve_cache_dump_memory();
 728}
 729
 730static struct reserve_info msm8930_reserve_info __initdata = {
 731	.memtype_reserve_table = msm8930_reserve_table,
 732	.calculate_reserve_sizes = msm8930_calculate_reserve_sizes,
 733	.reserve_fixed_area = msm8930_reserve_fixed_area,
 734	.paddr_to_memtype = msm8930_paddr_to_memtype,
 735};
 736
 737static int msm8930_memory_bank_size(void)
 738{
 739	return 1<<29;
 740}
 741
 742static void __init locate_unstable_memory(void)
 743{
 744	struct membank *mb = &meminfo.bank[meminfo.nr_banks - 1];
 745	unsigned long bank_size;
 746	unsigned long low, high;
 747
 748	bank_size = msm8930_memory_bank_size();
 749	low = meminfo.bank[0].start;
 750	high = mb->start + mb->size;
 751
 752	/* Check if 32 bit overflow occured */
 753	if (high < mb->start)
 754		high -= PAGE_SIZE;
 755
 756	if (high < MAX_FIXED_AREA_SIZE + MSM8930_FIXED_AREA_START)
 757		panic("fixed area extends beyond end of memory\n");
 758
 759	low &= ~(bank_size - 1);
 760
 761	if (high - low <= bank_size)
 762		goto no_dmm;
 763
 764	msm8930_reserve_info.bank_size = bank_size;
 765#ifdef CONFIG_ENABLE_DMM
 766	msm8930_reserve_info.low_unstable_address = mb->start -
 767					MIN_MEMORY_BLOCK_SIZE + mb->size;
 768	msm8930_reserve_info.max_unstable_size = MIN_MEMORY_BLOCK_SIZE;
 769	pr_info("low unstable address %lx max size %lx bank size %lx\n",
 770		msm8930_reserve_info.low_unstable_address,
 771		msm8930_reserve_info.max_unstable_size,
 772		msm8930_reserve_info.bank_size);
 773	return;
 774#endif
 775no_dmm:
 776	msm8930_reserve_info.low_unstable_address = high;
 777	msm8930_reserve_info.max_unstable_size = 0;
 778}
 779
 780static void __init place_movable_zone(void)
 781{
 782#ifdef CONFIG_ENABLE_DMM
 783	movable_reserved_start = msm8930_reserve_info.low_unstable_address;
 784	movable_reserved_size = msm8930_reserve_info.max_unstable_size;
 785	pr_info("movable zone start %lx size %lx\n",
 786		movable_reserved_start, movable_reserved_size);
 787#endif
 788}
 789
 790static void __init msm8930_early_memory(void)
 791{
 792	reserve_info = &msm8930_reserve_info;
 793	locate_unstable_memory();
 794	place_movable_zone();
 795}
 796
 797static void __init msm8930_reserve(void)
 798{
 799	msm_reserve();
 800}
 801
 802static int msm8930_change_memory_power(u64 start, u64 size,
 803	int change_type)
 804{
 805	return soc_change_memory_power(start, size, change_type);
 806}
 807
 808static void __init msm8930_allocate_memory_regions(void)
 809{
 810	msm8930_allocate_fb_region();
 811}
 812
 813#ifdef CONFIG_WCD9304_CODEC
 814
 815#define SITAR_INTERRUPT_BASE (NR_MSM_IRQS + NR_GPIO_IRQS + NR_PM8921_IRQS)
 816
 817/* Micbias setting is based on 8660 CDP/MTP/FLUID requirement
 818 * 4 micbiases are used to power various analog and digital
 819 * microphones operating at 1800 mV. Technically, all micbiases
 820 * can source from single cfilter since all microphones operate
 821 * at the same voltage level. The arrangement below is to make
 822 * sure all cfilters are exercised. LDO_H regulator ouput level
 823 * does not need to be as high as 2.85V. It is choosen for
 824 * microphone sensitivity purpose.
 825 */
 826static struct wcd9xxx_pdata sitar_platform_data = {
 827		.slimbus_slave_device = {
 828		.name = "sitar-slave",
 829		.e_addr = {0, 0, 0x00, 0, 0x17, 2},
 830	},
 831	.irq = MSM_GPIO_TO_INT(62),
 832	.irq_base = SITAR_INTERRUPT_BASE,
 833	.num_irqs = NR_WCD9XXX_IRQS,
 834	.reset_gpio = 42,
 835	.micbias = {
 836		.ldoh_v = SITAR_LDOH_2P85_V,
 837		.cfilt1_mv = 1800,
 838		.cfilt2_mv = 1800,
 839		.bias1_cfilt_sel = SITAR_CFILT1_SEL,
 840		.bias2_cfilt_sel = SITAR_CFILT2_SEL,
 841		.bias1_cap_mode = MICBIAS_EXT_BYP_CAP,
 842		.bias2_cap_mode = MICBIAS_NO_EXT_BYP_CAP,
 843	},
 844	.regulator = {
 845	{
 846		.name = "CDC_VDD_CP",
 847		.min_uV = 1800000,
 848		.max_uV = 2200000,
 849		.optimum_uA = WCD9XXX_CDC_VDDA_CP_CUR_MAX,
 850	},
 851	{
 852		.name = "CDC_VDDA_RX",
 853		.min_uV = 1800000,
 854		.max_uV = 1800000,
 855		.optimum_uA = WCD9XXX_CDC_VDDA_RX_CUR_MAX,
 856	},
 857	{
 858		.name = "CDC_VDDA_TX",
 859		.min_uV = 1800000,
 860		.max_uV = 1800000,
 861		.optimum_uA = WCD9XXX_CDC_VDDA_TX_CUR_MAX,
 862	},
 863	{
 864		.name = "VDDIO_CDC",
 865		.min_uV = 1800000,
 866		.max_uV = 1800000,
 867		.optimum_uA = WCD9XXX_VDDIO_CDC_CUR_MAX,
 868	},
 869	{
 870		.name = "VDDD_CDC_D",
 871		.min_uV = 1200000,
 872		.max_uV = 1250000,
 873		.optimum_uA = WCD9XXX_VDDD_CDC_D_CUR_MAX,
 874	},
 875	{
 876		.name = "CDC_VDDA_A_1P2V",
 877		.min_uV = 1200000,
 878		.max_uV = 1250000,
 879		.optimum_uA = WCD9XXX_VDDD_CDC_A_CUR_MAX,
 880	},
 881	},
 882};
 883
 884static struct slim_device msm_slim_sitar = {
 885	.name = "sitar-slim",
 886	.e_addr = {0, 1, 0x00, 0, 0x17, 2},
 887	.dev = {
 888	.platform_data = &sitar_platform_data,
 889	},
 890};
 891
 892static struct wcd9xxx_pdata sitar1p1_platform_data = {
 893		.slimbus_slave_device = {
 894		.name = "sitar-slave",
 895		.e_addr = {0, 0, 0x70, 0, 0x17, 2},
 896	},
 897	.irq = MSM_GPIO_TO_INT(62),
 898	.irq_base = SITAR_INTERRUPT_BASE,
 899	.num_irqs = NR_WCD9XXX_IRQS,
 900	.reset_gpio = 42,
 901	.micbias = {
 902		.ldoh_v = SITAR_LDOH_2P85_V,
 903		.cfilt1_mv = 1800,
 904		.cfilt2_mv = 1800,
 905		.bias1_cfilt_sel = SITAR_CFILT1_SEL,
 906		.bias2_cfilt_sel = SITAR_CFILT2_SEL,
 907		.bias1_cap_mode = MICBIAS_EXT_BYP_CAP,
 908		.bias2_cap_mode = MICBIAS_NO_EXT_BYP_CAP,
 909	},
 910	.regulator = {
 911	{
 912		.name = "CDC_VDD_CP",
 913		.min_uV = 1800000,
 914		.max_uV = 2200000,
 915		.optimum_uA = WCD9XXX_CDC_VDDA_CP_CUR_MAX,
 916	},
 917	{
 918		.name = "CDC_VDDA_RX",
 919		.min_uV = 1800000,
 920		.max_uV = 1800000,
 921		.optimum_uA = WCD9XXX_CDC_VDDA_RX_CUR_MAX,
 922	},
 923	{
 924		.name = "CDC_VDDA_TX",
 925		.min_uV = 1800000,
 926		.max_uV = 1800000,
 927		.optimum_uA = WCD9XXX_CDC_VDDA_TX_CUR_MAX,
 928	},
 929	{
 930		.name = "VDDIO_CDC",
 931		.min_uV = 1800000,
 932		.max_uV = 1800000,
 933		.optimum_uA = WCD9XXX_VDDIO_CDC_CUR_MAX,
 934	},
 935	{
 936		.name = "VDDD_CDC_D",
 937		.min_uV = 1200000,
 938		.max_uV = 1250000,
 939		.optimum_uA = WCD9XXX_VDDD_CDC_D_CUR_MAX,
 940	},
 941	{
 942		.name = "CDC_VDDA_A_1P2V",
 943		.min_uV = 1200000,
 944		.max_uV = 1250000,
 945		.optimum_uA = WCD9XXX_VDDD_CDC_A_CUR_MAX,
 946	},
 947	},
 948};
 949
 950static struct slim_device msm_slim_sitar1p1 = {
 951	.name = "sitar1p1-slim",
 952	.e_addr = {0, 1, 0x70, 0, 0x17, 2},
 953	.dev = {
 954	.platform_data = &sitar1p1_platform_data,
 955	},
 956};
 957#endif
 958
 959
 960static struct slim_boardinfo msm_slim_devices[] = {
 961#ifdef CONFIG_WCD9304_CODEC
 962	{
 963		.bus_num = 1,
 964		.slim_slave = &msm_slim_sitar,
 965	},
 966	{
 967		.bus_num = 1,
 968		.slim_slave = &msm_slim_sitar1p1,
 969	},
 970#endif
 971	/* add more slimbus slaves as needed */
 972};
 973
 974#define MSM_WCNSS_PHYS	0x03000000
 975#define MSM_WCNSS_SIZE	0x280000
 976
 977static struct resource resources_wcnss_wlan[] = {
 978	{
 979		.start	= RIVA_APPS_WLAN_RX_DATA_AVAIL_IRQ,
 980		.end	= RIVA_APPS_WLAN_RX_DATA_AVAIL_IRQ,
 981		.name	= "wcnss_wlanrx_irq",
 982		.flags	= IORESOURCE_IRQ,
 983	},
 984	{
 985		.start	= RIVA_APPS_WLAN_DATA_XFER_DONE_IRQ,
 986		.end	= RIVA_APPS_WLAN_DATA_XFER_DONE_IRQ,
 987		.name	= "wcnss_wlantx_irq",
 988		.flags	= IORESOURCE_IRQ,
 989	},
 990	{
 991		.start	= MSM_WCNSS_PHYS,
 992		.end	= MSM_WCNSS_PHYS + MSM_WCNSS_SIZE - 1,
 993		.name	= "wcnss_mmio",
 994		.flags	= IORESOURCE_MEM,
 995	},
 996	{
 997		.start	= 84,
 998		.end	= 88,
 999		.name	= "wcnss_gpios_5wire",
1000		.flags	= IORESOURCE_IO,
1001	},
1002};
1003
1004static struct qcom_wcnss_opts qcom_wcnss_pdata = {
1005	.has_48mhz_xo	= 1,
1006};
1007
1008static struct platform_device msm_device_wcnss_wlan = {
1009	.name		= "wcnss_wlan",
1010	.id		= 0,
1011	.num_resources	= ARRAY_SIZE(resources_wcnss_wlan),
1012	.resource	= resources_wcnss_wlan,
1013	.dev		= {.platform_data = &qcom_wcnss_pdata},
1014};
1015
1016#ifdef CONFIG_QSEECOM
1017/* qseecom bus scaling */
1018static struct msm_bus_vectors qseecom_clks_init_vectors[] = {
1019	{
1020		.src = MSM_BUS_MASTER_SPS,
1021		.dst = MSM_BUS_SLAVE_EBI_CH0,
1022		.ib = 0,
1023		.ab = 0,
1024	},
1025	{
1026		.src = MSM_BUS_MASTER_SPS,
1027		.dst = MSM_BUS_SLAVE_SPS,
1028		.ib = 0,
1029		.ab = 0,
1030	},
1031	{
1032		.src = MSM_BUS_MASTER_SPDM,
1033		.dst = MSM_BUS_SLAVE_SPDM,
1034		.ib = 0,
1035		.ab = 0,
1036	},
1037};
1038
1039static struct msm_bus_vectors qseecom_enable_dfab_vectors[] = {
1040	{
1041		.src = MSM_BUS_MASTER_SPS,
1042		.dst = MSM_BUS_SLAVE_EBI_CH0,
1043		.ib = (492 * 8) * 1000000UL,
1044		.ab = (492 * 8) *  100000UL,
1045	},
1046	{
1047		.src = MSM_BUS_MASTER_SPS,
1048		.dst = MSM_BUS_SLAVE_SPS,
1049		.ib = (492 * 8) * 1000000UL,
1050		.ab = (492 * 8) *  100000UL,
1051	},
1052	{
1053		.src = MSM_BUS_MASTER_SPDM,
1054		.dst = MSM_BUS_SLAVE_SPDM,
1055		.ib = 0,
1056		.ab = 0,
1057	},
1058};
1059
1060static struct msm_bus_vectors qseecom_enable_sfpb_vectors[] = {
1061	{
1062		.src = MSM_BUS_MASTER_SPS,
1063		.dst = MSM_BUS_SLAVE_EBI_CH0,
1064		.ib = 0,
1065		.ab = 0,
1066	},
1067	{
1068		.src = MSM_BUS_MASTER_SPS,
1069		.dst = MSM_BUS_SLAVE_SPS,
1070		.ib = 0,
1071		.ab = 0,
1072	},
1073	{
1074		.src = MSM_BUS_MASTER_SPDM,
1075		.dst = MSM_BUS_SLAVE_SPDM,
1076		.ib = (64 * 8) * 1000000UL,
1077		.ab = (64 * 8) *  100000UL,
1078	},
1079};
1080
1081static struct msm_bus_vectors qseecom_enable_dfab_sfpb_vectors[] = {
1082	{
1083		.src = MSM_BUS_MASTER_SPS,
1084		.dst = MSM_BUS_SLAVE_EBI_CH0,
1085		.ib = (492 * 8) * 1000000UL,
1086		.ab = (492 * 8) *  100000UL,
1087	},
1088	{
1089		.src = MSM_BUS_MASTER_SPS,
1090		.dst = MSM_BUS_SLAVE_SPS,
1091		.ib = (492 * 8) * 1000000UL,
1092		.ab = (492 * 8) *  100000UL,
1093	},
1094	{
1095		.src = MSM_BUS_MASTER_SPDM,
1096		.dst = MSM_BUS_SLAVE_SPDM,
1097		.ib = (64 * 8) * 1000000UL,
1098		.ab = (64 * 8) *  100000UL,
1099	},
1100};
1101
1102static struct msm_bus_paths qseecom_hw_bus_scale_usecases[] = {
1103	{
1104		ARRAY_SIZE(qseecom_clks_init_vectors),
1105		qseecom_clks_init_vectors,
1106	},
1107	{
1108		ARRAY_SIZE(qseecom_enable_dfab_vectors),
1109		qseecom_enable_sfpb_vectors,
1110	},
1111	{
1112		ARRAY_SIZE(qseecom_enable_sfpb_vectors),
1113		qseecom_enable_sfpb_vectors,
1114	},
1115	{
1116		ARRAY_SIZE(qseecom_enable_dfab_sfpb_vectors),
1117		qseecom_enable_dfab_sfpb_vectors,
1118	},
1119};
1120
1121static struct msm_bus_scale_pdata qseecom_bus_pdata = {
1122	qseecom_hw_bus_scale_usecases,
1123	ARRAY_SIZE(qseecom_hw_bus_scale_usecases),
1124	.name = "qsee",
1125};
1126
1127static struct platform_device qseecom_device = {
1128	.name		= "qseecom",
1129	.id		= 0,
1130	.dev		= {
1131		.platform_data = &qseecom_bus_pdata,
1132	},
1133};
1134#endif
1135
1136#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
1137		defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE) || \
1138		defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
1139		defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
1140
1141#define QCE_SIZE		0x10000
1142#define QCE_0_BASE		0x18500000
1143
1144#define QCE_HW_KEY_SUPPORT	0
1145#define QCE_SHA_HMAC_SUPPORT	1
1146#define QCE_SHARE_CE_RESOURCE	1
1147#define QCE_CE_SHARED		0
1148
1149/* Begin Bus scaling definitions */
1150static struct msm_bus_vectors crypto_hw_init_vectors[] = {
1151	{
1152		.src = MSM_BUS_MASTER_ADM_PORT0,
1153		.dst = MSM_BUS_SLAVE_EBI_CH0,
1154		.ab = 0,
1155		.ib = 0,
1156	},
1157	{
1158		.src = MSM_BUS_MASTER_ADM_PORT1,
1159		.dst = MSM_BUS_SLAVE_GSBI1_UART,
1160		.ab = 0,
1161		.ib = 0,
1162	},
1163};
1164
1165static struct msm_bus_vectors crypto_hw_active_vectors[] = {
1166	{
1167		.src = MSM_BUS_MASTER_ADM_PORT0,
1168		.dst = MSM_BUS_SLAVE_EBI_CH0,
1169		.ab = 70000000UL,
1170		.ib = 70000000UL,
1171	},
1172	{
1173		.src = MSM_BUS_MASTER_ADM_PORT1,
1174		.dst = MSM_BUS_SLAVE_GSBI1_UART,
1175		.ab = 2480000000UL,
1176		.ib = 2480000000UL,
1177	},
1178};
1179
1180static struct msm_bus_paths crypto_hw_bus_scale_usecases[] = {
1181	{
1182		ARRAY_SIZE(crypto_hw_init_vectors),
1183		crypto_hw_init_vectors,
1184	},
1185	{
1186		ARRAY_SIZE(crypto_hw_active_vectors),
1187		crypto_hw_active_vectors,
1188	},
1189};
1190
1191static struct msm_bus_scale_pdata crypto_hw_bus_scale_pdata = {
1192		crypto_hw_bus_scale_usecases,
1193		ARRAY_SIZE(crypto_hw_bus_scale_usecases),
1194		.name = "cryptohw",
1195};
1196/* End Bus Scaling Definitions*/
1197
1198static struct resource qcrypto_resources[] = {
1199	[0] = {
1200		.start = QCE_0_BASE,
1201		.end = QCE_0_BASE + QCE_SIZE - 1,
1202		.flags = IORESOURCE_MEM,
1203	},
1204	[1] = {
1205		.name = "crypto_channels",
1206		.start = DMOV_CE_IN_CHAN,
1207		.end = DMOV_CE_OUT_CHAN,
1208		.flags = IORESOURCE_DMA,
1209	},
1210	[2] = {
1211		.name = "crypto_crci_in",
1212		.start = DMOV_CE_IN_CRCI,
1213		.end = DMOV_CE_IN_CRCI,
1214		.flags = IORESOURCE_DMA,
1215	},
1216	[3] = {
1217		.name = "crypto_crci_out",
1218		.start = DMOV_CE_OUT_CRCI,
1219		.end = DMOV_CE_OUT_CRCI,
1220		.flags = IORESOURCE_DMA,
1221	},
1222};
1223
1224static struct resource qcedev_resources[] = {
1225	[0] = {
1226		.start = QCE_0_BASE,
1227		.end = QCE_0_BASE + QCE_SIZE - 1,
1228		.flags = IORESOURCE_MEM,
1229	},
1230	[1] = {
1231		.name = "crypto_channels",
1232		.start = DMOV_CE_IN_CHAN,
1233		.end = DMOV_CE_OUT_CHAN,
1234		.flags = IORESOURCE_DMA,
1235	},
1236	[2] = {
1237		.name = "crypto_crci_in",
1238		.start = DMOV_CE_IN_CRCI,
1239		.end = DMOV_CE_IN_CRCI,
1240		.flags = IORESOURCE_DMA,
1241	},
1242	[3] = {
1243		.name = "crypto_crci_out",
1244		.start = DMOV_CE_OUT_CRCI,
1245		.end = DMOV_CE_OUT_CRCI,
1246		.flags = IORESOURCE_DMA,
1247	},
1248};
1249
1250#endif
1251
1252#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
1253		defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE)
1254
1255static struct msm_ce_hw_support qcrypto_ce_hw_suppport = {
1256	.ce_shared = QCE_CE_SHARED,
1257	.shared_ce_resource = QCE_SHARE_CE_RESOURCE,
1258	.hw_key_support = QCE_HW_KEY_SUPPORT,
1259	.sha_hmac = QCE_SHA_HMAC_SUPPORT,
1260	.bus_scale_table = &crypto_hw_bus_scale_pdata,
1261};
1262
1263static struct platform_device qcrypto_device = {
1264	.name		= "qcrypto",
1265	.id		= 0,
1266	.num_resources	= ARRAY_SIZE(qcrypto_resources),
1267	.resource	= qcrypto_resources,
1268	.dev		= {
1269		.coherent_dma_mask = DMA_BIT_MASK(32),
1270		.platform_data = &qcrypto_ce_hw_suppport,
1271	},
1272};
1273#endif
1274
1275#if defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
1276		defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
1277
1278static struct msm_ce_hw_support qcedev_ce_hw_suppport = {
1279	.ce_shared = QCE_CE_SHARED,
1280	.shared_ce_resource = QCE_SHARE_CE_RESOURCE,
1281	.hw_key_support = QCE_HW_KEY_SUPPORT,
1282	.sha_hmac = QCE_SHA_HMAC_SUPPORT,
1283	.bus_scale_table = &crypto_hw_bus_scale_pdata,
1284};
1285
1286static struct platform_device qcedev_device = {
1287	.name		= "qce",
1288	.id		= 0,
1289	.num_resources	= ARRAY_SIZE(qcedev_resources),
1290	.resource	= qcedev_resources,
1291	.dev		= {
1292		.coherent_dma_mask = DMA_BIT_MASK(32),
1293		.platform_data = &qcedev_ce_hw_suppport,
1294	},
1295};
1296#endif
1297
1298#define MDM2AP_ERRFATAL			70
1299#define AP2MDM_ERRFATAL			95
1300#define MDM2AP_STATUS			69
1301#define AP2MDM_STATUS			94
1302#define AP2MDM_PMIC_RESET_N		80
1303#define AP2MDM_KPDPWR_N			81
1304
1305static struct resource mdm_resources[] = {
1306	{
1307		.start	= MDM2AP_ERRFATAL,
1308		.end	= MDM2AP_ERRFATAL,
1309		.name	= "MDM2AP_ERRFATAL",
1310		.flags	= IORESOURCE_IO,
1311	},
1312	{
1313		.start	= AP2MDM_ERRFATAL,
1314		.end	= AP2MDM_ERRFATAL,
1315		.name	= "AP2MDM_ERRFATAL",
1316		.flags	= IORESOURCE_IO,
1317	},
1318	{
1319		.start	= MDM2AP_STATUS,
1320		.end	= MDM2AP_STATUS,
1321		.name	= "MDM2AP_STATUS",
1322		.flags	= IORESOURCE_IO,
1323	},
1324	{
1325		.start	= AP2MDM_STATUS,
1326		.end	= AP2MDM_STATUS,
1327		.name	= "AP2MDM_STATUS",
1328		.flags	= IORESOURCE_IO,
1329	},
1330	{
1331		.start	= AP2MDM_PMIC_RESET_N,
1332		.end	= AP2MDM_PMIC_RESET_N,
1333		.name	= "AP2MDM_PMIC_RESET_N",
1334		.flags	= IORESOURCE_IO,
1335	},
1336	{
1337		.start	= AP2MDM_KPDPWR_N,
1338		.end	= AP2MDM_KPDPWR_N,
1339		.name	= "AP2MDM_KPDPWR_N",
1340		.flags	= IORESOURCE_IO,
1341	},
1342};
1343
1344static struct mdm_platform_data mdm_platform_data = {
1345	.mdm_version = "2.5",
1346};
1347
1348static struct platform_device mdm_device = {
1349	.name		= "mdm2_modem",
1350	.id		= -1,
1351	.num_resources	= ARRAY_SIZE(mdm_resources),
1352	.resource	= mdm_resources,
1353	.dev		= {
1354		.platform_data = &mdm_platform_data,
1355	},
1356};
1357
1358static struct platform_device *mdm_devices[] __initdata = {
1359	&mdm_device,
1360};
1361
1362#ifdef CONFIG_MSM_MPM
1363static uint16_t msm_mpm_irqs_m2a[MSM_MPM_NR_MPM_IRQS] __initdata = {
1364	[1] = MSM_GPIO_TO_INT(46),
1365	[2] = MSM_GPIO_TO_INT(150),
1366	[4] = MSM_GPIO_TO_INT(103),
1367	[5] = MSM_GPIO_TO_INT(104),
1368	[6] = MSM_GPIO_TO_INT(105),
1369	[7] = MSM_GPIO_TO_INT(106),
1370	[8] = MSM_GPIO_TO_INT(107),
1371	[9] = MSM_GPIO_TO_INT(7),
1372	[10] = MSM_GPIO_TO_INT(11),
1373	[11] = MSM_GPIO_TO_INT(15),
1374	[12] = MSM_GPIO_TO_INT(19),
1375	[13] = MSM_GPIO_TO_INT(23),
1376	[14] = MSM_GPIO_TO_INT(27),
1377	[15] = MSM_GPIO_TO_INT(31),
1378	[16] = MSM_GPIO_TO_INT(35),
1379	[19] = MSM_GPIO_TO_INT(90),
1380	[20] = MSM_GPIO_TO_INT(92),
1381	[23] = MSM_GPIO_TO_INT(85),
1382	[24] = MSM_GPIO_TO_INT(83),
1383	[25] = USB1_HS_IRQ,
1384	[26] = MSM_GPIO_TO_INT(6),
1385	[27] = HDMI_IRQ,
1386	[29] = MSM_GPIO_TO_INT(10),
1387	[30] = MSM_GPIO_TO_INT(102),
1388	[31] = MSM_GPIO_TO_INT(81),
1389	[32] = MSM_GPIO_TO_INT(78),
1390	[33] = MSM_GPIO_TO_INT(94),
1391	[34] = MSM_GPIO_TO_INT(72),
1392	[35] = MSM_GPIO_TO_INT(39),
1393	[36] = MSM_GPIO_TO_INT(43),
1394	[37] = MSM_GPIO_TO_INT(61),
1395	[38] = MSM_GPIO_TO_INT(50),
1396	[39] = MSM_GPIO_TO_INT(42),
1397	[41] = MSM_GPIO_TO_INT(62),
1398	[42] = MSM_GPIO_TO_INT(8),
1399	[43] = MSM_GPIO_TO_INT(33),
1400	[44] = MSM_GPIO_TO_INT(70),
1401	[45] = MSM_GPIO_TO_INT(69),
1402	[46] = MSM_GPIO_TO_INT(67),
1403	[47] = MSM_GPIO_TO_INT(65),
1404	[48] = MSM_GPIO_TO_INT(55),
1405	[49] = MSM_GPIO_TO_INT(74),
1406	[50] = MSM_GPIO_TO_INT(98),
1407	[51] = MSM_GPIO_TO_INT(49),
1408	[52] = MSM_GPIO_TO_INT(40),
1409	[53] = MSM_GPIO_TO_INT(37),
1410	[54] = MSM_GPIO_TO_INT(24),
1411	[55] = MSM_GPIO_TO_INT(14),
1412};
1413
1414static uint16_t msm_mpm_bypassed_apps_irqs[] __initdata = {
1415	TLMM_MSM_SUMMARY_IRQ,
1416	RPM_APCC_CPU0_GP_HIGH_IRQ,
1417	RPM_APCC_CPU0_GP_MEDIUM_IRQ,
1418	RPM_APCC_CPU0_GP_LOW_IRQ,
1419	RPM_APCC_CPU0_WAKE_UP_IRQ,
1420	RPM_APCC_CPU1_GP_HIGH_IRQ,
1421	RPM_APCC_CPU1_GP_MEDIUM_IRQ,
1422	RPM_APCC_CPU1_GP_LOW_IRQ,
1423	RPM_APCC_CPU1_WAKE_UP_IRQ,
1424	MSS_TO_APPS_IRQ_0,
1425	MSS_TO_APPS_IRQ_1,
1426	MSS_TO_APPS_IRQ_2,
1427	MSS_TO_APPS_IRQ_3,
1428	MSS_TO_APPS_IRQ_4,
1429	MSS_TO_APPS_IRQ_5,
1430	MSS_TO_APPS_IRQ_6,
1431	MSS_TO_APPS_IRQ_7,
1432	MSS_TO_APPS_IRQ_8,
1433	MSS_TO_APPS_IRQ_9,
1434	LPASS_SCSS_GP_LOW_IRQ,
1435	LPASS_SCSS_GP_MEDIUM_IRQ,
1436	LPASS_SCSS_GP_HIGH_IRQ,
1437	SPS_MTI_30,
1438	SPS_MTI_31,
1439	RIVA_APSS_SPARE_IRQ,
1440	RIVA_APPS_WLAN_SMSM_IRQ,
1441	RIVA_APPS_WLAN_RX_DATA_AVAIL_IRQ,
1442	RIVA_APPS_WLAN_DATA_XFER_DONE_IRQ,
1443};
1444
1445struct msm_mpm_device_data msm8930_mpm_dev_data __initdata = {
1446	.irqs_m2a = msm_mpm_irqs_m2a,
1447	.irqs_m2a_size = ARRAY_SIZE(msm_mpm_irqs_m2a),
1448	.bypassed_apps_irqs = msm_mpm_bypassed_apps_irqs,
1449	.bypassed_apps_irqs_size = ARRAY_SIZE(msm_mpm_bypassed_apps_irqs),
1450	.mpm_request_reg_base = MSM_RPM_BASE + 0x9d8,
1451	.mpm_status_reg_base = MSM_RPM_BASE + 0xdf8,
1452	.mpm_apps_ipc_reg = MSM_APCS_GCC_BASE + 0x008,
1453	.mpm_apps_ipc_val =  BIT(1),
1454	.mpm_ipc_irq = RPM_APCC_CPU0_GP_MEDIUM_IRQ,
1455
1456};
1457#endif
1458
1459#define MSM_SHARED_RAM_PHYS 0x80000000
1460
1461static void __init msm8930_map_io(void)
1462{
1463	msm_shared_ram_phys = MSM_SHARED_RAM_PHYS;
1464	msm_map_msm8930_io();
1465
1466	if (socinfo_init() < 0)
1467		pr_err("socinfo_init() failed!\n");
1468}
1469
1470static void __init msm8930_init_irq(void)
1471{
1472	struct msm_mpm_device_data *data = NULL;
1473#ifdef CONFIG_MSM_MPM
1474	data = &msm8930_mpm_dev_data;
1475#endif
1476
1477	msm_mpm_irq_extn_init(data);
1478	gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
1479						(void *)MSM_QGIC_CPU_BASE);
1480}
1481
1482static void __init msm8930_init_buses(void)
1483{
1484#ifdef CONFIG_MSM_BUS_SCALING
1485	msm_bus_rpm_set_mt_mask();
1486	msm_bus_8930_apps_fabric_pdata.rpm_enabled = 1;
1487	msm_bus_8930_sys_fabric_pdata.rpm_enabled = 1;
1488	msm_bus_8930_mm_fabric_pdata.rpm_enabled = 1;
1489	msm_bus_8930_apps_fabric.dev.platform_data =
1490		&msm_bus_8930_apps_fabric_pdata;
1491	msm_bus_8930_sys_fabric.dev.platform_data =
1492		&msm_bus_8930_sys_fabric_pdata;
1493	msm_bus_8930_mm_fabric.dev.platform_data =
1494		&msm_bus_8930_mm_fabric_pdata;
1495	msm_bus_8930_sys_fpb.dev.platform_data = &msm_bus_8930_sys_fpb_pdata;
1496	msm_bus_8930_cpss_fpb.dev.platform_data = &msm_bus_8930_cpss_fpb_pdata;
1497#endif
1498}
1499
1500static struct msm_spi_platform_data msm8960_qup_spi_gsbi1_pdata = {
1501	.max_clock_speed = 15060000,
1502};
1503
1504#ifdef CONFIG_USB_MSM_OTG_72K
1505static struct msm_otg_platform_data msm_otg_pdata;
1506#else
1507static int enable_usb_host_mode;
1508static int __init usb_host_mode_with_pm8917(char *param)
1509{
1510	int ret;
1511
1512	ret = kstrtoint(param, 10, &enable_usb_host_mode);
1513	return ret;
1514}
1515early_param("usb_host_mode_pm8917", usb_host_mode_with_pm8917);
1516
1517#ifdef CONFIG_MSM_BUS_SCALING
1518/* Bandwidth requests (zero) if no vote placed */
1519static struct msm_bus_vectors usb_init_vectors[] = {
1520	{
1521		.src = MSM_BUS_MASTER_SPS,
1522		.dst = MSM_BUS_SLAVE_EBI_CH0,
1523		.ab = 0,
1524		.ib = 0,
1525	},
1526};
1527
1528/* Bus bandwidth requests in Bytes/sec */
1529static struct msm_bus_vectors usb_max_vectors[] = {
1530	{
1531		.src = MSM_BUS_MASTER_SPS,
1532		.dst = MSM_BUS_SLAVE_EBI_CH0,
1533		.ab = 60000000,		/* At least 480Mbps on bus. */
1534		.ib = 960000000,	/* MAX bursts rate */
1535	},
1536};
1537
1538static struct msm_bus_paths usb_bus_scale_usecases[] = {
1539	{
1540		ARRAY_SIZE(usb_init_vectors),
1541		usb_init_vectors,
1542	},
1543	{
1544		ARRAY_SIZE(usb_max_vectors),
1545		usb_max_vectors,
1546	},
1547};
1548
1549static struct msm_bus_scale_pdata usb_bus_scale_pdata = {
1550	usb_bus_scale_usecases,
1551	ARRAY_SIZE(usb_bus_scale_usecases),
1552	.name = "usb",
1553};
1554#endif
1555
1556static int hsusb_phy_init_seq[] = {
1557	0x44, 0x80, /* set VBUS valid threshold
1558			and disconnect valid threshold */
1559	0x38, 0x81, /* update DC voltage level */
1560	0x24, 0x82, /* set preemphasis and rise/fall time */
1561	0x13, 0x83, /* set source impedance adjusment */
1562	-1};
1563
1564#define MSM_MPM_PIN_USB1_OTGSESSVLD	40
1565
1566static struct msm_otg_platform_data msm_otg_pdata = {
1567	.mode			= USB_OTG,
1568	.otg_control		= OTG_PMIC_CONTROL,
1569	.phy_type		= SNPS_28NM_INTEGRATED_PHY,
1570	.power_budget		= 750,
1571#ifdef CONFIG_MSM_BUS_SCALING
1572	.bus_scale_table	= &usb_bus_scale_pdata,
1573#endif
1574#ifdef CONFIG_FB_MSM_HDMI_MHL_8334
1575	.mhl_dev_name		= "sii8334",
1576#endif
1577	.mpm_otgsessvld_int	= MSM_MPM_PIN_USB1_OTGSESSVLD,
1578};
1579#endif
1580
1581#define PID_MAGIC_ID		0x71432909
1582#define SERIAL_NUM_MAGIC_ID	0x61945374
1583#define SERIAL_NUMBER_LENGTH	127
1584#define DLOAD_USB_BASE_ADD	0x2A03F0C8
1585
1586struct magic_num_struct {
1587	uint32_t pid;
1588	uint32_t serial_num;
1589};
1590
1591struct dload_struct {
1592	uint32_t	reserved1;
1593	uint32_t	reserved2;
1594	uint32_t	reserved3;
1595	uint16_t	reserved4;
1596	uint16_t	pid;
1597	char		serial_number[SERIAL_NUMBER_LENGTH];
1598	uint16_t	reserved5;
1599	struct magic_num_struct magic_struct;
1600};
1601
1602static int usb_diag_update_pid_and_serial_num(uint32_t pid, const char *snum)
1603{
1604	struct dload_struct __iomem *dload = 0;
1605
1606	dload = ioremap(DLOAD_USB_BASE_ADD, sizeof(*dload));
1607	if (!dload) {
1608		pr_err("%s: cannot remap I/O memory region: %08x\n",
1609					__func__, DLOAD_USB_BASE_ADD);
1610		return -ENXIO;
1611	}
1612
1613	pr_debug("%s: dload:%p pid:%x serial_num:%s\n",
1614				__func__, dload, pid, snum);
1615	/* update pid */
1616	dload->magic_struct.pid = PID_MAGIC_ID;
1617	dload->pid = pid;
1618
1619	/* update serial number */
1620	dload->magic_struct.serial_num = 0;
1621	if (!snum) {
1622		memset(dload->serial_number, 0, SERIAL_NUMBER_LENGTH);
1623		goto out;
1624	}
1625
1626	dload->magic_struct.serial_num = SERIAL_NUM_MAGIC_ID;
1627	strlcpy(dload->serial_number, snum, SERIAL_NUMBER_LENGTH);
1628out:
1629	iounmap(dload);
1630	return 0;
1631}
1632
1633static struct android_usb_platform_data android_usb_pdata = {
1634	.update_pid_and_serial_num = usb_diag_update_pid_and_serial_num,
1635};
1636
1637static struct platform_device android_usb_device = {
1638	.name	= "android_usb",
1639	.id	= -1,
1640	.dev	= {
1641		.platform_data = &android_usb_pdata,
1642	},
1643};
1644
1645static uint8_t spm_wfi_cmd_sequence[] __initdata = {
1646	0x03, 0x0f,
1647};
1648
1649static uint8_t spm_retention_cmd_sequence[] __initdata = {
1650	0x00, 0x05, 0x03, 0x0D,
1651	0x0B, 0x00, 0x0f,
1652};
1653
1654static uint8_t spm_power_collapse_without_rpm[] __initdata = {
1655	0x00, 0x24, 0x54, 0x10,
1656	0x09, 0x03, 0x01,
1657	0x10, 0x54, 0x30, 0x0C,
1658	0x24, 0x30, 0x0f,
1659};
1660
1661static uint8_t spm_power_collapse_with_rpm[] __initdata = {
1662	0x00, 0x24, 0x54, 0x10,
1663	0x09, 0x07, 0x01, 0x0B,
1664	0x10, 0x54, 0x30, 0x0C,
1665	0x24, 0x30, 0x0f,
1666};
1667
1668static struct msm_spm_seq_entry msm_spm_boot_cpu_seq_list[] __initdata = {
1669	[0] = {
1670		.mode = MSM_SPM_MODE_CLOCK_GATING,
1671		.notify_rpm = false,
1672		.cmd = spm_wfi_cmd_sequence,
1673	},
1674	[1] = {
1675		.mode = MSM_SPM_MODE_POWER_RETENTION,
1676		.notify_rpm = false,
1677		.cmd = spm_retention_cmd_sequence,
1678	},
1679	[2] = {
1680		.mode = MSM_SPM_MODE_POWER_COLLAPSE,
1681		.notify_rpm = false,
1682		.cmd = spm_power_collapse_without_rpm,
1683	},
1684	[3] = {
1685		.mode = MSM_SPM_MODE_POWER_COLLAPSE,
1686		.notify_rpm = true,
1687		.cmd = spm_power_collapse_with_rpm,
1688	},
1689};
1690
1691static struct msm_spm_seq_entry msm_spm_nonboot_cpu_seq_list[] __initdata = {
1692	[0] = {
1693		.mode = MSM_SPM_MODE_CLOCK_GATING,
1694		.notify_rpm = false,
1695		.cmd = spm_wfi_cmd_sequence,
1696	},
1697	[1] = {
1698		.mode = MSM_SPM_MODE_POWER_COLLAPSE,
1699		.notify_rpm = false,
1700		.cmd = spm_power_collapse_without_rpm,
1701	},
1702	[2] = {
1703		.mode = MSM_SPM_MODE_POWER_COLLAPSE,
1704		.notify_rpm = true,
1705		.cmd = spm_power_collapse_with_rpm,
1706	},
1707};
1708
1709static struct msm_spm_platform_data msm_spm_data[] __initdata = {
1710	[0] = {
1711		.reg_base_addr = MSM_SAW0_BASE,
1712		.reg_init_values[MSM_SPM_REG_SAW2_CFG] = 0x1F,
1713#if defined(CONFIG_MSM_AVS_HW)
1714		.reg_init_values[MSM_SPM_REG_SAW2_AVS_CTL] = 0x00,
1715		.reg_init_values[MSM_SPM_REG_SAW2_AVS_HYSTERESIS] = 0x00,
1716#endif
1717		.reg_init_values[MSM_SPM_REG_SAW2_SPM_CTL] = 0x01,
1718		.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DLY] = 0x03020004,
1719		.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_0] = 0x0084009C,
1720		.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_1] = 0x00A4001C,
1721		.vctl_timeout_us = 50,
1722		.num_modes = ARRAY_SIZE(msm_spm_boot_cpu_seq_list),
1723		.modes = msm_spm_boot_cpu_seq_list,
1724	},
1725	[1] = {
1726		.reg_base_addr = MSM_SAW1_BASE,
1727		.reg_init_values[MSM_SPM_REG_SAW2_CFG] = 0x1F,
1728#if defined(CONFIG_MSM_AVS_HW)
1729		.reg_init_values[MSM_SPM_REG_SAW2_AVS_CTL] = 0x00,
1730		.reg_init_values[MSM_SPM_REG_SAW2_AVS_HYSTERESIS] = 0x00,
1731#endif
1732		.reg_init_values[MSM_SPM_REG_SAW2_SPM_CTL] = 0x01,
1733		.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DLY] = 0x02020204,
1734		.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_0] = 0x0060009C,
1735		.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_1] = 0x0000001C,
1736		.vctl_timeout_us = 50,
1737		.num_modes = ARRAY_SIZE(msm_spm_nonboot_cpu_seq_list),
1738		.modes = msm_spm_nonboot_cpu_seq_list,
1739	},
1740};
1741
1742static uint8_t l2_spm_wfi_cmd_sequence[] __initdata = {
1743	0x00, 0x20, 0x03, 0x20,
1744	0x00, 0x0f,
1745};
1746
1747static uint8_t l2_spm_gdhs_cmd_sequence[] __initdata = {
1748	0x00, 0x20, 0x34, 0x64,
1749	0x48, 0x07, 0x48, 0x20,
1750	0x50, 0x64, 0x04, 0x34,
1751	0x50, 0x0f,
1752};
1753static uint8_t l2_spm_power_off_cmd_sequence[] __initdata = {
1754	0x00, 0x10, 0x34, 0x64,
1755	0x48, 0x07, 0x48, 0x10,
1756	0x50, 0x64, 0x04, 0x34,
1757	0x50, 0x0F,
1758};
1759
1760static struct msm_spm_seq_entry msm_spm_l2_seq_list[] __initdata = {
1761	[0] = {
1762		.mode = MSM_SPM_L2_MODE_RETENTION,
1763		.notify_rpm = false,
1764		.cmd = l2_spm_wfi_cmd_sequence,
1765	},
1766	[1] = {
1767		.mode = MSM_SPM_L2_MODE_GDHS,
1768		.notify_rpm = true,
1769		.cmd = l2_spm_gdhs_cmd_sequence,
1770	},
1771	[2] = {
1772		.mode = MSM_SPM_L2_MODE_POWER_COLLAPSE,
1773		.notify_rpm = true,
1774		.cmd = l2_spm_power_off_cmd_sequence,
1775	},
1776};
1777
1778static struct msm_spm_platform_data msm_spm_l2_data[] __initdata = {
1779	[0] = {
1780		.reg_base_addr = MSM_SAW_L2_BASE,
1781		.reg_init_values[MSM_SPM_REG_SAW2_SPM_CTL] = 0x00,
1782		.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DLY] = 0x02020204,
1783		.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_0] = 0x00A000AE,
1784		.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_1] = 0x00A00020,
1785		.modes = msm_spm_l2_seq_list,
1786		.num_modes = ARRAY_SIZE(msm_spm_l2_seq_list),
1787	},
1788};
1789
1790#define ISA1200_HAP_EN_GPIO	77
1791#define ISA1200_HAP_LEN_GPIO	78
1792#define ISA1200_HAP_CLK_PM8038	PM8038_GPIO_PM_TO_SYS(7)
1793#define ISA1200_HAP_CLK_PM8917	PM8917_GPIO_PM_TO_SYS(38)
1794
1795static int isa1200_power(int on)
1796{
1797	unsigned int gpio = ISA1200_HAP_CLK_PM8038;
1798	enum pm8xxx_aux_clk_id clk_id = CLK_MP3_1;
1799	int rc = 0;
1800
1801	if (socinfo_get_pmic_model() == PMIC_MODEL_PM8917) {
1802		gpio = ISA1200_HAP_CLK_PM8917;
1803		clk_id = CLK_MP3_2;
1804	}
1805
1806	gpio_set_value_cansleep(gpio, !!on);
1807
1808	if (on)
1809		rc = pm8xxx_aux_clk_control(clk_id, XO_DIV_1, true);
1810	else
1811		rc = pm8xxx_aux_clk_control(clk_id, XO_DIV_NONE, true);
1812
1813	if (rc) {
1814		pr_err("%s: unable to write aux clock register(%d)\n",
1815			__func__, rc);
1816	}
1817
1818	return rc;
1819}
1820
1821static int isa1200_dev_setup(bool enable)
1822{
1823	unsigned int gpio = ISA1200_HAP_CLK_PM8038;
1824	int rc = 0;
1825
1826	if (socinfo_get_pmic_model() == PMIC_MODEL_PM8917)
1827		gpio = ISA1200_HAP_CLK_PM8917;
1828
1829	if (!enable)
1830		goto fail_gpio_dir;
1831
1832	rc = gpio_request(gpio, "haptics_clk");
1833	if (rc) {
1834		pr_err("%s: gpio_request for %d gpio failed rc(%d)\n",
1835					__func__, gpio, rc);
1836		goto fail_gpio_req;
1837	}
1838
1839	rc = gpio_direction_output(gpio, 0);
1840	if (rc) {
1841		pr_err("%s: gpio_direction_output failed for %d gpio rc(%d)\n",
1842						__func__, gpio, rc);
1843		goto fail_gpio_dir;
1844	}
1845
1846	return 0;
1847
1848fail_gpio_dir:
1849	gpio_free(gpio);
1850fail_gpio_req:
1851	return rc;
1852
1853}
1854
1855static struct isa1200_regulator isa1200_reg_data[] = {
1856	{
1857		.name = "vddp",
1858		.min_uV = ISA_I2C_VTG_MIN_UV,
1859		.max_uV = ISA_I2C_VTG_MAX_UV,
1860		.load_uA = ISA_I2C_CURR_UA,
1861	},
1862	{
1863		.name = "vcc_i2c",
1864		.min_uV = ISA_I2C_VTG_MIN_UV,
1865		.max_uV = ISA_I2C_VTG_MAX_UV,
1866		.load_uA = ISA_I2C_CURR_UA,
1867	},
1868};
1869
1870static struct isa1200_platform_data isa1200_1_pdata = {
1871	.name = "vibrator",
1872	.dev_setup = isa1200_dev_setup,
1873	.power_on = isa1200_power,
1874	.hap_en_gpio = ISA1200_HAP_EN_GPIO,
1875	.hap_len_gpio = ISA1200_HAP_LEN_GPIO,
1876	.max_timeout = 15000,
1877	.mode_ctrl = PWM_GEN_MODE,
1878	.pwm_fd = {
1879		.pwm_div = 256,
1880	},
1881	.is_erm = false,
1882	.smart_en = true,
1883	.ext_clk_en = true,
1884	.chip_en = 1,
1885	.regulator_info = isa1200_reg_data,
1886	.num_regulators = ARRAY_SIZE(isa1200_reg_data),
1887};
1888
1889static struct i2c_board_info msm_isa1200_board_info[] __initdata = {
1890	{
1891		I2C_BOARD_INFO("isa1200_1", 0x90>>1),
1892		.platform_data = &isa1200_1_pdata,
1893	},
1894};
1895
1896#define MXT_TS_GPIO_IRQ			11
1897#define MXT_TS_RESET_GPIO		52
1898
1899static const u8 mxt_config_data_8930_v1[] = {
1900	/* T6 Object */
1901	 0, 0, 0, 0, 0, 0,
1902	/* T38 Object */
1903	 15, 3, 0, 15, 12, 11, 0, 0,
1904	/* T7 Object */
1905	32, 16, 50,
1906	/* T8 Object */
1907	 30, 0, 5, 1, 0, 0, 8, 8, 0, 0,
1908	/* T9 Object */
1909	 131, 0, 0, 19, 11, 0, 16, 43, 2, 3,
1910	 10, 7, 2, 0, 4, 5, 35, 10, 43, 4,
1911	 54, 2, 15, 32, 38, 38, 143, 40, 143, 80,
1912	 7, 9, 50, 50, 2,
1913	/* T15 Object */
1914	 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1915	 0,
1916	/* T18 Object */
1917	 0, 0,
1918	/* T19 Object */
1919	 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1920	 0, 0, 0, 0, 0, 0,
1921	/* T23 Object */
1922	 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1923	 0, 0, 0, 0, 0,
1924	/* T25 Object */
1925	 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1926	 0, 0, 0, 0,
1927	/* T40 Object */
1928	 0, 0, 0, 0, 0,
1929	/* T42 Object */
1930	 0, 0, 0, 0, 0, 0, 0, 0,
1931	/* T46 Object */
1932	 0, 3, 8, 16, 0, 0, 1, 0, 0,
1933	/* T47 Object */
1934	 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1935	/* T48 Object */
1936	 0, 0, 8, 0, 0, 0, 0, 0, 0, 0,
1937	 0, 0, 0, 0, 0, 0, 0, 100, 4, 64,
1938	 0, 0, 5, 42, 0, 0, 0, 0, 0, 0,
1939	 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1940	 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1941	 0, 0, 0, 0,
1942};
1943
1944static const u8 mxt_config_data_8930_v2[] = {
1945	/* T6 Object */
1946	 0, 0, 0, 0, 0, 0,
1947	/* T38 Object */
1948	 15, 4, 0, 9, 7, 12, 0, 0,
1949	/* T7 Object */
1950	32, 16, 50,
1951	/* T8 Object */
1952	 30, 0, 5, 10, 0, 0, 10, 10, 0, 0,
1953	/* T9 Object */
1954	 131, 0, 0, 19, 11, 0, 16, 50, 1, 3,
1955	 12, 7, 2, 0, 4, 5, 2, 10, 43, 4,
1956	 54, 2, -25, 29, 38, 18, 143, 40, 207, 80,
1957	 17, 5, 50, 50, 0,
1958	/* T18 Object */
1959	 0, 0,
1960	/* T19 Object */
1961	 0, 0, 0, 0, 0, 0,
1962	/* T25 Object */
1963	 0, 0, 0, 0, 0, 0,
1964	/* T42 Object */
1965	 3, 60, 20, 20, 150, 0, 0, 0,
1966	/* T46 Object */
1967	 0, 3, 28, 28, 0, 0, 1, 0, 0,
1968	/* T47 Object */
1969	 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1970	/* T48 Object */
1971	 1, 3, 82, 0, 0, 0, 0, 0, 0, 0,
1972	 16, 30, 0, 6, 6, 0, 0, 124, 4, 100,
1973	 0, 0, 0, 5, 0, 42, 0, 1, 0, 40,
1974	 52, 20, 0, 0, 0, 50, 1, 5, 2, 1,
1975	 4, 5, 3, -25, 29, 38, 18, 143, 40, 207,
1976	 80, 10, 5, 2,
1977	/* T55 Object */
1978	0, 0, 0, 0,
1979};
1980
1981static ssize_t mxt224e_vkeys_show(struct kobject *kobj,
1982			struct kobj_attribute *attr, char *buf)
1983{
1984	return snprintf(buf, 200,
1985	__stringify(EV_KEY) ":" __stringify(KEY_BACK) ":57:1030:90:90"
1986	":" __stringify(EV_KEY) ":" __stringify(KEY_MENU) ":206:1030:90:90"
1987	":" __stringify(EV_KEY) ":" __stringify(KEY_HOME) ":366:1030:90:90"
1988	":" __stringify(EV_KEY) ":" __stringify(KEY_SEARCH) ":503:1030:90:90"
1989	"\n");
1990}
1991
1992static struct kobj_attribute mxt224e_vkeys_attr = {
1993	.attr = {
1994		.mode = S_IRUGO,
1995	},
1996	.show = &mxt224e_vkeys_show,
1997};
1998
1999static struct attribute *mxt224e_properties_attrs[] = {
2000	&mxt224e_vkeys_attr.attr,
2001	NULL
2002};
2003
2004static struct attribute_group mxt224e_properties_attr_group = {
2005	.attrs = mxt224e_properties_attrs,
2006};
2007
2008static void mxt_init_vkeys_8930(void)
2009{
2010	int rc = 0;
2011	st

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