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/arch/arm/mach-pxa/clock.c

https://github.com/AICP/kernel_asus_grouper
C | 86 lines | 64 code | 19 blank | 3 comment | 8 complexity | a31c4b00705108b1cdc18ec86666e21b MD5 | raw file
 1/*
 2 *  linux/arch/arm/mach-sa1100/clock.c
 3 */
 4#include <linux/module.h>
 5#include <linux/kernel.h>
 6#include <linux/clk.h>
 7#include <linux/spinlock.h>
 8#include <linux/delay.h>
 9#include <linux/clkdev.h>
10
11#include "clock.h"
12
13static DEFINE_SPINLOCK(clocks_lock);
14
15int clk_enable(struct clk *clk)
16{
17	unsigned long flags;
18
19	spin_lock_irqsave(&clocks_lock, flags);
20	if (clk->enabled++ == 0)
21		clk->ops->enable(clk);
22	spin_unlock_irqrestore(&clocks_lock, flags);
23
24	if (clk->delay)
25		udelay(clk->delay);
26
27	return 0;
28}
29EXPORT_SYMBOL(clk_enable);
30
31void clk_disable(struct clk *clk)
32{
33	unsigned long flags;
34
35	WARN_ON(clk->enabled == 0);
36
37	spin_lock_irqsave(&clocks_lock, flags);
38	if (--clk->enabled == 0)
39		clk->ops->disable(clk);
40	spin_unlock_irqrestore(&clocks_lock, flags);
41}
42EXPORT_SYMBOL(clk_disable);
43
44unsigned long clk_get_rate(struct clk *clk)
45{
46	unsigned long rate;
47
48	rate = clk->rate;
49	if (clk->ops->getrate)
50		rate = clk->ops->getrate(clk);
51
52	return rate;
53}
54EXPORT_SYMBOL(clk_get_rate);
55
56int clk_set_rate(struct clk *clk, unsigned long rate)
57{
58	unsigned long flags;
59	int ret = -EINVAL;
60
61	if (clk->ops->setrate) {
62		spin_lock_irqsave(&clocks_lock, flags);
63		ret = clk->ops->setrate(clk, rate);
64		spin_unlock_irqrestore(&clocks_lock, flags);
65	}
66
67	return ret;
68}
69EXPORT_SYMBOL(clk_set_rate);
70
71void clk_dummy_enable(struct clk *clk)
72{
73}
74
75void clk_dummy_disable(struct clk *clk)
76{
77}
78
79const struct clkops clk_dummy_ops = {
80	.enable		= clk_dummy_enable,
81	.disable	= clk_dummy_disable,
82};
83
84struct clk clk_dummy = {
85	.ops		= &clk_dummy_ops,
86};