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/include/linux/mfd/pm8xxx/misc.h

https://github.com/airy09/android_kernel_sony_apq8064
C Header | 350 lines | 169 code | 36 blank | 145 comment | 1 complexity | a1c7f94066199230cad28b8bf2e09cf2 MD5 | raw file
  1/*
  2 * Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
  3 * Copyright (C) 2012 Sony Mobile Communications AB.
  4 *
  5 * This program is free software; you can redistribute it and/or modify
  6 * it under the terms of the GNU General Public License version 2 and
  7 * only version 2 as published by the Free Software Foundation.
  8 *
  9 * This program is distributed in the hope that it will be useful,
 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 12 * GNU General Public License for more details.
 13 */
 14
 15#ifndef __MFD_PM8XXX_MISC_H__
 16#define __MFD_PM8XXX_MISC_H__
 17
 18#include <linux/err.h>
 19
 20#define PM8XXX_MISC_DEV_NAME	"pm8xxx-misc"
 21
 22/**
 23 * struct pm8xxx_misc_platform_data - PM8xxx misc driver platform data
 24 * @priority:	PMIC prority level in a multi-PMIC system. Lower value means
 25 *		greater priority. Actions are performed from highest to lowest
 26 *		priority PMIC.
 27 */
 28struct pm8xxx_misc_platform_data {
 29	int	priority;
 30};
 31
 32enum pm8xxx_uart_path_sel {
 33	UART_NONE,
 34	UART_TX1_RX1,
 35	UART_TX2_RX2,
 36	UART_TX3_RX3,
 37};
 38
 39enum pm8xxx_coincell_chg_voltage {
 40	PM8XXX_COINCELL_VOLTAGE_3p2V = 1,
 41	PM8XXX_COINCELL_VOLTAGE_3p1V,
 42	PM8XXX_COINCELL_VOLTAGE_3p0V,
 43	PM8XXX_COINCELL_VOLTAGE_2p5V = 16
 44};
 45
 46enum pm8xxx_coincell_chg_resistor {
 47	PM8XXX_COINCELL_RESISTOR_2100_OHMS,
 48	PM8XXX_COINCELL_RESISTOR_1700_OHMS,
 49	PM8XXX_COINCELL_RESISTOR_1200_OHMS,
 50	PM8XXX_COINCELL_RESISTOR_800_OHMS
 51};
 52
 53enum pm8xxx_coincell_chg_state {
 54	PM8XXX_COINCELL_CHG_DISABLE,
 55	PM8XXX_COINCELL_CHG_ENABLE
 56};
 57
 58struct pm8xxx_coincell_chg {
 59	enum pm8xxx_coincell_chg_state		state;
 60	enum pm8xxx_coincell_chg_voltage	voltage;
 61	enum pm8xxx_coincell_chg_resistor	resistor;
 62};
 63
 64enum pm8xxx_smpl_delay {
 65	PM8XXX_SMPL_DELAY_0p5,
 66	PM8XXX_SMPL_DELAY_1p0,
 67	PM8XXX_SMPL_DELAY_1p5,
 68	PM8XXX_SMPL_DELAY_2p0,
 69};
 70
 71enum pm8xxx_pon_config {
 72	PM8XXX_DISABLE_HARD_RESET = 0,
 73	PM8XXX_SHUTDOWN_ON_HARD_RESET,
 74	PM8XXX_RESTART_ON_HARD_RESET,
 75};
 76
 77enum pm8xxx_pon_delay_config {
 78	PM8XXX_HARD_RESET_DELAY_MS_MIN = 0,
 79	PM8XXX_HARD_RESET_DELAY_MS_0 = PM8XXX_HARD_RESET_DELAY_MS_MIN,
 80	PM8XXX_HARD_RESET_DELAY_MS_10,
 81	PM8XXX_HARD_RESET_DELAY_MS_50,
 82	PM8XXX_HARD_RESET_DELAY_MS_100,
 83	PM8XXX_HARD_RESET_DELAY_MS_250,
 84	PM8XXX_HARD_RESET_DELAY_MS_500,
 85	PM8XXX_HARD_RESET_DELAY_MS_1000,
 86	PM8XXX_HARD_RESET_DELAY_MS_2000,
 87	PM8XXX_HARD_RESET_DELAY_MS_MAX,
 88};
 89
 90enum pm8xxx_pon_debounce_config {
 91	PM8XXX_HARD_RESET_DEBOUNCE_MS_MIN = 0,
 92	PM8XXX_HARD_RESET_DEBOUNCE_MS_0 = PM8XXX_HARD_RESET_DEBOUNCE_MS_MIN,
 93	PM8XXX_HARD_RESET_DEBOUNCE_MS_32,
 94	PM8XXX_HARD_RESET_DEBOUNCE_MS_56,
 95	PM8XXX_HARD_RESET_DEBOUNCE_MS_80,
 96	PM8XXX_HARD_RESET_DEBOUNCE_MS_128,
 97	PM8XXX_HARD_RESET_DEBOUNCE_MS_184,
 98	PM8XXX_HARD_RESET_DEBOUNCE_MS_272,
 99	PM8XXX_HARD_RESET_DEBOUNCE_MS_408,
100	PM8XXX_HARD_RESET_DEBOUNCE_MS_608,
101	PM8XXX_HARD_RESET_DEBOUNCE_MS_904,
102	PM8XXX_HARD_RESET_DEBOUNCE_MS_1352,
103	PM8XXX_HARD_RESET_DEBOUNCE_MS_2048,
104	PM8XXX_HARD_RESET_DEBOUNCE_MS_3072,
105	PM8XXX_HARD_RESET_DEBOUNCE_MS_4480,
106	PM8XXX_HARD_RESET_DEBOUNCE_MS_6720,
107	PM8XXX_HARD_RESET_DEBOUNCE_MS_10256,
108	PM8XXX_HARD_RESET_DEBOUNCE_MS_MAX,
109};
110
111enum pm8xxx_aux_clk_id {
112	CLK_MP3_1,
113	CLK_MP3_2,
114};
115
116enum pm8xxx_aux_clk_div {
117	XO_DIV_NONE,
118	XO_DIV_1,
119	XO_DIV_2,
120	XO_DIV_4,
121	XO_DIV_8,
122	XO_DIV_16,
123	XO_DIV_32,
124	XO_DIV_64,
125};
126
127enum pm8xxx_hsed_bias {
128	PM8XXX_HSED_BIAS0,
129	PM8XXX_HSED_BIAS1,
130	PM8XXX_HSED_BIAS2,
131};
132
133#if defined(CONFIG_MFD_PM8XXX_MISC) || defined(CONFIG_MFD_PM8XXX_MISC_MODULE)
134
135/**
136 * pm8xxx_reset_pwr_off - switch all PM8XXX PMIC chips attached to the system to
137 *			  either reset or shutdown when they are turned off
138 * @reset: 0 = shudown the PMICs, 1 = shutdown and then restart the PMICs
139 *
140 * RETURNS: an appropriate -ERRNO error value on error, or zero for success.
141 */
142int pm8xxx_reset_pwr_off(int reset);
143
144int pm8xxx_uart_gpio_mux_ctrl(enum pm8xxx_uart_path_sel uart_path_sel);
145
146/**
147 * pm8xxx_coincell_chg_config - Disables or enables the coincell charger, and
148 *				configures its voltage and resistor settings.
149 * @chg_config:			Holds both voltage and resistor values, and a
150 *				switch to change the state of charger.
151 *				If state is to disable the charger then
152 *				both voltage and resistor are disregarded.
153 *
154 * RETURNS: an appropriate -ERRNO error value on error, or zero for success.
155 */
156int pm8xxx_coincell_chg_config(struct pm8xxx_coincell_chg *chg_config);
157
158/**
159 * pm8xxx_smpl_control - enables/disables SMPL detection
160 * @enable: 0 = shutdown PMIC on power loss, 1 = reset PMIC on power loss
161 *
162 * This function enables or disables the Sudden Momentary Power Loss detection
163 * module.  If SMPL detection is enabled, then when a sufficiently long power
164 * loss event occurs, the PMIC will automatically reset itself.  If SMPL
165 * detection is disabled, then the PMIC will shutdown when power loss occurs.
166 *
167 * RETURNS: an appropriate -ERRNO error value on error, or zero for success.
168 */
169int pm8xxx_smpl_control(int enable);
170
171/**
172 * pm8xxx_smpl_set_delay - sets the SMPL detection time delay
173 * @delay: enum value corresponding to delay time
174 *
175 * This function sets the time delay of the SMPL detection module.  If power
176 * is reapplied within this interval, then the PMIC reset automatically.  The
177 * SMPL detection module must be enabled for this delay time to take effect.
178 *
179 * RETURNS: an appropriate -ERRNO error value on error, or zero for success.
180 */
181int pm8xxx_smpl_set_delay(enum pm8xxx_smpl_delay delay);
182
183/**
184 * pm8xxx_watchdog_reset_control - enables/disables watchdog reset detection
185 * @enable: 0 = shutdown when PS_HOLD goes low, 1 = reset when PS_HOLD goes low
186 *
187 * This function enables or disables the PMIC watchdog reset detection feature.
188 * If watchdog reset detection is enabled, then the PMIC will reset itself
189 * when PS_HOLD goes low.  If it is not enabled, then the PMIC will shutdown
190 * when PS_HOLD goes low.
191 *
192 * RETURNS: an appropriate -ERRNO error value on error, or zero for success.
193 */
194int pm8xxx_watchdog_reset_control(int enable);
195
196/**
197 * pm8xxx_hard_reset_config - Allows different reset configurations
198 *
199 * config = DISABLE_HARD_RESET to disable hard reset
200 *	  = SHUTDOWN_ON_HARD_RESET to turn off the system on hard reset
201 *	  = RESTART_ON_HARD_RESET to restart the system on hard reset
202 *
203 * RETURNS: an appropriate -ERRNO error value on error, or zero for success.
204 */
205int pm8xxx_hard_reset_config(enum pm8xxx_pon_config config);
206
207/**
208 * pm8xxx_hard_reset_delay_config - Set hard reset delay time
209 *
210 * Available delay time values are as follows:
211 *   0, 10, 50, 100, 250, 500, 1000, 2000
212 *
213 * RETURNS: an appropriate -ERRNO error value on error, or zero for success.
214 */
215int pm8xxx_hard_reset_delay_config(enum pm8xxx_pon_delay_config config);
216
217/**
218 * pm8xxx_hard_reset_debounce_config - Set hard reset debounce time
219 *
220 *  Available debounce time values are as follows:
221 *   0, 32, 56, 80, 128, 184, 272, 408, 608, 904, 1352, 2048, 3072,
222 *   4480, 6720, 10256
223 *
224 * RETURNS: an appropriate -ERRNO error value on error, or zero for success.
225 */
226int pm8xxx_hard_reset_debounce_config(enum pm8xxx_pon_debounce_config config);
227
228/**
229 * pm8xxx_stay_on - enables stay_on feature
230 *
231 * PMIC stay-on feature allows PMIC to ignore MSM PS_HOLD=low
232 * signal so that some special functions like debugging could be
233 * performed.
234 *
235 * This feature should not be used in any product release.
236 *
237 * RETURNS: an appropriate -ERRNO error value on error, or zero for success.
238 */
239int pm8xxx_stay_on(void);
240
241/**
242 * pm8xxx_preload_dVdd - preload the dVdd regulator during off state.
243 *
244 * This can help to reduce fluctuations in the dVdd voltage during startup
245 * at the cost of additional off state current draw.
246 *
247 * This API should only be called if dVdd startup issues are suspected.
248 *
249 * RETURNS: an appropriate -ERRNO error value on error, or zero for success.
250 */
251int pm8xxx_preload_dVdd(void);
252
253/**
254 * pm8xxx_usb_id_pullup - Control a pullup for USB ID
255 *
256 * @enable: enable (1) or disable (0) the pullup
257 *
258 * RETURNS: an appropriate -ERRNO error value on error, or zero for success.
259 */
260int pm8xxx_usb_id_pullup(int enable);
261
262/**
263 * pm8xxx_aux_clk_control - Control an auxiliary clock
264 * @clk_id: ID of clock to be programmed, registers of XO_CNTRL2
265 * @divider: divisor to use when configuring desired clock
266 * @enable: enable (1) the designated clock with the supplied division,
267 *		or disable (0) the designated clock
268 *
269 * RETURNS: an appropriate -ERRNO error value on error, or zero for success.
270 */
271int pm8xxx_aux_clk_control(enum pm8xxx_aux_clk_id clk_id,
272				enum pm8xxx_aux_clk_div divider,
273				bool enable);
274
275/**
276 * pm8xxx_hsed_bias_control - Control the HSED_BIAS signal
277 * @bias: the bias line to be controlled (of the 3)
278 * @enable: enable/disable the bias line
279 *
280 * RETURNS: an appropriate -ERRNO error value on error, or zero for success.
281 */
282int pm8xxx_hsed_bias_control(enum pm8xxx_hsed_bias bias, bool enable);
283
284/**
285 * pm8xxx_read_register - Read a PMIC register
286 * @addr: PMIC register address
287 * @value: Output parameter which gets the value of the register read.
288 *
289 * RETURNS: an appropriate -ERRNO error value on error, or zero for success.
290 */
291int pm8xxx_read_register(u16 addr, u8 *value);
292
293#else
294
295static inline int pm8xxx_reset_pwr_off(int reset)
296{
297	return -ENODEV;
298}
299static inline int
300pm8xxx_uart_gpio_mux_ctrl(enum pm8xxx_uart_path_sel uart_path_sel)
301{
302	return -ENODEV;
303}
304static inline int
305pm8xxx_coincell_chg_config(struct pm8xxx_coincell_chg *chg_config)
306{
307	return -ENODEV;
308}
309static inline int pm8xxx_smpl_set_delay(enum pm8xxx_smpl_delay delay)
310{
311	return -ENODEV;
312}
313static inline int pm8xxx_smpl_control(int enable)
314{
315	return -ENODEV;
316}
317static inline int pm8xxx_watchdog_reset_control(int enable)
318{
319	return -ENODEV;
320}
321static inline int pm8xxx_hard_reset_config(enum pm8xxx_pon_config config)
322{
323	return -ENODEV;
324}
325static inline int pm8xxx_stay_on(void)
326{
327	return -ENODEV;
328}
329static inline int pm8xxx_preload_dVdd(void)
330{
331	return -ENODEV;
332}
333static inline int pm8xxx_usb_id_pullup(int enable)
334{
335	return -ENODEV;
336}
337static inline int pm8xxx_aux_clk_control(enum pm8xxx_aux_clk_id clk_id,
338			enum pm8xxx_aux_clk_div divider, bool enable)
339{
340	return -ENODEV;
341}
342static inline int pm8xxx_hsed_bias_control(enum pm8xxx_hsed_bias bias,
343							bool enable)
344{
345	return -ENODEV;
346}
347
348#endif
349
350#endif