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/arch/arm/mach-msm/board-9625.c

https://github.com/AICP/kernel_google_msm
C | 115 lines | 91 code | 13 blank | 11 comment | 1 complexity | d1c4b7d1a2de14e53de83e67e8ac2275 MD5 | raw file
  1/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
  2 *
  3 * This program is free software; you can redistribute it and/or modify
  4 * it under the terms of the GNU General Public License version 2 and
  5 * only version 2 as published by the Free Software Foundation.
  6 *
  7 * This program is distributed in the hope that it will be useful,
  8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 10 * GNU General Public License for more details.
 11 */
 12
 13#include <linux/kernel.h>
 14#include <linux/platform_device.h>
 15#include <linux/io.h>
 16#include <linux/irq.h>
 17#include <linux/irqdomain.h>
 18#include <linux/of.h>
 19#include <linux/of_address.h>
 20#include <linux/of_platform.h>
 21#include <linux/of_irq.h>
 22#include <linux/memory.h>
 23#include <asm/mach/map.h>
 24#include <asm/hardware/cache-l2x0.h>
 25#include <asm/hardware/gic.h>
 26#include <asm/arch_timer.h>
 27#include <asm/mach/arch.h>
 28#include <asm/mach/time.h>
 29#include <mach/socinfo.h>
 30#include <mach/board.h>
 31#include <mach/gpio.h>
 32#include <mach/clk-provider.h>
 33#include "clock.h"
 34
 35#define L2CC_AUX_CTRL	((0x1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) | \
 36			(0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) | \
 37			(0x1 << L2X0_AUX_CTRL_EVNT_MON_BUS_EN_SHIFT))
 38
 39static struct clk_lookup msm_clocks_dummy[] = {
 40	CLK_DUMMY("core_clk",   BLSP1_UART_CLK, "msm_serial_hsl.0", OFF),
 41	CLK_DUMMY("iface_clk",  BLSP1_UART_CLK, "msm_serial_hsl.0", OFF),
 42	CLK_DUMMY("phy_clk", NULL, "msm_otg", OFF),
 43	CLK_DUMMY("core_clk", NULL, "msm_otg", OFF),
 44	CLK_DUMMY("alt_core_clk", NULL, "msm_otg", OFF),
 45	CLK_DUMMY("iface_clk", NULL, "msm_otg", OFF),
 46	CLK_DUMMY("xo", NULL, "msm_otg", OFF),
 47	CLK_DUMMY("dfab_clk",	DFAB_CLK,	NULL, 0),
 48	CLK_DUMMY("dma_bam_pclk",	DMA_BAM_P_CLK,	NULL, 0),
 49	CLK_DUMMY("mem_clk",	NULL,	NULL, 0),
 50	CLK_DUMMY("core_clk",	SPI_CLK,	"spi_qsd.1",	OFF),
 51	CLK_DUMMY("iface_clk",	SPI_P_CLK,	"spi_qsd.1",	OFF),
 52	CLK_DUMMY("core_clk",	NULL,	"f9966000.i2c", 0),
 53	CLK_DUMMY("iface_clk",	NULL,	"f9966000.i2c", 0),
 54	CLK_DUMMY("core_clk",	NULL,	"fe12f000.slim",	OFF),
 55};
 56
 57struct clock_init_data msm_dummy_clock_init_data __initdata = {
 58	.table = msm_clocks_dummy,
 59	.size = ARRAY_SIZE(msm_clocks_dummy),
 60};
 61
 62static struct of_device_id irq_match[] __initdata  = {
 63	{ .compatible = "qcom,msm-qgic2", .data = gic_of_init, },
 64	{ .compatible = "qcom,msm-gpio", .data = msm_gpio_of_init, },
 65	{}
 66};
 67
 68static const char *msm9625_dt_match[] __initconst = {
 69	"qcom,msm9625",
 70	NULL
 71};
 72
 73static struct of_dev_auxdata msm9625_auxdata_lookup[] __initdata = {
 74	OF_DEV_AUXDATA("qcom,msm-lsuart-v14", 0xF991F000, \
 75			"msm_serial_hsl.0", NULL),
 76	OF_DEV_AUXDATA("qcom,spi-qup-v2", 0xF9928000, \
 77			"spi_qsd.1", NULL),
 78	{}
 79};
 80
 81void __init msm9625_init_irq(void)
 82{
 83	l2x0_of_init(L2CC_AUX_CTRL, L2X0_AUX_CTRL_MASK);
 84	of_irq_init(irq_match);
 85}
 86
 87static void __init msm_dt_timer_init(void)
 88{
 89	arch_timer_of_register();
 90}
 91
 92static struct sys_timer msm_dt_timer = {
 93	.init = msm_dt_timer_init
 94};
 95
 96void __init msm9625_init(void)
 97{
 98	if (socinfo_init() < 0)
 99		pr_err("%s: socinfo_init() failed\n", __func__);
100
101	msm9625_init_gpiomux();
102	msm_clock_init(&msm_dummy_clock_init_data);
103	of_platform_populate(NULL, of_default_bus_match_table,
104			msm9625_auxdata_lookup, NULL);
105}
106
107DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)")
108	.map_io = msm_map_msm9625_io,
109	.init_irq = msm9625_init_irq,
110	.init_machine = msm9625_init,
111	.handle_irq = gic_handle_irq,
112	.timer = &msm_dt_timer,
113	.dt_compat = msm9625_dt_match,
114	.nr_irqs = -1,
115MACHINE_END