/arch/arm/mach-msm/board-fsm9xxx.c
C | 995 lines | 833 code | 112 blank | 50 comment | 18 complexity | f2cb220875565f42d2f49ae4508a8026 MD5 | raw file
1/* Copyright (c) 2010-2012, The Linux Foundation. All rights reserved. 2 * 3 * This program is free software; you can redistribute it and/or modify 4 * it under the terms of the GNU General Public License version 2 and 5 * only version 2 as published by the Free Software Foundation. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 * 12 */ 13#include <linux/kernel.h> 14#include <linux/irq.h> 15#include <linux/gpio.h> 16#include <linux/platform_device.h> 17#include <linux/delay.h> 18#include <linux/io.h> 19#include <linux/msm_ssbi.h> 20#include <linux/mfd/pmic8058.h> 21#include <linux/regulator/pmic8058-regulator.h> 22#include <linux/i2c.h> 23#include <linux/dma-mapping.h> 24#include <linux/dmapool.h> 25#include <linux/regulator/pm8058-xo.h> 26 27#include <asm/mach-types.h> 28#include <asm/mach/arch.h> 29#include <asm/setup.h> 30 31#include <mach/board.h> 32#include <mach/memory.h> 33#include <mach/msm_iomap.h> 34#include <mach/dma.h> 35#include <mach/sirc.h> 36#include <mach/restart.h> 37 38#include <mach/socinfo.h> 39#include "devices.h" 40#include "timer.h" 41#include "clock.h" 42#include "pm.h" 43#include "spm.h" 44#include <linux/regulator/consumer.h> 45#include <linux/regulator/machine.h> 46#include <linux/msm_adc.h> 47#include <linux/m_adcproc.h> 48#include <linux/platform_data/qcom_crypto_device.h> 49 50#define PMIC_GPIO_INT 144 51#define PMIC_VREG_WLAN_LEVEL 2900 52#define PMIC_GPIO_SD_DET 165 53 54#define GPIO_EPHY_RST_N 37 55#define GPIO_MAC_TXD_3 119 56#define GPIO_MAC_TXD_2 120 57#define GPIO_MAC_TXD_1 121 58#define GPIO_MAC_TXD_0 122 59#define GPIO_MAC_TX_EN 123 60#define GPIO_MAC_MDIO 127 61#define GPIO_MAC_MDC 128 62#define GPIO_MAC_TX_CLK 133 63#define GPIO_GRFC_FTR0_0 136 /* GRFC 20 */ 64#define GPIO_GRFC_FTR0_1 137 /* GRFC 21 */ 65#define GPIO_GRFC_FTR1_0 145 /* GRFC 22 */ 66#define GPIO_GRFC_FTR1_1 93 /* GRFC 19 */ 67#define GPIO_GRFC_2 110 68#define GPIO_GRFC_3 109 69#define GPIO_GRFC_4 108 70#define GPIO_GRFC_5 107 71#define GPIO_GRFC_6 106 72#define GPIO_GRFC_7 105 73#define GPIO_GRFC_8 104 74#define GPIO_GRFC_9 103 75#define GPIO_GRFC_10 102 76#define GPIO_GRFC_11 101 77#define GPIO_GRFC_13 99 78#define GPIO_GRFC_14 98 79#define GPIO_GRFC_15 97 80#define GPIO_GRFC_16 96 81#define GPIO_GRFC_17 95 82#define GPIO_GRFC_18 94 83#define GPIO_GRFC_24 150 84#define GPIO_GRFC_25 151 85#define GPIO_GRFC_26 152 86#define GPIO_GRFC_27 153 87#define GPIO_GRFC_28 154 88#define GPIO_GRFC_29 155 89 90#define GPIO_USER_FIRST 58 91#define GPIO_USER_LAST 63 92 93#define GPIO_UIM_RESET 75 94#define GPIO_UIM_DATA_IO 76 95#define GPIO_UIM_CLOCK 77 96 97#define GPIO_PM_UIM_M_RST 26 /* UIM_RST input */ 98#define GPIO_PM_UIM_RST 27 /* UIM_RST output */ 99#define GPIO_PM_UIM_M_CLK 28 /* UIM_CLK input */ 100#define GPIO_PM_UIM_CLK 29 /* UIM_CLK output */ 101 102#define FPGA_SDCC_STATUS 0x8E0001A8 103 104/* Macros assume PMIC GPIOs start at 0 */ 105#define PM8058_GPIO_PM_TO_SYS(pm_gpio) (pm_gpio + NR_MSM_GPIOS) 106#define PM8058_GPIO_SYS_TO_PM(sys_gpio) (sys_gpio - NR_MSM_GPIOS) 107#define PM8058_MPP_BASE (NR_MSM_GPIOS + PM8058_GPIOS) 108#define PM8058_MPP_PM_TO_SYS(pm_gpio) (pm_gpio + PM8058_MPP_BASE) 109#define PM8058_MPP_SYS_TO_PM(sys_gpio) (sys_gpio - PM8058_MPP_BASE) 110 111#define PMIC_GPIO_5V_PA_PWR 21 /* PMIC GPIO Number 22 */ 112#define PMIC_GPIO_4_2V_PA_PWR 22 /* PMIC GPIO Number 23 */ 113#define PMIC_MPP_UIM_M_DATA 0 /* UIM_DATA input */ 114#define PMIC_MPP_UIM_DATA 1 /* UIM_DATA output */ 115#define PMIC_MPP_3 2 /* PMIC MPP Number 3 */ 116#define PMIC_MPP_6 5 /* PMIC MPP Number 6 */ 117#define PMIC_MPP_7 6 /* PMIC MPP Number 7 */ 118#define PMIC_MPP_10 9 /* PMIC MPP Number 10 */ 119 120/* 121 * PM8058 122 */ 123struct pm8xxx_mpp_init_info { 124 unsigned mpp; 125 struct pm8xxx_mpp_config_data config; 126}; 127 128#define PM8XXX_MPP_INIT(_mpp, _type, _level, _control) \ 129{ \ 130 .mpp = PM8058_MPP_PM_TO_SYS(_mpp), \ 131 .config = { \ 132 .type = PM8XXX_MPP_TYPE_##_type, \ 133 .level = _level, \ 134 .control = PM8XXX_MPP_##_control, \ 135 } \ 136} 137 138static int pm8058_gpios_init(void) 139{ 140 int i; 141 int rc; 142 struct pm8058_gpio_cfg { 143 int gpio; 144 struct pm_gpio cfg; 145 }; 146 147 struct pm8058_gpio_cfg gpio_cfgs[] = { 148 { /* 5V PA Power */ 149 PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_5V_PA_PWR), 150 { 151 .vin_sel = 0, 152 .direction = PM_GPIO_DIR_BOTH, 153 .output_value = 1, 154 .output_buffer = PM_GPIO_OUT_BUF_CMOS, 155 .pull = PM_GPIO_PULL_DN, 156 .out_strength = PM_GPIO_STRENGTH_HIGH, 157 .function = PM_GPIO_FUNC_NORMAL, 158 .inv_int_pol = 0, 159 }, 160 }, 161 { /* 4.2V PA Power */ 162 PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_4_2V_PA_PWR), 163 { 164 .vin_sel = 0, 165 .direction = PM_GPIO_DIR_BOTH, 166 .output_value = 1, 167 .output_buffer = PM_GPIO_OUT_BUF_CMOS, 168 .pull = PM_GPIO_PULL_DN, 169 .out_strength = PM_GPIO_STRENGTH_HIGH, 170 .function = PM_GPIO_FUNC_NORMAL, 171 .inv_int_pol = 0, 172 }, 173 }, 174 }; 175 176 for (i = 0; i < ARRAY_SIZE(gpio_cfgs); ++i) { 177 rc = pm8xxx_gpio_config(gpio_cfgs[i].gpio, &gpio_cfgs[i].cfg); 178 if (rc < 0) { 179 pr_err("%s pmic gpio config failed\n", __func__); 180 return rc; 181 } 182 } 183 184 return 0; 185} 186 187static int pm8058_mpps_init(void) 188{ 189 int rc, i; 190 191 struct pm8xxx_mpp_init_info pm8058_mpps[] = { 192 PM8XXX_MPP_INIT(PMIC_MPP_3, A_OUTPUT, 193 PM8XXX_MPP_AOUT_LVL_1V25_2, AOUT_CTRL_ENABLE), 194 PM8XXX_MPP_INIT(PMIC_MPP_6, A_OUTPUT, 195 PM8XXX_MPP_AOUT_LVL_1V25_2, AOUT_CTRL_ENABLE), 196 PM8XXX_MPP_INIT(PMIC_MPP_UIM_M_DATA, D_BI_DIR, 197 PM8058_MPP_DIG_LEVEL_S3, BI_PULLUP_1KOHM), 198 PM8XXX_MPP_INIT(PMIC_MPP_UIM_DATA, D_BI_DIR, 199 PM8058_MPP_DIG_LEVEL_L3, BI_PULLUP_30KOHM), 200 }; 201 202 for (i = 0; i < ARRAY_SIZE(pm8058_mpps); i++) { 203 rc = pm8xxx_mpp_config(pm8058_mpps[i].mpp, 204 &pm8058_mpps[i].config); 205 if (rc) { 206 pr_err("%s: Config %d mpp pm 8058 failed\n", 207 __func__, pm8058_mpps[i].mpp); 208 return rc; 209 } 210 } 211 212 return 0; 213} 214 215static struct regulator_consumer_supply pm8058_vreg_supply[PM8058_VREG_MAX] = { 216 [PM8058_VREG_ID_L3] = REGULATOR_SUPPLY("8058_l3", NULL), 217 [PM8058_VREG_ID_L8] = REGULATOR_SUPPLY("8058_l8", NULL), 218 [PM8058_VREG_ID_L9] = REGULATOR_SUPPLY("8058_l9", NULL), 219 [PM8058_VREG_ID_L14] = REGULATOR_SUPPLY("8058_l14", NULL), 220 [PM8058_VREG_ID_L15] = REGULATOR_SUPPLY("8058_l15", NULL), 221 [PM8058_VREG_ID_L18] = REGULATOR_SUPPLY("8058_l18", NULL), 222 [PM8058_VREG_ID_S4] = REGULATOR_SUPPLY("8058_s4", NULL), 223 224 [PM8058_VREG_ID_LVS0] = REGULATOR_SUPPLY("8058_lvs0", NULL), 225}; 226 227#define PM8058_VREG_INIT(_id, _min_uV, _max_uV, _modes, _ops, _apply_uV, \ 228 _always_on, _pull_down) \ 229 { \ 230 .init_data = { \ 231 .constraints = { \ 232 .valid_modes_mask = _modes, \ 233 .valid_ops_mask = _ops, \ 234 .min_uV = _min_uV, \ 235 .max_uV = _max_uV, \ 236 .apply_uV = _apply_uV, \ 237 .always_on = _always_on, \ 238 }, \ 239 .num_consumer_supplies = 1, \ 240 .consumer_supplies = &pm8058_vreg_supply[_id], \ 241 }, \ 242 .id = _id, \ 243 .pull_down_enable = _pull_down, \ 244 .pin_ctrl = 0, \ 245 .pin_fn = PM8058_VREG_PIN_FN_ENABLE, \ 246 } 247 248#define PM8058_VREG_INIT_LDO(_id, _min_uV, _max_uV) \ 249 PM8058_VREG_INIT(_id, _min_uV, _max_uV, REGULATOR_MODE_NORMAL | \ 250 REGULATOR_MODE_IDLE | REGULATOR_MODE_STANDBY, \ 251 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS | \ 252 REGULATOR_CHANGE_MODE, 1, 1, 1) 253 254#define PM8058_VREG_INIT_SMPS(_id, _min_uV, _max_uV) \ 255 PM8058_VREG_INIT(_id, _min_uV, _max_uV, REGULATOR_MODE_NORMAL | \ 256 REGULATOR_MODE_IDLE | REGULATOR_MODE_STANDBY, \ 257 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS | \ 258 REGULATOR_CHANGE_MODE, 1, 1, 1) 259 260#define PM8058_VREG_INIT_LVS(_id, _min_uV, _max_uV) \ 261 PM8058_VREG_INIT(_id, _min_uV, _min_uV, REGULATOR_MODE_NORMAL, \ 262 REGULATOR_CHANGE_STATUS, 0, 0, 1) 263 264static struct pm8058_vreg_pdata pm8058_vreg_init[] = { 265 PM8058_VREG_INIT_LDO(PM8058_VREG_ID_L3, 3000000, 3000000), 266 PM8058_VREG_INIT_LDO(PM8058_VREG_ID_L8, 2200000, 2200000), 267 PM8058_VREG_INIT_LDO(PM8058_VREG_ID_L9, 2050000, 2050000), 268 PM8058_VREG_INIT_LDO(PM8058_VREG_ID_L14, 2850000, 2850000), 269 PM8058_VREG_INIT_LDO(PM8058_VREG_ID_L15, 2200000, 2200000), 270 PM8058_VREG_INIT_LDO(PM8058_VREG_ID_L18, 2200000, 2200000), 271 PM8058_VREG_INIT_LVS(PM8058_VREG_ID_LVS0, 1800000, 1800000), 272 PM8058_VREG_INIT_SMPS(PM8058_VREG_ID_S4, 1300000, 1300000), 273}; 274 275#ifdef CONFIG_SENSORS_MSM_ADC 276static struct adc_access_fn xoadc_fn = { 277 pm8058_xoadc_select_chan_and_start_conv, 278 pm8058_xoadc_read_adc_code, 279 pm8058_xoadc_get_properties, 280 pm8058_xoadc_slot_request, 281 pm8058_xoadc_restore_slot, 282 pm8058_xoadc_calibrate, 283}; 284 285static struct msm_adc_channels msm_adc_channels_data[] = { 286 {"pmic_therm", CHANNEL_ADC_DIE_TEMP, 0, &xoadc_fn, CHAN_PATH_TYPE12, 287 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE1, scale_pmic_therm}, 288 {"ref_1250mv", CHANNEL_ADC_1250_REF, 0, &xoadc_fn, CHAN_PATH_TYPE13, 289 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE2, scale_default}, 290 {"xo_therm", CHANNEL_ADC_XOTHERM, 0, &xoadc_fn, CHAN_PATH_TYPE_NONE, 291 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE5, tdkntcgtherm}, 292 {"fsm_therm", CHANNEL_ADC_FSM_THERM, 0, &xoadc_fn, CHAN_PATH_TYPE6, 293 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE5, tdkntcgtherm}, 294 {"pa_therm", CHANNEL_ADC_PA_THERM, 0, &xoadc_fn, CHAN_PATH_TYPE7, 295 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE5, tdkntcgtherm}, 296}; 297 298static struct msm_adc_platform_data msm_adc_pdata = { 299 .channel = msm_adc_channels_data, 300 .num_chan_supported = ARRAY_SIZE(msm_adc_channels_data), 301 .target_hw = FSM_9xxx, 302}; 303 304static struct platform_device msm_adc_device = { 305 .name = "msm_adc", 306 .id = -1, 307 .dev = { 308 .platform_data = &msm_adc_pdata, 309 }, 310}; 311 312static void pmic8058_xoadc_mpp_config(void) 313{ 314 int rc, i; 315 struct pm8xxx_mpp_init_info xoadc_mpps[] = { 316 PM8XXX_MPP_INIT(PMIC_MPP_7, A_INPUT, PM8XXX_MPP_AIN_AMUX_CH5, 317 AOUT_CTRL_DISABLE), 318 PM8XXX_MPP_INIT(PMIC_MPP_10, A_INPUT, PM8XXX_MPP_AIN_AMUX_CH6, 319 AOUT_CTRL_DISABLE), 320 }; 321 for (i = 0; i < ARRAY_SIZE(xoadc_mpps); i++) { 322 rc = pm8xxx_mpp_config(xoadc_mpps[i].mpp, 323 &xoadc_mpps[i].config); 324 if (rc) { 325 pr_err("%s: Config MPP %d of PM8058 failed\n", 326 __func__, xoadc_mpps[i].mpp); 327 } 328 } 329} 330 331static struct regulator *vreg_ldo18_adc; 332 333static int pmic8058_xoadc_vreg_config(int on) 334{ 335 int rc; 336 337 if (on) { 338 rc = regulator_enable(vreg_ldo18_adc); 339 if (rc) 340 pr_err("%s: Enable of regulator ldo18_adc " 341 "failed\n", __func__); 342 } else { 343 rc = regulator_disable(vreg_ldo18_adc); 344 if (rc) 345 pr_err("%s: Disable of regulator ldo18_adc " 346 "failed\n", __func__); 347 } 348 349 return rc; 350} 351 352static int pmic8058_xoadc_vreg_setup(void) 353{ 354 int rc; 355 356 vreg_ldo18_adc = regulator_get(NULL, "8058_l18"); 357 if (IS_ERR(vreg_ldo18_adc)) { 358 pr_err("%s: vreg get failed (%ld)\n", 359 __func__, PTR_ERR(vreg_ldo18_adc)); 360 rc = PTR_ERR(vreg_ldo18_adc); 361 goto fail; 362 } 363 364 rc = regulator_set_voltage(vreg_ldo18_adc, 2200000, 2200000); 365 if (rc) { 366 pr_err("%s: unable to set ldo18 voltage to 2.2V\n", __func__); 367 goto fail; 368 } 369 370 return rc; 371fail: 372 regulator_put(vreg_ldo18_adc); 373 return rc; 374} 375 376static void pmic8058_xoadc_vreg_shutdown(void) 377{ 378 regulator_put(vreg_ldo18_adc); 379} 380 381/* usec. For this ADC, 382 * this time represents clk rate @ txco w/ 1024 decimation ratio. 383 * Each channel has different configuration, thus at the time of starting 384 * the conversion, xoadc will return actual conversion time 385 * */ 386static struct adc_properties pm8058_xoadc_data = { 387 .adc_reference = 2200, /* milli-voltage for this adc */ 388 .bitresolution = 15, 389 .bipolar = 0, 390 .conversiontime = 54, 391}; 392 393static struct xoadc_platform_data pm8058_xoadc_pdata = { 394 .xoadc_prop = &pm8058_xoadc_data, 395 .xoadc_mpp_config = pmic8058_xoadc_mpp_config, 396 .xoadc_vreg_set = pmic8058_xoadc_vreg_config, 397 .xoadc_num = XOADC_PMIC_0, 398 .xoadc_vreg_setup = pmic8058_xoadc_vreg_setup, 399 .xoadc_vreg_shutdown = pmic8058_xoadc_vreg_shutdown, 400}; 401#endif 402 403#define XO_CONSUMERS(_id) \ 404 static struct regulator_consumer_supply xo_consumers_##_id[] 405 406/* 407 * Consumer specific regulator names: 408 * regulator name consumer dev_name 409 */ 410XO_CONSUMERS(A0) = { 411 REGULATOR_SUPPLY("8058_xo_a0", NULL), 412 REGULATOR_SUPPLY("a0_clk_buffer", "fsm_xo_driver"), 413}; 414XO_CONSUMERS(A1) = { 415 REGULATOR_SUPPLY("8058_xo_a1", NULL), 416 REGULATOR_SUPPLY("a1_clk_buffer", "fsm_xo_driver"), 417}; 418 419#define PM8058_XO_INIT(_id, _modes, _ops, _always_on) \ 420 { \ 421 .init_data = { \ 422 .constraints = { \ 423 .valid_modes_mask = _modes, \ 424 .valid_ops_mask = _ops, \ 425 .boot_on = 1, \ 426 .always_on = _always_on, \ 427 }, \ 428 .num_consumer_supplies = \ 429 ARRAY_SIZE(xo_consumers_##_id),\ 430 .consumer_supplies = xo_consumers_##_id, \ 431 }, \ 432 .id = PM8058_XO_ID_##_id, \ 433 } 434 435#define PM8058_XO_INIT_AX(_id) \ 436 PM8058_XO_INIT(_id, REGULATOR_MODE_NORMAL, REGULATOR_CHANGE_STATUS, 0) 437 438static struct pm8058_xo_pdata pm8058_xo_init_pdata[] = { 439 PM8058_XO_INIT_AX(A0), 440 PM8058_XO_INIT_AX(A1), 441}; 442 443#define PM8058_GPIO_INT 47 444 445static struct pm8xxx_irq_platform_data pm8xxx_irq_pdata = { 446 .irq_base = PMIC8058_IRQ_BASE, 447 .devirq = MSM_GPIO_TO_INT(PM8058_GPIO_INT), 448 .irq_trigger_flag = IRQF_TRIGGER_LOW, 449}; 450 451static struct pm8xxx_gpio_platform_data pm8xxx_gpio_pdata = { 452 .gpio_base = PM8058_GPIO_PM_TO_SYS(0), 453}; 454 455static struct pm8xxx_mpp_platform_data pm8xxx_mpp_pdata = { 456 .mpp_base = PM8058_MPP_PM_TO_SYS(0), 457}; 458 459static struct pm8058_platform_data pm8058_fsm9xxx_data = { 460 .irq_pdata = &pm8xxx_irq_pdata, 461 .gpio_pdata = &pm8xxx_gpio_pdata, 462 .mpp_pdata = &pm8xxx_mpp_pdata, 463 .regulator_pdatas = pm8058_vreg_init, 464 .num_regulators = ARRAY_SIZE(pm8058_vreg_init), 465 .xo_buffer_pdata = pm8058_xo_init_pdata, 466 .num_xo_buffers = ARRAY_SIZE(pm8058_xo_init_pdata), 467#ifdef CONFIG_SENSORS_MSM_ADC 468 .xoadc_pdata = &pm8058_xoadc_pdata, 469#endif 470}; 471 472#ifdef CONFIG_MSM_SSBI 473static struct msm_ssbi_platform_data fsm9xxx_ssbi_pm8058_pdata = { 474 .controller_type = FSM_SBI_CTRL_SSBI, 475 .slave = { 476 .name = "pm8058-core", 477 .platform_data = &pm8058_fsm9xxx_data, 478 }, 479}; 480#endif 481 482static int __init buses_init(void) 483{ 484 if (gpio_tlmm_config(GPIO_CFG(PMIC_GPIO_INT, 5, GPIO_CFG_INPUT, 485 GPIO_CFG_NO_PULL, GPIO_CFG_2MA), GPIO_CFG_ENABLE)) 486 pr_err("%s: gpio_tlmm_config (gpio=%d) failed\n", 487 __func__, PMIC_GPIO_INT); 488 489 return 0; 490} 491 492/* 493 * EPHY 494 */ 495 496static struct msm_gpio phy_config_data[] = { 497 { GPIO_CFG(GPIO_EPHY_RST_N, 0, GPIO_CFG_OUTPUT, 498 GPIO_CFG_NO_PULL, GPIO_CFG_8MA), "MAC_RST_N" }, 499 { GPIO_CFG(GPIO_MAC_TXD_3, 0, GPIO_CFG_OUTPUT, 500 GPIO_CFG_NO_PULL, GPIO_CFG_8MA), "MAC_TXD_3"}, 501 { GPIO_CFG(GPIO_MAC_TXD_2, 0, GPIO_CFG_OUTPUT, 502 GPIO_CFG_NO_PULL, GPIO_CFG_8MA), "MAC_TXD_2"}, 503 { GPIO_CFG(GPIO_MAC_TXD_1, 0, GPIO_CFG_OUTPUT, 504 GPIO_CFG_NO_PULL, GPIO_CFG_8MA), "MAC_TXD_1"}, 505 { GPIO_CFG(GPIO_MAC_TXD_0, 0, GPIO_CFG_OUTPUT, 506 GPIO_CFG_NO_PULL, GPIO_CFG_8MA), "MAC_TXD_0"}, 507 { GPIO_CFG(GPIO_MAC_TX_EN, 0, GPIO_CFG_OUTPUT, 508 GPIO_CFG_NO_PULL, GPIO_CFG_8MA), "MAC_TX_EN"}, 509 { GPIO_CFG(GPIO_MAC_TX_CLK, 0, GPIO_CFG_OUTPUT, 510 GPIO_CFG_NO_PULL, GPIO_CFG_10MA), "MAC_TX_CLK"}, 511 { GPIO_CFG(GPIO_MAC_MDIO, 0, GPIO_CFG_OUTPUT, 512 GPIO_CFG_NO_PULL, GPIO_CFG_6MA), "MDIO_MAC_MDIO"}, 513 { GPIO_CFG(GPIO_MAC_MDC, 0, GPIO_CFG_OUTPUT, 514 GPIO_CFG_NO_PULL, GPIO_CFG_6MA), "MDC_MAC_MDC"}, 515}; 516 517static int __init phy_init(void) 518{ 519 msm_gpios_request_enable(phy_config_data, ARRAY_SIZE(phy_config_data)); 520 gpio_direction_output(GPIO_EPHY_RST_N, 0); 521 udelay(100); 522 gpio_set_value(GPIO_EPHY_RST_N, 1); 523 524 return 0; 525} 526 527/* 528 * RF 529 */ 530 531static struct msm_gpio grfc_config_data[] = { 532 { GPIO_CFG(GPIO_GRFC_FTR0_0, 7, GPIO_CFG_OUTPUT, 533 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "HH_RFMODE1_0" }, 534 { GPIO_CFG(GPIO_GRFC_FTR0_1, 7, GPIO_CFG_OUTPUT, 535 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "HH_RFMODE1_1" }, 536 { GPIO_CFG(GPIO_GRFC_FTR1_0, 7, GPIO_CFG_OUTPUT, 537 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "HH_RFMODE2_0" }, 538 { GPIO_CFG(GPIO_GRFC_FTR1_1, 7, GPIO_CFG_OUTPUT, 539 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "HH_RFMODE2_1" }, 540 { GPIO_CFG(GPIO_GRFC_2, 7, GPIO_CFG_OUTPUT, 541 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_2" }, 542 { GPIO_CFG(GPIO_GRFC_3, 7, GPIO_CFG_OUTPUT, 543 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_3" }, 544 { GPIO_CFG(GPIO_GRFC_4, 7, GPIO_CFG_OUTPUT, 545 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_4" }, 546 { GPIO_CFG(GPIO_GRFC_5, 7, GPIO_CFG_OUTPUT, 547 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_5" }, 548 { GPIO_CFG(GPIO_GRFC_6, 7, GPIO_CFG_OUTPUT, 549 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_6" }, 550 { GPIO_CFG(GPIO_GRFC_7, 7, GPIO_CFG_OUTPUT, 551 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_7" }, 552 { GPIO_CFG(GPIO_GRFC_8, 7, GPIO_CFG_OUTPUT, 553 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_8" }, 554 { GPIO_CFG(GPIO_GRFC_9, 7, GPIO_CFG_OUTPUT, 555 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_9" }, 556 { GPIO_CFG(GPIO_GRFC_10, 7, GPIO_CFG_OUTPUT, 557 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_10" }, 558 { GPIO_CFG(GPIO_GRFC_11, 7, GPIO_CFG_OUTPUT, 559 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_11" }, 560 { GPIO_CFG(GPIO_GRFC_13, 7, GPIO_CFG_OUTPUT, 561 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_13" }, 562 { GPIO_CFG(GPIO_GRFC_14, 7, GPIO_CFG_OUTPUT, 563 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_14" }, 564 { GPIO_CFG(GPIO_GRFC_15, 7, GPIO_CFG_OUTPUT, 565 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_15" }, 566 { GPIO_CFG(GPIO_GRFC_16, 7, GPIO_CFG_OUTPUT, 567 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_16" }, 568 { GPIO_CFG(GPIO_GRFC_17, 7, GPIO_CFG_OUTPUT, 569 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_17" }, 570 { GPIO_CFG(GPIO_GRFC_18, 7, GPIO_CFG_OUTPUT, 571 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_18" }, 572 { GPIO_CFG(GPIO_GRFC_24, 7, GPIO_CFG_OUTPUT, 573 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_24" }, 574 { GPIO_CFG(GPIO_GRFC_25, 7, GPIO_CFG_OUTPUT, 575 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_25" }, 576 { GPIO_CFG(GPIO_GRFC_26, 7, GPIO_CFG_OUTPUT, 577 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_26" }, 578 { GPIO_CFG(GPIO_GRFC_27, 7, GPIO_CFG_OUTPUT, 579 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_27" }, 580 { GPIO_CFG(GPIO_GRFC_28, 7, GPIO_CFG_OUTPUT, 581 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_28" }, 582 { GPIO_CFG(GPIO_GRFC_29, 7, GPIO_CFG_OUTPUT, 583 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_29" }, 584 { GPIO_CFG(39, 1, GPIO_CFG_OUTPUT, 585 GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "PP2S_EXT_SYNC" }, 586}; 587 588static int __init grfc_init(void) 589{ 590 msm_gpios_request_enable(grfc_config_data, 591 ARRAY_SIZE(grfc_config_data)); 592 593 return 0; 594} 595 596/* 597 * UART 598 */ 599 600#ifdef CONFIG_SERIAL_MSM_CONSOLE 601static struct msm_gpio uart1_config_data[] = { 602 { GPIO_CFG(138, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), 603 "UART1_Rx" }, 604 { GPIO_CFG(139, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), 605 "UART1_Tx" }, 606}; 607 608static void fsm9xxx_init_uart1(void) 609{ 610 msm_gpios_request_enable(uart1_config_data, 611 ARRAY_SIZE(uart1_config_data)); 612 613} 614#endif 615 616static struct msm_gpio uart3_uim_config_data[] = { 617 { GPIO_CFG(GPIO_UIM_RESET, 0, GPIO_CFG_OUTPUT, 618 GPIO_CFG_PULL_UP, GPIO_CFG_2MA), "UIM_Reset" }, 619 { GPIO_CFG(GPIO_UIM_DATA_IO, 2, GPIO_CFG_OUTPUT, 620 GPIO_CFG_PULL_UP, GPIO_CFG_2MA), "UIM_Data" }, 621 { GPIO_CFG(GPIO_UIM_CLOCK, 2, GPIO_CFG_OUTPUT, 622 GPIO_CFG_PULL_UP, GPIO_CFG_2MA), "UIM_Clock" }, 623}; 624 625static void fsm9xxx_init_uart3_uim(void) 626{ 627 struct pm_gpio pmic_uim_gpio_in = { 628 .direction = PM_GPIO_DIR_IN, 629 .pull = PM_GPIO_PULL_NO, 630 .out_strength = PM_GPIO_STRENGTH_HIGH, 631 .function = PM_GPIO_FUNC_PAIRED, 632 .vin_sel = PM8058_GPIO_VIN_L3, 633 }; 634 struct pm_gpio pmic_uim_gpio_out = { 635 .direction = PM_GPIO_DIR_OUT, 636 .pull = PM_GPIO_PULL_NO, 637 .out_strength = PM_GPIO_STRENGTH_HIGH, 638 .function = PM_GPIO_FUNC_PAIRED, 639 .vin_sel = PM8058_GPIO_VIN_L3, 640 }; 641 642 /* TLMM */ 643 msm_gpios_request_enable(uart3_uim_config_data, 644 ARRAY_SIZE(uart3_uim_config_data)); 645 646 /* Put UIM to reset state */ 647 gpio_direction_output(GPIO_UIM_RESET, 0); 648 gpio_set_value(GPIO_UIM_RESET, 0); 649 gpio_export(GPIO_UIM_RESET, false); 650 651 /* PMIC */ 652 pm8xxx_gpio_config(PM8058_GPIO_PM_TO_SYS(GPIO_PM_UIM_M_RST), 653 &pmic_uim_gpio_in); 654 pm8xxx_gpio_config(PM8058_GPIO_PM_TO_SYS(GPIO_PM_UIM_RST), 655 &pmic_uim_gpio_out); 656 pm8xxx_gpio_config(PM8058_GPIO_PM_TO_SYS(GPIO_PM_UIM_M_CLK), 657 &pmic_uim_gpio_in); 658 pm8xxx_gpio_config(PM8058_GPIO_PM_TO_SYS(GPIO_PM_UIM_CLK), 659 &pmic_uim_gpio_out); 660} 661 662/* 663 * SSBI 664 */ 665 666#ifdef CONFIG_I2C_SSBI 667static struct msm_i2c_ssbi_platform_data msm_i2c_ssbi2_pdata = { 668 .controller_type = FSM_SBI_CTRL_SSBI, 669}; 670 671static struct msm_i2c_ssbi_platform_data msm_i2c_ssbi3_pdata = { 672 .controller_type = FSM_SBI_CTRL_SSBI, 673}; 674#endif 675 676#if defined(CONFIG_I2C_SSBI) || defined(CONFIG_MSM_SSBI) 677/* Intialize GPIO configuration for SSBI */ 678static struct msm_gpio ssbi_gpio_config_data[] = { 679 { GPIO_CFG(140, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), 680 "SSBI_1" }, 681 { GPIO_CFG(141, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), 682 "SSBI_2" }, 683 { GPIO_CFG(92, 2, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), 684 "SSBI_3" }, 685}; 686 687static void 688fsm9xxx_init_ssbi_gpio(void) 689{ 690 msm_gpios_request_enable(ssbi_gpio_config_data, 691 ARRAY_SIZE(ssbi_gpio_config_data)); 692 693} 694#endif 695 696/* 697 * User GPIOs 698 */ 699 700static void user_gpios_init(void) 701{ 702 unsigned int gpio; 703 704 for (gpio = GPIO_USER_FIRST; gpio <= GPIO_USER_LAST; ++gpio) 705 gpio_tlmm_config(GPIO_CFG(gpio, 0, GPIO_CFG_INPUT, 706 GPIO_CFG_NO_PULL, GPIO_CFG_2MA), GPIO_CFG_ENABLE); 707} 708 709/* 710 * Crypto 711 */ 712 713#define QCE_SIZE 0x10000 714 715#define QCE_0_BASE 0x80C00000 716#define QCE_1_BASE 0x80E00000 717#define QCE_2_BASE 0x81000000 718 719#define QCE_NO_HW_KEY_SUPPORT 0 /* No shared HW key with external */ 720#define QCE_NO_SHARE_CE_RESOURCE 0 /* No CE resource shared with TZ */ 721#define QCE_NO_CE_SHARED 0 /* CE not shared with TZ */ 722#define QCE_NO_SHA_HMAC_SUPPORT 0 /* No SHA-HMAC by SHA operation */ 723 724static struct resource qcrypto_resources[] = { 725 [0] = { 726 .start = QCE_0_BASE, 727 .end = QCE_0_BASE + QCE_SIZE - 1, 728 .flags = IORESOURCE_MEM, 729 }, 730 [1] = { 731 .name = "crypto_channels", 732 .start = DMOV_CE1_IN_CHAN, 733 .end = DMOV_CE1_OUT_CHAN, 734 .flags = IORESOURCE_DMA, 735 }, 736 [2] = { 737 .name = "crypto_crci_in", 738 .start = DMOV_CE1_IN_CRCI, 739 .end = DMOV_CE1_IN_CRCI, 740 .flags = IORESOURCE_DMA, 741 }, 742 [3] = { 743 .name = "crypto_crci_out", 744 .start = DMOV_CE1_OUT_CRCI, 745 .end = DMOV_CE1_OUT_CRCI, 746 .flags = IORESOURCE_DMA, 747 }, 748 [4] = { 749 .name = "crypto_crci_hash", 750 .start = DMOV_CE1_HASH_CRCI, 751 .end = DMOV_CE1_HASH_CRCI, 752 .flags = IORESOURCE_DMA, 753 }, 754}; 755 756static struct msm_ce_hw_support qcrypto_ce_hw_suppport = { 757 .ce_shared = QCE_NO_CE_SHARED, 758 .shared_ce_resource = QCE_NO_SHARE_CE_RESOURCE, 759 .hw_key_support = QCE_NO_HW_KEY_SUPPORT, 760 .sha_hmac = QCE_NO_SHA_HMAC_SUPPORT, 761 .bus_scale_table = NULL, 762}; 763 764struct platform_device qcrypto_device = { 765 .name = "qcrypto", 766 .id = 0, 767 .num_resources = ARRAY_SIZE(qcrypto_resources), 768 .resource = qcrypto_resources, 769 .dev = { 770 .coherent_dma_mask = DMA_BIT_MASK(32), 771 .platform_data = &qcrypto_ce_hw_suppport, 772 }, 773}; 774 775static struct resource qcedev_resources[] = { 776 [0] = { 777 .start = QCE_0_BASE, 778 .end = QCE_0_BASE + QCE_SIZE - 1, 779 .flags = IORESOURCE_MEM, 780 }, 781 [1] = { 782 .name = "crypto_channels", 783 .start = DMOV_CE1_IN_CHAN, 784 .end = DMOV_CE1_OUT_CHAN, 785 .flags = IORESOURCE_DMA, 786 }, 787 [2] = { 788 .name = "crypto_crci_in", 789 .start = DMOV_CE1_IN_CRCI, 790 .end = DMOV_CE1_IN_CRCI, 791 .flags = IORESOURCE_DMA, 792 }, 793 [3] = { 794 .name = "crypto_crci_out", 795 .start = DMOV_CE1_OUT_CRCI, 796 .end = DMOV_CE1_OUT_CRCI, 797 .flags = IORESOURCE_DMA, 798 }, 799 [4] = { 800 .name = "crypto_crci_hash", 801 .start = DMOV_CE1_HASH_CRCI, 802 .end = DMOV_CE1_HASH_CRCI, 803 .flags = IORESOURCE_DMA, 804 }, 805}; 806 807static struct msm_ce_hw_support qcedev_ce_hw_suppport = { 808 .ce_shared = QCE_NO_CE_SHARED, 809 .shared_ce_resource = QCE_NO_SHARE_CE_RESOURCE, 810 .hw_key_support = QCE_NO_HW_KEY_SUPPORT, 811 .sha_hmac = QCE_NO_SHA_HMAC_SUPPORT, 812 .bus_scale_table = NULL, 813}; 814 815static struct platform_device qcedev_device = { 816 .name = "qce", 817 .id = 0, 818 .num_resources = ARRAY_SIZE(qcedev_resources), 819 .resource = qcedev_resources, 820 .dev = { 821 .coherent_dma_mask = DMA_BIT_MASK(32), 822 .platform_data = &qcedev_ce_hw_suppport, 823 }, 824}; 825 826static struct resource ota_qcrypto_resources[] = { 827 [0] = { 828 .start = QCE_1_BASE, 829 .end = QCE_1_BASE + QCE_SIZE - 1, 830 .flags = IORESOURCE_MEM, 831 }, 832 [1] = { 833 .name = "crypto_channels", 834 .start = DMOV_CE2_IN_CHAN, 835 .end = DMOV_CE2_OUT_CHAN, 836 .flags = IORESOURCE_DMA, 837 }, 838 [2] = { 839 .name = "crypto_crci_in", 840 .start = DMOV_CE2_IN_CRCI, 841 .end = DMOV_CE2_IN_CRCI, 842 .flags = IORESOURCE_DMA, 843 }, 844 [3] = { 845 .name = "crypto_crci_out", 846 .start = DMOV_CE2_OUT_CRCI, 847 .end = DMOV_CE2_OUT_CRCI, 848 .flags = IORESOURCE_DMA, 849 }, 850 [4] = { 851 .name = "crypto_crci_hash", 852 .start = DMOV_CE2_HASH_CRCI, 853 .end = DMOV_CE2_HASH_CRCI, 854 .flags = IORESOURCE_DMA, 855 }, 856}; 857 858struct platform_device ota_qcrypto_device = { 859 .name = "qcota", 860 .id = 0, 861 .num_resources = ARRAY_SIZE(ota_qcrypto_resources), 862 .resource = ota_qcrypto_resources, 863 .dev = { 864 .coherent_dma_mask = DMA_BIT_MASK(32), 865 }, 866}; 867 868static struct platform_device fsm9xxx_device_acpuclk = { 869 .name = "acpuclk-9xxx", 870 .id = -1, 871}; 872 873/* 874 * Devices 875 */ 876 877static struct platform_device *devices[] __initdata = { 878 &fsm9xxx_device_acpuclk, 879 &msm_device_smd, 880 &msm_device_dmov, 881 &msm_device_nand, 882#ifdef CONFIG_MSM_SSBI 883 &msm_device_ssbi_pmic1, 884#endif 885#ifdef CONFIG_I2C_SSBI 886 &msm_device_ssbi2, 887 &msm_device_ssbi3, 888#endif 889#ifdef CONFIG_SENSORS_MSM_ADC 890 &msm_adc_device, 891#endif 892#ifdef CONFIG_I2C_QUP 893 &msm_gsbi1_qup_i2c_device, 894#endif 895#if defined(CONFIG_SERIAL_MSM) || defined(CONFIG_MSM_SERIAL_DEBUGGER) 896 &msm_device_uart1, 897#endif 898 &msm_device_uart3, 899#if defined(CONFIG_QFP_FUSE) 900 &fsm_qfp_fuse_device, 901#endif 902 &qfec_device, 903 &qcrypto_device, 904 &qcedev_device, 905 &ota_qcrypto_device, 906 &fsm_xo_device, 907 &fsm9xxx_device_watchdog, 908}; 909 910static void __init fsm9xxx_init_irq(void) 911{ 912 msm_init_irq(); 913 msm_init_sirc(); 914} 915 916#ifdef CONFIG_MSM_SPM 917static struct msm_spm_platform_data msm_spm_data __initdata = { 918 .reg_base_addr = MSM_SAW_BASE, 919 920 .reg_init_values[MSM_SPM_REG_SAW_CFG] = 0x05, 921 .reg_init_values[MSM_SPM_REG_SAW_SPM_CTL] = 0x18, 922 .reg_init_values[MSM_SPM_REG_SAW_SPM_SLP_TMR_DLY] = 0x00006666, 923 .reg_init_values[MSM_SPM_REG_SAW_SPM_WAKE_TMR_DLY] = 0xFF000666, 924 925 .reg_init_values[MSM_SPM_REG_SAW_SPM_PMIC_CTL] = 0xE0F272, 926 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLK_EN] = 0x01, 927 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_PRECLMP_EN] = 0x03, 928 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_POSTCLMP_EN] = 0x00, 929 930 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLMP_EN] = 0x01, 931 .reg_init_values[MSM_SPM_REG_SAW_SLP_RST_EN] = 0x00, 932 .reg_init_values[MSM_SPM_REG_SAW_SPM_MPM_CFG] = 0x00, 933 934 .awake_vlevel = 0xF2, 935 .retention_vlevel = 0xE0, 936 .collapse_vlevel = 0x72, 937 .retention_mid_vlevel = 0xE0, 938 .collapse_mid_vlevel = 0xE0, 939}; 940#endif 941 942static void __init fsm9xxx_init(void) 943{ 944 regulator_has_full_constraints(); 945 946#if defined(CONFIG_I2C_SSBI) || defined(CONFIG_MSM_SSBI) 947 fsm9xxx_init_ssbi_gpio(); 948#endif 949#ifdef CONFIG_MSM_SSBI 950 msm_device_ssbi_pmic1.dev.platform_data = 951 &fsm9xxx_ssbi_pm8058_pdata; 952#endif 953 buses_init(); 954 955 platform_add_devices(devices, ARRAY_SIZE(devices)); 956 957#ifdef CONFIG_MSM_SPM 958 msm_spm_init(&msm_spm_data, 1); 959#endif 960 pm8058_gpios_init(); 961 pm8058_mpps_init(); 962 phy_init(); 963 grfc_init(); 964 user_gpios_init(); 965 966#ifdef CONFIG_SERIAL_MSM_CONSOLE 967 fsm9xxx_init_uart1(); 968#endif 969 fsm9xxx_init_uart3_uim(); 970#ifdef CONFIG_I2C_SSBI 971 msm_device_ssbi2.dev.platform_data = &msm_i2c_ssbi2_pdata; 972 msm_device_ssbi3.dev.platform_data = &msm_i2c_ssbi3_pdata; 973#endif 974} 975 976static void __init fsm9xxx_map_io(void) 977{ 978 msm_shared_ram_phys = 0x00100000; 979 msm_map_fsm9xxx_io(); 980 msm_clock_init(&fsm9xxx_clock_init_data); 981 if (socinfo_init() < 0) 982 pr_err("%s: socinfo_init() failed!\n", 983 __func__); 984 985} 986 987MACHINE_START(FSM9XXX_SURF, "QCT FSM9XXX") 988 .atag_offset = 0x100, 989 .map_io = fsm9xxx_map_io, 990 .init_irq = fsm9xxx_init_irq, 991 .handle_irq = vic_handle_irq, 992 .init_machine = fsm9xxx_init, 993 .timer = &msm_timer, 994 .restart = fsm_restart, 995MACHINE_END