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/arch/powerpc/include/asm/processor.h

https://github.com/aicjofs/android_kernel_lge_v500_20d_f2fs
C Header | 420 lines | 272 code | 74 blank | 74 comment | 5 complexity | 231ef22a4d81937523ff0d1d81149342 MD5 | raw file
  1#ifndef _ASM_POWERPC_PROCESSOR_H
  2#define _ASM_POWERPC_PROCESSOR_H
  3
  4/*
  5 * Copyright (C) 2001 PPC 64 Team, IBM Corp
  6 *
  7 * This program is free software; you can redistribute it and/or
  8 * modify it under the terms of the GNU General Public License
  9 * as published by the Free Software Foundation; either version
 10 * 2 of the License, or (at your option) any later version.
 11 */
 12
 13#include <asm/reg.h>
 14
 15#ifdef CONFIG_VSX
 16#define TS_FPRWIDTH 2
 17#else
 18#define TS_FPRWIDTH 1
 19#endif
 20
 21#ifndef __ASSEMBLY__
 22#include <linux/compiler.h>
 23#include <linux/cache.h>
 24#include <asm/ptrace.h>
 25#include <asm/types.h>
 26
 27/* We do _not_ want to define new machine types at all, those must die
 28 * in favor of using the device-tree
 29 * -- BenH.
 30 */
 31
 32/* PREP sub-platform types see residual.h for these */
 33#define _PREP_Motorola	0x01	/* motorola prep */
 34#define _PREP_Firm	0x02	/* firmworks prep */
 35#define _PREP_IBM	0x00	/* ibm prep */
 36#define _PREP_Bull	0x03	/* bull prep */
 37
 38/* CHRP sub-platform types. These are arbitrary */
 39#define _CHRP_Motorola	0x04	/* motorola chrp, the cobra */
 40#define _CHRP_IBM	0x05	/* IBM chrp, the longtrail and longtrail 2 */
 41#define _CHRP_Pegasos	0x06	/* Genesi/bplan's Pegasos and Pegasos2 */
 42#define _CHRP_briq	0x07	/* TotalImpact's briQ */
 43
 44#if defined(__KERNEL__) && defined(CONFIG_PPC32)
 45
 46extern int _chrp_type;
 47
 48#ifdef CONFIG_PPC_PREP
 49
 50/* what kind of prep workstation we are */
 51extern int _prep_type;
 52
 53#endif /* CONFIG_PPC_PREP */
 54
 55#endif /* defined(__KERNEL__) && defined(CONFIG_PPC32) */
 56
 57/*
 58 * Default implementation of macro that returns current
 59 * instruction pointer ("program counter").
 60 */
 61#define current_text_addr() ({ __label__ _l; _l: &&_l;})
 62
 63/* Macros for adjusting thread priority (hardware multi-threading) */
 64#define HMT_very_low()   asm volatile("or 31,31,31   # very low priority")
 65#define HMT_low()	 asm volatile("or 1,1,1	     # low priority")
 66#define HMT_medium_low() asm volatile("or 6,6,6      # medium low priority")
 67#define HMT_medium()	 asm volatile("or 2,2,2	     # medium priority")
 68#define HMT_medium_high() asm volatile("or 5,5,5      # medium high priority")
 69#define HMT_high()	 asm volatile("or 3,3,3	     # high priority")
 70
 71#ifdef __KERNEL__
 72
 73struct task_struct;
 74void start_thread(struct pt_regs *regs, unsigned long fdptr, unsigned long sp);
 75void release_thread(struct task_struct *);
 76
 77/* Prepare to copy thread state - unlazy all lazy status */
 78extern void prepare_to_copy(struct task_struct *tsk);
 79
 80/* Create a new kernel thread. */
 81extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
 82
 83/* Lazy FPU handling on uni-processor */
 84extern struct task_struct *last_task_used_math;
 85extern struct task_struct *last_task_used_altivec;
 86extern struct task_struct *last_task_used_vsx;
 87extern struct task_struct *last_task_used_spe;
 88
 89#ifdef CONFIG_PPC32
 90
 91#if CONFIG_TASK_SIZE > CONFIG_KERNEL_START
 92#error User TASK_SIZE overlaps with KERNEL_START address
 93#endif
 94#define TASK_SIZE	(CONFIG_TASK_SIZE)
 95
 96/* This decides where the kernel will search for a free chunk of vm
 97 * space during mmap's.
 98 */
 99#define TASK_UNMAPPED_BASE	(TASK_SIZE / 8 * 3)
100#endif
101
102#ifdef CONFIG_PPC64
103/* 64-bit user address space is 44-bits (16TB user VM) */
104#define TASK_SIZE_USER64 (0x0000100000000000UL)
105
106/* 
107 * 32-bit user address space is 4GB - 1 page 
108 * (this 1 page is needed so referencing of 0xFFFFFFFF generates EFAULT
109 */
110#define TASK_SIZE_USER32 (0x0000000100000000UL - (1*PAGE_SIZE))
111
112#define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \
113		TASK_SIZE_USER32 : TASK_SIZE_USER64)
114#define TASK_SIZE	  TASK_SIZE_OF(current)
115
116/* This decides where the kernel will search for a free chunk of vm
117 * space during mmap's.
118 */
119#define TASK_UNMAPPED_BASE_USER32 (PAGE_ALIGN(TASK_SIZE_USER32 / 4))
120#define TASK_UNMAPPED_BASE_USER64 (PAGE_ALIGN(TASK_SIZE_USER64 / 4))
121
122#define TASK_UNMAPPED_BASE ((is_32bit_task()) ? \
123		TASK_UNMAPPED_BASE_USER32 : TASK_UNMAPPED_BASE_USER64 )
124#endif
125
126#ifdef __powerpc64__
127
128#define STACK_TOP_USER64 TASK_SIZE_USER64
129#define STACK_TOP_USER32 TASK_SIZE_USER32
130
131#define STACK_TOP (is_32bit_task() ? \
132		   STACK_TOP_USER32 : STACK_TOP_USER64)
133
134#define STACK_TOP_MAX STACK_TOP_USER64
135
136#else /* __powerpc64__ */
137
138#define STACK_TOP TASK_SIZE
139#define STACK_TOP_MAX	STACK_TOP
140
141#endif /* __powerpc64__ */
142
143typedef struct {
144	unsigned long seg;
145} mm_segment_t;
146
147#define TS_FPROFFSET 0
148#define TS_VSRLOWOFFSET 1
149#define TS_FPR(i) fpr[i][TS_FPROFFSET]
150
151struct thread_struct {
152	unsigned long	ksp;		/* Kernel stack pointer */
153	unsigned long	ksp_limit;	/* if ksp <= ksp_limit stack overflow */
154
155#ifdef CONFIG_PPC64
156	unsigned long	ksp_vsid;
157#endif
158	struct pt_regs	*regs;		/* Pointer to saved register state */
159	mm_segment_t	fs;		/* for get_fs() validation */
160#ifdef CONFIG_BOOKE
161	/* BookE base exception scratch space; align on cacheline */
162	unsigned long	normsave[8] ____cacheline_aligned;
163#endif
164#ifdef CONFIG_PPC32
165	void		*pgdir;		/* root of page-table tree */
166#endif
167#ifdef CONFIG_PPC_ADV_DEBUG_REGS
168	/*
169	 * The following help to manage the use of Debug Control Registers
170	 * om the BookE platforms.
171	 */
172	unsigned long	dbcr0;
173	unsigned long	dbcr1;
174#ifdef CONFIG_BOOKE
175	unsigned long	dbcr2;
176#endif
177	/*
178	 * The stored value of the DBSR register will be the value at the
179	 * last debug interrupt. This register can only be read from the
180	 * user (will never be written to) and has value while helping to
181	 * describe the reason for the last debug trap.  Torez
182	 */
183	unsigned long	dbsr;
184	/*
185	 * The following will contain addresses used by debug applications
186	 * to help trace and trap on particular address locations.
187	 * The bits in the Debug Control Registers above help define which
188	 * of the following registers will contain valid data and/or addresses.
189	 */
190	unsigned long	iac1;
191	unsigned long	iac2;
192#if CONFIG_PPC_ADV_DEBUG_IACS > 2
193	unsigned long	iac3;
194	unsigned long	iac4;
195#endif
196	unsigned long	dac1;
197	unsigned long	dac2;
198#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
199	unsigned long	dvc1;
200	unsigned long	dvc2;
201#endif
202#endif
203	/* FP and VSX 0-31 register set */
204	double		fpr[32][TS_FPRWIDTH];
205	struct {
206
207		unsigned int pad;
208		unsigned int val;	/* Floating point status */
209	} fpscr;
210	int		fpexc_mode;	/* floating-point exception mode */
211	unsigned int	align_ctl;	/* alignment handling control */
212#ifdef CONFIG_PPC64
213	unsigned long	start_tb;	/* Start purr when proc switched in */
214	unsigned long	accum_tb;	/* Total accumilated purr for process */
215#ifdef CONFIG_HAVE_HW_BREAKPOINT
216	struct perf_event *ptrace_bps[HBP_NUM];
217	/*
218	 * Helps identify source of single-step exception and subsequent
219	 * hw-breakpoint enablement
220	 */
221	struct perf_event *last_hit_ubp;
222#endif /* CONFIG_HAVE_HW_BREAKPOINT */
223#endif
224	unsigned long	dabr;		/* Data address breakpoint register */
225#ifdef CONFIG_ALTIVEC
226	/* Complete AltiVec register set */
227	vector128	vr[32] __attribute__((aligned(16)));
228	/* AltiVec status */
229	vector128	vscr __attribute__((aligned(16)));
230	unsigned long	vrsave;
231	int		used_vr;	/* set if process has used altivec */
232#endif /* CONFIG_ALTIVEC */
233#ifdef CONFIG_VSX
234	/* VSR status */
235	int		used_vsr;	/* set if process has used altivec */
236#endif /* CONFIG_VSX */
237#ifdef CONFIG_SPE
238	unsigned long	evr[32];	/* upper 32-bits of SPE regs */
239	u64		acc;		/* Accumulator */
240	unsigned long	spefscr;	/* SPE & eFP status */
241	int		used_spe;	/* set if process has used spe */
242#endif /* CONFIG_SPE */
243#ifdef CONFIG_KVM_BOOK3S_32_HANDLER
244	void*		kvm_shadow_vcpu; /* KVM internal data */
245#endif /* CONFIG_KVM_BOOK3S_32_HANDLER */
246#ifdef CONFIG_PPC64
247	unsigned long	dscr;
248	int		dscr_inherit;
249#endif
250};
251
252#define ARCH_MIN_TASKALIGN 16
253
254#define INIT_SP		(sizeof(init_stack) + (unsigned long) &init_stack)
255#define INIT_SP_LIMIT \
256	(_ALIGN_UP(sizeof(init_thread_info), 16) + (unsigned long) &init_stack)
257
258#ifdef CONFIG_SPE
259#define SPEFSCR_INIT .spefscr = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE,
260#else
261#define SPEFSCR_INIT
262#endif
263
264#ifdef CONFIG_PPC32
265#define INIT_THREAD { \
266	.ksp = INIT_SP, \
267	.ksp_limit = INIT_SP_LIMIT, \
268	.fs = KERNEL_DS, \
269	.pgdir = swapper_pg_dir, \
270	.fpexc_mode = MSR_FE0 | MSR_FE1, \
271	SPEFSCR_INIT \
272}
273#else
274#define INIT_THREAD  { \
275	.ksp = INIT_SP, \
276	.ksp_limit = INIT_SP_LIMIT, \
277	.regs = (struct pt_regs *)INIT_SP - 1, /* XXX bogus, I think */ \
278	.fs = KERNEL_DS, \
279	.fpr = {{0}}, \
280	.fpscr = { .val = 0, }, \
281	.fpexc_mode = 0, \
282}
283#endif
284
285/*
286 * Return saved PC of a blocked thread. For now, this is the "user" PC
287 */
288#define thread_saved_pc(tsk)    \
289        ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
290
291#define task_pt_regs(tsk)	((struct pt_regs *)(tsk)->thread.regs)
292
293unsigned long get_wchan(struct task_struct *p);
294
295#define KSTK_EIP(tsk)  ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
296#define KSTK_ESP(tsk)  ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0)
297
298/* Get/set floating-point exception mode */
299#define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr))
300#define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val))
301
302extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr);
303extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val);
304
305#define GET_ENDIAN(tsk, adr) get_endian((tsk), (adr))
306#define SET_ENDIAN(tsk, val) set_endian((tsk), (val))
307
308extern int get_endian(struct task_struct *tsk, unsigned long adr);
309extern int set_endian(struct task_struct *tsk, unsigned int val);
310
311#define GET_UNALIGN_CTL(tsk, adr)	get_unalign_ctl((tsk), (adr))
312#define SET_UNALIGN_CTL(tsk, val)	set_unalign_ctl((tsk), (val))
313
314extern int get_unalign_ctl(struct task_struct *tsk, unsigned long adr);
315extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val);
316
317static inline unsigned int __unpack_fe01(unsigned long msr_bits)
318{
319	return ((msr_bits & MSR_FE0) >> 10) | ((msr_bits & MSR_FE1) >> 8);
320}
321
322static inline unsigned long __pack_fe01(unsigned int fpmode)
323{
324	return ((fpmode << 10) & MSR_FE0) | ((fpmode << 8) & MSR_FE1);
325}
326
327#ifdef CONFIG_PPC64
328#define cpu_relax()	do { HMT_low(); HMT_medium(); barrier(); } while (0)
329#else
330#define cpu_relax()	barrier()
331#endif
332
333/* Check that a certain kernel stack pointer is valid in task_struct p */
334int validate_sp(unsigned long sp, struct task_struct *p,
335                       unsigned long nbytes);
336
337/*
338 * Prefetch macros.
339 */
340#define ARCH_HAS_PREFETCH
341#define ARCH_HAS_PREFETCHW
342#define ARCH_HAS_SPINLOCK_PREFETCH
343
344static inline void prefetch(const void *x)
345{
346	if (unlikely(!x))
347		return;
348
349	__asm__ __volatile__ ("dcbt 0,%0" : : "r" (x));
350}
351
352static inline void prefetchw(const void *x)
353{
354	if (unlikely(!x))
355		return;
356
357	__asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x));
358}
359
360#define spin_lock_prefetch(x)	prefetchw(x)
361
362#ifdef CONFIG_PPC64
363#define HAVE_ARCH_PICK_MMAP_LAYOUT
364#endif
365
366#ifdef CONFIG_PPC64
367static inline unsigned long get_clean_sp(struct pt_regs *regs, int is_32)
368{
369	unsigned long sp;
370
371	if (is_32)
372		sp = regs->gpr[1] & 0x0ffffffffUL;
373	else
374		sp = regs->gpr[1];
375
376	return sp;
377}
378#else
379static inline unsigned long get_clean_sp(struct pt_regs *regs, int is_32)
380{
381	return regs->gpr[1];
382}
383#endif
384
385extern unsigned long cpuidle_disable;
386enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_POWERSAVE_OFF};
387
388extern int powersave_nap;	/* set if nap mode can be used in idle loop */
389void cpu_idle_wait(void);
390
391#ifdef CONFIG_PSERIES_IDLE
392extern void update_smt_snooze_delay(int snooze);
393extern int pseries_notify_cpuidle_add_cpu(int cpu);
394#else
395static inline void update_smt_snooze_delay(int snooze) {}
396static inline int pseries_notify_cpuidle_add_cpu(int cpu) { return 0; }
397#endif
398
399extern void flush_instruction_cache(void);
400extern void hard_reset_now(void);
401extern void poweroff_now(void);
402extern int fix_alignment(struct pt_regs *);
403extern void cvt_fd(float *from, double *to);
404extern void cvt_df(double *from, float *to);
405extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
406
407#ifdef CONFIG_PPC64
408/*
409 * We handle most unaligned accesses in hardware. On the other hand 
410 * unaligned DMA can be very expensive on some ppc64 IO chips (it does
411 * powers of 2 writes until it reaches sufficient alignment).
412 *
413 * Based on this we disable the IP header alignment in network drivers.
414 */
415#define NET_IP_ALIGN	0
416#endif
417
418#endif /* __KERNEL__ */
419#endif /* __ASSEMBLY__ */
420#endif /* _ASM_POWERPC_PROCESSOR_H */