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/arch/powerpc/include/asm/pte-hash64-64k.h

https://github.com/aicjofs/android_kernel_lge_v500_20d_f2fs
C Header | 79 lines | 34 code | 12 blank | 33 comment | 6 complexity | 5f3c9d27b2a78c07465d4112224ab725 MD5 | raw file
 1/* To be include by pgtable-hash64.h only */
 2
 3/* Additional PTE bits (don't change without checking asm in hash_low.S) */
 4#define _PAGE_SPECIAL	0x00000400 /* software: special page */
 5#define _PAGE_HPTE_SUB	0x0ffff000 /* combo only: sub pages HPTE bits */
 6#define _PAGE_HPTE_SUB0	0x08000000 /* combo only: first sub page */
 7#define _PAGE_COMBO	0x10000000 /* this is a combo 4k page */
 8#define _PAGE_4K_PFN	0x20000000 /* PFN is for a single 4k page */
 9
10/* For 64K page, we don't have a separate _PAGE_HASHPTE bit. Instead,
11 * we set that to be the whole sub-bits mask. The C code will only
12 * test this, so a multi-bit mask will work. For combo pages, this
13 * is equivalent as effectively, the old _PAGE_HASHPTE was an OR of
14 * all the sub bits. For real 64k pages, we now have the assembly set
15 * _PAGE_HPTE_SUB0 in addition to setting the HIDX bits which overlap
16 * that mask. This is fine as long as the HIDX bits are never set on
17 * a PTE that isn't hashed, which is the case today.
18 *
19 * A little nit is for the huge page C code, which does the hashing
20 * in C, we need to provide which bit to use.
21 */
22#define _PAGE_HASHPTE	_PAGE_HPTE_SUB
23
24/* Note the full page bits must be in the same location as for normal
25 * 4k pages as the same assembly will be used to insert 64K pages
26 * wether the kernel has CONFIG_PPC_64K_PAGES or not
27 */
28#define _PAGE_F_SECOND  0x00008000 /* full page: hidx bits */
29#define _PAGE_F_GIX     0x00007000 /* full page: hidx bits */
30
31/* PTE flags to conserve for HPTE identification */
32#define _PAGE_HPTEFLAGS (_PAGE_BUSY | _PAGE_HASHPTE | _PAGE_COMBO)
33
34/* Shift to put page number into pte.
35 *
36 * That gives us a max RPN of 34 bits, which means a max of 50 bits
37 * of addressable physical space, or 46 bits for the special 4k PFNs.
38 */
39#define PTE_RPN_SHIFT	(30)
40
41#ifndef __ASSEMBLY__
42
43/*
44 * With 64K pages on hash table, we have a special PTE format that
45 * uses a second "half" of the page table to encode sub-page information
46 * in order to deal with 64K made of 4K HW pages. Thus we override the
47 * generic accessors and iterators here
48 */
49#define __real_pte(e,p) 	((real_pte_t) { \
50			(e), ((e) & _PAGE_COMBO) ? \
51				(pte_val(*((p) + PTRS_PER_PTE))) : 0 })
52#define __rpte_to_hidx(r,index)	((pte_val((r).pte) & _PAGE_COMBO) ? \
53        (((r).hidx >> ((index)<<2)) & 0xf) : ((pte_val((r).pte) >> 12) & 0xf))
54#define __rpte_to_pte(r)	((r).pte)
55#define __rpte_sub_valid(rpte, index) \
56	(pte_val(rpte.pte) & (_PAGE_HPTE_SUB0 >> (index)))
57
58/* Trick: we set __end to va + 64k, which happens works for
59 * a 16M page as well as we want only one iteration
60 */
61#define pte_iterate_hashed_subpages(rpte, psize, va, index, shift)	    \
62        do {                                                                \
63                unsigned long __end = va + PAGE_SIZE;                       \
64                unsigned __split = (psize == MMU_PAGE_4K ||                 \
65				    psize == MMU_PAGE_64K_AP);              \
66                shift = mmu_psize_defs[psize].shift;                        \
67		for (index = 0; va < __end; index++, va += (1L << shift)) { \
68		        if (!__split || __rpte_sub_valid(rpte, index)) do { \
69
70#define pte_iterate_hashed_end() } while(0); } } while(0)
71
72#define pte_pagesize_index(mm, addr, pte)	\
73	(((pte) & _PAGE_COMBO)? MMU_PAGE_4K: MMU_PAGE_64K)
74
75#define remap_4k_pfn(vma, addr, pfn, prot)				\
76	remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE,		\
77			__pgprot(pgprot_val((prot)) | _PAGE_4K_PFN))
78
79#endif	/* __ASSEMBLY__ */