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/arch/powerpc/include/asm/qe.h

https://github.com/aicjofs/android_kernel_lge_v500_20d_f2fs
C Header | 739 lines | 588 code | 61 blank | 90 comment | 1 complexity | 73ce0aa82f1fc9aecc4116b470f7dd83 MD5 | raw file
  1/*
  2 * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
  3 *
  4 * Authors: 	Shlomi Gridish <gridish@freescale.com>
  5 * 		Li Yang <leoli@freescale.com>
  6 *
  7 * Description:
  8 * QUICC Engine (QE) external definitions and structure.
  9 *
 10 * This program is free software; you can redistribute  it and/or modify it
 11 * under  the terms of  the GNU General  Public License as published by the
 12 * Free Software Foundation;  either version 2 of the  License, or (at your
 13 * option) any later version.
 14 */
 15#ifndef _ASM_POWERPC_QE_H
 16#define _ASM_POWERPC_QE_H
 17#ifdef __KERNEL__
 18
 19#include <linux/spinlock.h>
 20#include <linux/errno.h>
 21#include <linux/err.h>
 22#include <asm/cpm.h>
 23#include <asm/immap_qe.h>
 24
 25#define QE_NUM_OF_SNUM	256	/* There are 256 serial number in QE */
 26#define QE_NUM_OF_BRGS	16
 27#define QE_NUM_OF_PORTS	1024
 28
 29/* Memory partitions
 30*/
 31#define MEM_PART_SYSTEM		0
 32#define MEM_PART_SECONDARY	1
 33#define MEM_PART_MURAM		2
 34
 35/* Clocks and BRGs */
 36enum qe_clock {
 37	QE_CLK_NONE = 0,
 38	QE_BRG1,		/* Baud Rate Generator 1 */
 39	QE_BRG2,		/* Baud Rate Generator 2 */
 40	QE_BRG3,		/* Baud Rate Generator 3 */
 41	QE_BRG4,		/* Baud Rate Generator 4 */
 42	QE_BRG5,		/* Baud Rate Generator 5 */
 43	QE_BRG6,		/* Baud Rate Generator 6 */
 44	QE_BRG7,		/* Baud Rate Generator 7 */
 45	QE_BRG8,		/* Baud Rate Generator 8 */
 46	QE_BRG9,		/* Baud Rate Generator 9 */
 47	QE_BRG10,		/* Baud Rate Generator 10 */
 48	QE_BRG11,		/* Baud Rate Generator 11 */
 49	QE_BRG12,		/* Baud Rate Generator 12 */
 50	QE_BRG13,		/* Baud Rate Generator 13 */
 51	QE_BRG14,		/* Baud Rate Generator 14 */
 52	QE_BRG15,		/* Baud Rate Generator 15 */
 53	QE_BRG16,		/* Baud Rate Generator 16 */
 54	QE_CLK1,		/* Clock 1 */
 55	QE_CLK2,		/* Clock 2 */
 56	QE_CLK3,		/* Clock 3 */
 57	QE_CLK4,		/* Clock 4 */
 58	QE_CLK5,		/* Clock 5 */
 59	QE_CLK6,		/* Clock 6 */
 60	QE_CLK7,		/* Clock 7 */
 61	QE_CLK8,		/* Clock 8 */
 62	QE_CLK9,		/* Clock 9 */
 63	QE_CLK10,		/* Clock 10 */
 64	QE_CLK11,		/* Clock 11 */
 65	QE_CLK12,		/* Clock 12 */
 66	QE_CLK13,		/* Clock 13 */
 67	QE_CLK14,		/* Clock 14 */
 68	QE_CLK15,		/* Clock 15 */
 69	QE_CLK16,		/* Clock 16 */
 70	QE_CLK17,		/* Clock 17 */
 71	QE_CLK18,		/* Clock 18 */
 72	QE_CLK19,		/* Clock 19 */
 73	QE_CLK20,		/* Clock 20 */
 74	QE_CLK21,		/* Clock 21 */
 75	QE_CLK22,		/* Clock 22 */
 76	QE_CLK23,		/* Clock 23 */
 77	QE_CLK24,		/* Clock 24 */
 78	QE_CLK_DUMMY
 79};
 80
 81static inline bool qe_clock_is_brg(enum qe_clock clk)
 82{
 83	return clk >= QE_BRG1 && clk <= QE_BRG16;
 84}
 85
 86extern spinlock_t cmxgcr_lock;
 87
 88/* Export QE common operations */
 89#ifdef CONFIG_QUICC_ENGINE
 90extern void qe_reset(void);
 91#else
 92static inline void qe_reset(void) {}
 93#endif
 94
 95/* QE PIO */
 96#define QE_PIO_PINS 32
 97
 98struct qe_pio_regs {
 99	__be32	cpodr;		/* Open drain register */
100	__be32	cpdata;		/* Data register */
101	__be32	cpdir1;		/* Direction register */
102	__be32	cpdir2;		/* Direction register */
103	__be32	cppar1;		/* Pin assignment register */
104	__be32	cppar2;		/* Pin assignment register */
105#ifdef CONFIG_PPC_85xx
106	u8	pad[8];
107#endif
108};
109
110#define QE_PIO_DIR_IN	2
111#define QE_PIO_DIR_OUT	1
112extern void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin,
113				int dir, int open_drain, int assignment,
114				int has_irq);
115#ifdef CONFIG_QUICC_ENGINE
116extern int par_io_init(struct device_node *np);
117extern int par_io_of_config(struct device_node *np);
118extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
119			     int assignment, int has_irq);
120extern int par_io_data_set(u8 port, u8 pin, u8 val);
121#else
122static inline int par_io_init(struct device_node *np) { return -ENOSYS; }
123static inline int par_io_of_config(struct device_node *np) { return -ENOSYS; }
124static inline int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
125		int assignment, int has_irq) { return -ENOSYS; }
126static inline int par_io_data_set(u8 port, u8 pin, u8 val) { return -ENOSYS; }
127#endif /* CONFIG_QUICC_ENGINE */
128
129/*
130 * Pin multiplexing functions.
131 */
132struct qe_pin;
133#ifdef CONFIG_QE_GPIO
134extern struct qe_pin *qe_pin_request(struct device_node *np, int index);
135extern void qe_pin_free(struct qe_pin *qe_pin);
136extern void qe_pin_set_gpio(struct qe_pin *qe_pin);
137extern void qe_pin_set_dedicated(struct qe_pin *pin);
138#else
139static inline struct qe_pin *qe_pin_request(struct device_node *np, int index)
140{
141	return ERR_PTR(-ENOSYS);
142}
143static inline void qe_pin_free(struct qe_pin *qe_pin) {}
144static inline void qe_pin_set_gpio(struct qe_pin *qe_pin) {}
145static inline void qe_pin_set_dedicated(struct qe_pin *pin) {}
146#endif /* CONFIG_QE_GPIO */
147
148#ifdef CONFIG_QUICC_ENGINE
149int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input);
150#else
151static inline int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol,
152			       u32 cmd_input)
153{
154	return -ENOSYS;
155}
156#endif /* CONFIG_QUICC_ENGINE */
157
158/* QE internal API */
159enum qe_clock qe_clock_source(const char *source);
160unsigned int qe_get_brg_clk(void);
161int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier);
162int qe_get_snum(void);
163void qe_put_snum(u8 snum);
164unsigned int qe_get_num_of_risc(void);
165unsigned int qe_get_num_of_snums(void);
166
167static inline int qe_alive_during_sleep(void)
168{
169	/*
170	 * MPC8568E reference manual says:
171	 *
172	 * "...power down sequence waits for all I/O interfaces to become idle.
173	 *  In some applications this may happen eventually without actively
174	 *  shutting down interfaces, but most likely, software will have to
175	 *  take steps to shut down the eTSEC, QUICC Engine Block, and PCI
176	 *  interfaces before issuing the command (either the write to the core
177	 *  MSR[WE] as described above or writing to POWMGTCSR) to put the
178	 *  device into sleep state."
179	 *
180	 * MPC8569E reference manual has a similar paragraph.
181	 */
182#ifdef CONFIG_PPC_85xx
183	return 0;
184#else
185	return 1;
186#endif
187}
188
189/* we actually use cpm_muram implementation, define this for convenience */
190#define qe_muram_init cpm_muram_init
191#define qe_muram_alloc cpm_muram_alloc
192#define qe_muram_alloc_fixed cpm_muram_alloc_fixed
193#define qe_muram_free cpm_muram_free
194#define qe_muram_addr cpm_muram_addr
195#define qe_muram_offset cpm_muram_offset
196
197/* Structure that defines QE firmware binary files.
198 *
199 * See Documentation/powerpc/qe_firmware.txt for a description of these
200 * fields.
201 */
202struct qe_firmware {
203	struct qe_header {
204		__be32 length;  /* Length of the entire structure, in bytes */
205		u8 magic[3];    /* Set to { 'Q', 'E', 'F' } */
206		u8 version;     /* Version of this layout. First ver is '1' */
207	} header;
208	u8 id[62];      /* Null-terminated identifier string */
209	u8 split;	/* 0 = shared I-RAM, 1 = split I-RAM */
210	u8 count;       /* Number of microcode[] structures */
211	struct {
212		__be16 model;   	/* The SOC model  */
213		u8 major;       	/* The SOC revision major */
214		u8 minor;       	/* The SOC revision minor */
215	} __attribute__ ((packed)) soc;
216	u8 padding[4];			/* Reserved, for alignment */
217	__be64 extended_modes;		/* Extended modes */
218	__be32 vtraps[8];		/* Virtual trap addresses */
219	u8 reserved[4];			/* Reserved, for future expansion */
220	struct qe_microcode {
221		u8 id[32];      	/* Null-terminated identifier */
222		__be32 traps[16];       /* Trap addresses, 0 == ignore */
223		__be32 eccr;    	/* The value for the ECCR register */
224		__be32 iram_offset;     /* Offset into I-RAM for the code */
225		__be32 count;   	/* Number of 32-bit words of the code */
226		__be32 code_offset;     /* Offset of the actual microcode */
227		u8 major;       	/* The microcode version major */
228		u8 minor;       	/* The microcode version minor */
229		u8 revision;		/* The microcode version revision */
230		u8 padding;		/* Reserved, for alignment */
231		u8 reserved[4];		/* Reserved, for future expansion */
232	} __attribute__ ((packed)) microcode[1];
233	/* All microcode binaries should be located here */
234	/* CRC32 should be located here, after the microcode binaries */
235} __attribute__ ((packed));
236
237struct qe_firmware_info {
238	char id[64];		/* Firmware name */
239	u32 vtraps[8];		/* Virtual trap addresses */
240	u64 extended_modes;	/* Extended modes */
241};
242
243#ifdef CONFIG_QUICC_ENGINE
244/* Upload a firmware to the QE */
245int qe_upload_firmware(const struct qe_firmware *firmware);
246#else
247static inline int qe_upload_firmware(const struct qe_firmware *firmware)
248{
249	return -ENOSYS;
250}
251#endif /* CONFIG_QUICC_ENGINE */
252
253/* Obtain information on the uploaded firmware */
254struct qe_firmware_info *qe_get_firmware_info(void);
255
256/* QE USB */
257int qe_usb_clock_set(enum qe_clock clk, int rate);
258
259/* Buffer descriptors */
260struct qe_bd {
261	__be16 status;
262	__be16 length;
263	__be32 buf;
264} __attribute__ ((packed));
265
266#define BD_STATUS_MASK	0xffff0000
267#define BD_LENGTH_MASK	0x0000ffff
268
269/* Alignment */
270#define QE_INTR_TABLE_ALIGN	16	/* ??? */
271#define QE_ALIGNMENT_OF_BD	8
272#define QE_ALIGNMENT_OF_PRAM	64
273
274/* RISC allocation */
275#define QE_RISC_ALLOCATION_RISC1	0x1  /* RISC 1 */
276#define QE_RISC_ALLOCATION_RISC2	0x2  /* RISC 2 */
277#define QE_RISC_ALLOCATION_RISC3	0x4  /* RISC 3 */
278#define QE_RISC_ALLOCATION_RISC4	0x8  /* RISC 4 */
279#define QE_RISC_ALLOCATION_RISC1_AND_RISC2	(QE_RISC_ALLOCATION_RISC1 | \
280						 QE_RISC_ALLOCATION_RISC2)
281#define QE_RISC_ALLOCATION_FOUR_RISCS	(QE_RISC_ALLOCATION_RISC1 | \
282					 QE_RISC_ALLOCATION_RISC2 | \
283					 QE_RISC_ALLOCATION_RISC3 | \
284					 QE_RISC_ALLOCATION_RISC4)
285
286/* QE extended filtering Table Lookup Key Size */
287enum qe_fltr_tbl_lookup_key_size {
288	QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES
289		= 0x3f,		/* LookupKey parsed by the Generate LookupKey
290				   CMD is truncated to 8 bytes */
291	QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES
292		= 0x5f,		/* LookupKey parsed by the Generate LookupKey
293				   CMD is truncated to 16 bytes */
294};
295
296/* QE FLTR extended filtering Largest External Table Lookup Key Size */
297enum qe_fltr_largest_external_tbl_lookup_key_size {
298	QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE
299		= 0x0,/* not used */
300	QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES
301		= QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES,	/* 8 bytes */
302	QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES
303		= QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES,	/* 16 bytes */
304};
305
306/* structure representing QE parameter RAM */
307struct qe_timer_tables {
308	u16 tm_base;		/* QE timer table base adr */
309	u16 tm_ptr;		/* QE timer table pointer */
310	u16 r_tmr;		/* QE timer mode register */
311	u16 r_tmv;		/* QE timer valid register */
312	u32 tm_cmd;		/* QE timer cmd register */
313	u32 tm_cnt;		/* QE timer internal cnt */
314} __attribute__ ((packed));
315
316#define QE_FLTR_TAD_SIZE	8
317
318/* QE extended filtering Termination Action Descriptor (TAD) */
319struct qe_fltr_tad {
320	u8 serialized[QE_FLTR_TAD_SIZE];
321} __attribute__ ((packed));
322
323/* Communication Direction */
324enum comm_dir {
325	COMM_DIR_NONE = 0,
326	COMM_DIR_RX = 1,
327	COMM_DIR_TX = 2,
328	COMM_DIR_RX_AND_TX = 3
329};
330
331/* QE CMXUCR Registers.
332 * There are two UCCs represented in each of the four CMXUCR registers.
333 * These values are for the UCC in the LSBs
334 */
335#define QE_CMXUCR_MII_ENET_MNG		0x00007000
336#define QE_CMXUCR_MII_ENET_MNG_SHIFT	12
337#define QE_CMXUCR_GRANT			0x00008000
338#define QE_CMXUCR_TSA			0x00004000
339#define QE_CMXUCR_BKPT			0x00000100
340#define QE_CMXUCR_TX_CLK_SRC_MASK	0x0000000F
341
342/* QE CMXGCR Registers.
343*/
344#define QE_CMXGCR_MII_ENET_MNG		0x00007000
345#define QE_CMXGCR_MII_ENET_MNG_SHIFT	12
346#define QE_CMXGCR_USBCS			0x0000000f
347#define QE_CMXGCR_USBCS_CLK3		0x1
348#define QE_CMXGCR_USBCS_CLK5		0x2
349#define QE_CMXGCR_USBCS_CLK7		0x3
350#define QE_CMXGCR_USBCS_CLK9		0x4
351#define QE_CMXGCR_USBCS_CLK13		0x5
352#define QE_CMXGCR_USBCS_CLK17		0x6
353#define QE_CMXGCR_USBCS_CLK19		0x7
354#define QE_CMXGCR_USBCS_CLK21		0x8
355#define QE_CMXGCR_USBCS_BRG9		0x9
356#define QE_CMXGCR_USBCS_BRG10		0xa
357
358/* QE CECR Commands.
359*/
360#define QE_CR_FLG			0x00010000
361#define QE_RESET			0x80000000
362#define QE_INIT_TX_RX			0x00000000
363#define QE_INIT_RX			0x00000001
364#define QE_INIT_TX			0x00000002
365#define QE_ENTER_HUNT_MODE		0x00000003
366#define QE_STOP_TX			0x00000004
367#define QE_GRACEFUL_STOP_TX		0x00000005
368#define QE_RESTART_TX			0x00000006
369#define QE_CLOSE_RX_BD			0x00000007
370#define QE_SWITCH_COMMAND		0x00000007
371#define QE_SET_GROUP_ADDRESS		0x00000008
372#define QE_START_IDMA			0x00000009
373#define QE_MCC_STOP_RX			0x00000009
374#define QE_ATM_TRANSMIT			0x0000000a
375#define QE_HPAC_CLEAR_ALL		0x0000000b
376#define QE_GRACEFUL_STOP_RX		0x0000001a
377#define QE_RESTART_RX			0x0000001b
378#define QE_HPAC_SET_PRIORITY		0x0000010b
379#define QE_HPAC_STOP_TX			0x0000020b
380#define QE_HPAC_STOP_RX			0x0000030b
381#define QE_HPAC_GRACEFUL_STOP_TX	0x0000040b
382#define QE_HPAC_GRACEFUL_STOP_RX	0x0000050b
383#define QE_HPAC_START_TX		0x0000060b
384#define QE_HPAC_START_RX		0x0000070b
385#define QE_USB_STOP_TX			0x0000000a
386#define QE_USB_RESTART_TX		0x0000000c
387#define QE_QMC_STOP_TX			0x0000000c
388#define QE_QMC_STOP_RX			0x0000000d
389#define QE_SS7_SU_FIL_RESET		0x0000000e
390/* jonathbr added from here down for 83xx */
391#define QE_RESET_BCS			0x0000000a
392#define QE_MCC_INIT_TX_RX_16		0x00000003
393#define QE_MCC_STOP_TX			0x00000004
394#define QE_MCC_INIT_TX_1		0x00000005
395#define QE_MCC_INIT_RX_1		0x00000006
396#define QE_MCC_RESET			0x00000007
397#define QE_SET_TIMER			0x00000008
398#define QE_RANDOM_NUMBER		0x0000000c
399#define QE_ATM_MULTI_THREAD_INIT	0x00000011
400#define QE_ASSIGN_PAGE			0x00000012
401#define QE_ADD_REMOVE_HASH_ENTRY	0x00000013
402#define QE_START_FLOW_CONTROL		0x00000014
403#define QE_STOP_FLOW_CONTROL		0x00000015
404#define QE_ASSIGN_PAGE_TO_DEVICE	0x00000016
405
406#define QE_ASSIGN_RISC			0x00000010
407#define QE_CR_MCN_NORMAL_SHIFT		6
408#define QE_CR_MCN_USB_SHIFT		4
409#define QE_CR_MCN_RISC_ASSIGN_SHIFT	8
410#define QE_CR_SNUM_SHIFT		17
411
412/* QE CECR Sub Block - sub block of QE command.
413*/
414#define QE_CR_SUBBLOCK_INVALID		0x00000000
415#define QE_CR_SUBBLOCK_USB		0x03200000
416#define QE_CR_SUBBLOCK_UCCFAST1		0x02000000
417#define QE_CR_SUBBLOCK_UCCFAST2		0x02200000
418#define QE_CR_SUBBLOCK_UCCFAST3		0x02400000
419#define QE_CR_SUBBLOCK_UCCFAST4		0x02600000
420#define QE_CR_SUBBLOCK_UCCFAST5		0x02800000
421#define QE_CR_SUBBLOCK_UCCFAST6		0x02a00000
422#define QE_CR_SUBBLOCK_UCCFAST7		0x02c00000
423#define QE_CR_SUBBLOCK_UCCFAST8		0x02e00000
424#define QE_CR_SUBBLOCK_UCCSLOW1		0x00000000
425#define QE_CR_SUBBLOCK_UCCSLOW2		0x00200000
426#define QE_CR_SUBBLOCK_UCCSLOW3		0x00400000
427#define QE_CR_SUBBLOCK_UCCSLOW4		0x00600000
428#define QE_CR_SUBBLOCK_UCCSLOW5		0x00800000
429#define QE_CR_SUBBLOCK_UCCSLOW6		0x00a00000
430#define QE_CR_SUBBLOCK_UCCSLOW7		0x00c00000
431#define QE_CR_SUBBLOCK_UCCSLOW8		0x00e00000
432#define QE_CR_SUBBLOCK_MCC1		0x03800000
433#define QE_CR_SUBBLOCK_MCC2		0x03a00000
434#define QE_CR_SUBBLOCK_MCC3		0x03000000
435#define QE_CR_SUBBLOCK_IDMA1		0x02800000
436#define QE_CR_SUBBLOCK_IDMA2		0x02a00000
437#define QE_CR_SUBBLOCK_IDMA3		0x02c00000
438#define QE_CR_SUBBLOCK_IDMA4		0x02e00000
439#define QE_CR_SUBBLOCK_HPAC		0x01e00000
440#define QE_CR_SUBBLOCK_SPI1		0x01400000
441#define QE_CR_SUBBLOCK_SPI2		0x01600000
442#define QE_CR_SUBBLOCK_RAND		0x01c00000
443#define QE_CR_SUBBLOCK_TIMER		0x01e00000
444#define QE_CR_SUBBLOCK_GENERAL		0x03c00000
445
446/* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command */
447#define QE_CR_PROTOCOL_UNSPECIFIED	0x00	/* For all other protocols */
448#define QE_CR_PROTOCOL_HDLC_TRANSPARENT	0x00
449#define QE_CR_PROTOCOL_QMC		0x02
450#define QE_CR_PROTOCOL_UART		0x04
451#define QE_CR_PROTOCOL_ATM_POS		0x0A
452#define QE_CR_PROTOCOL_ETHERNET		0x0C
453#define QE_CR_PROTOCOL_L2_SWITCH	0x0D
454
455/* BRG configuration register */
456#define QE_BRGC_ENABLE		0x00010000
457#define QE_BRGC_DIVISOR_SHIFT	1
458#define QE_BRGC_DIVISOR_MAX	0xFFF
459#define QE_BRGC_DIV16		1
460
461/* QE Timers registers */
462#define QE_GTCFR1_PCAS	0x80
463#define QE_GTCFR1_STP2	0x20
464#define QE_GTCFR1_RST2	0x10
465#define QE_GTCFR1_GM2	0x08
466#define QE_GTCFR1_GM1	0x04
467#define QE_GTCFR1_STP1	0x02
468#define QE_GTCFR1_RST1	0x01
469
470/* SDMA registers */
471#define QE_SDSR_BER1	0x02000000
472#define QE_SDSR_BER2	0x01000000
473
474#define QE_SDMR_GLB_1_MSK	0x80000000
475#define QE_SDMR_ADR_SEL		0x20000000
476#define QE_SDMR_BER1_MSK	0x02000000
477#define QE_SDMR_BER2_MSK	0x01000000
478#define QE_SDMR_EB1_MSK		0x00800000
479#define QE_SDMR_ER1_MSK		0x00080000
480#define QE_SDMR_ER2_MSK		0x00040000
481#define QE_SDMR_CEN_MASK	0x0000E000
482#define QE_SDMR_SBER_1		0x00000200
483#define QE_SDMR_SBER_2		0x00000200
484#define QE_SDMR_EB1_PR_MASK	0x000000C0
485#define QE_SDMR_ER1_PR		0x00000008
486
487#define QE_SDMR_CEN_SHIFT	13
488#define QE_SDMR_EB1_PR_SHIFT	6
489
490#define QE_SDTM_MSNUM_SHIFT	24
491
492#define QE_SDEBCR_BA_MASK	0x01FFFFFF
493
494/* Communication Processor */
495#define QE_CP_CERCR_MEE		0x8000	/* Multi-user RAM ECC enable */
496#define QE_CP_CERCR_IEE		0x4000	/* Instruction RAM ECC enable */
497#define QE_CP_CERCR_CIR		0x0800	/* Common instruction RAM */
498
499/* I-RAM */
500#define QE_IRAM_IADD_AIE	0x80000000	/* Auto Increment Enable */
501#define QE_IRAM_IADD_BADDR	0x00080000	/* Base Address */
502
503/* UPC */
504#define UPGCR_PROTOCOL	0x80000000	/* protocol ul2 or pl2 */
505#define UPGCR_TMS	0x40000000	/* Transmit master/slave mode */
506#define UPGCR_RMS	0x20000000	/* Receive master/slave mode */
507#define UPGCR_ADDR	0x10000000	/* Master MPHY Addr multiplexing */
508#define UPGCR_DIAG	0x01000000	/* Diagnostic mode */
509
510/* UCC GUEMR register */
511#define UCC_GUEMR_MODE_MASK_RX	0x02
512#define UCC_GUEMR_MODE_FAST_RX	0x02
513#define UCC_GUEMR_MODE_SLOW_RX	0x00
514#define UCC_GUEMR_MODE_MASK_TX	0x01
515#define UCC_GUEMR_MODE_FAST_TX	0x01
516#define UCC_GUEMR_MODE_SLOW_TX	0x00
517#define UCC_GUEMR_MODE_MASK (UCC_GUEMR_MODE_MASK_RX | UCC_GUEMR_MODE_MASK_TX)
518#define UCC_GUEMR_SET_RESERVED3	0x10	/* Bit 3 in the guemr is reserved but
519					   must be set 1 */
520
521/* structure representing UCC SLOW parameter RAM */
522struct ucc_slow_pram {
523	__be16 rbase;		/* RX BD base address */
524	__be16 tbase;		/* TX BD base address */
525	u8 rbmr;		/* RX bus mode register (same as CPM's RFCR) */
526	u8 tbmr;		/* TX bus mode register (same as CPM's TFCR) */
527	__be16 mrblr;		/* Rx buffer length */
528	__be32 rstate;		/* Rx internal state */
529	__be32 rptr;		/* Rx internal data pointer */
530	__be16 rbptr;		/* rb BD Pointer */
531	__be16 rcount;		/* Rx internal byte count */
532	__be32 rtemp;		/* Rx temp */
533	__be32 tstate;		/* Tx internal state */
534	__be32 tptr;		/* Tx internal data pointer */
535	__be16 tbptr;		/* Tx BD pointer */
536	__be16 tcount;		/* Tx byte count */
537	__be32 ttemp;		/* Tx temp */
538	__be32 rcrc;		/* temp receive CRC */
539	__be32 tcrc;		/* temp transmit CRC */
540} __attribute__ ((packed));
541
542/* General UCC SLOW Mode Register (GUMRH & GUMRL) */
543#define UCC_SLOW_GUMR_H_SAM_QMC		0x00000000
544#define UCC_SLOW_GUMR_H_SAM_SATM	0x00008000
545#define UCC_SLOW_GUMR_H_REVD		0x00002000
546#define UCC_SLOW_GUMR_H_TRX		0x00001000
547#define UCC_SLOW_GUMR_H_TTX		0x00000800
548#define UCC_SLOW_GUMR_H_CDP		0x00000400
549#define UCC_SLOW_GUMR_H_CTSP		0x00000200
550#define UCC_SLOW_GUMR_H_CDS		0x00000100
551#define UCC_SLOW_GUMR_H_CTSS		0x00000080
552#define UCC_SLOW_GUMR_H_TFL		0x00000040
553#define UCC_SLOW_GUMR_H_RFW		0x00000020
554#define UCC_SLOW_GUMR_H_TXSY		0x00000010
555#define UCC_SLOW_GUMR_H_4SYNC		0x00000004
556#define UCC_SLOW_GUMR_H_8SYNC		0x00000008
557#define UCC_SLOW_GUMR_H_16SYNC		0x0000000c
558#define UCC_SLOW_GUMR_H_RTSM		0x00000002
559#define UCC_SLOW_GUMR_H_RSYN		0x00000001
560
561#define UCC_SLOW_GUMR_L_TCI		0x10000000
562#define UCC_SLOW_GUMR_L_RINV		0x02000000
563#define UCC_SLOW_GUMR_L_TINV		0x01000000
564#define UCC_SLOW_GUMR_L_TEND		0x00040000
565#define UCC_SLOW_GUMR_L_TDCR_MASK	0x00030000
566#define UCC_SLOW_GUMR_L_TDCR_32	        0x00030000
567#define UCC_SLOW_GUMR_L_TDCR_16	        0x00020000
568#define UCC_SLOW_GUMR_L_TDCR_8	        0x00010000
569#define UCC_SLOW_GUMR_L_TDCR_1	        0x00000000
570#define UCC_SLOW_GUMR_L_RDCR_MASK	0x0000c000
571#define UCC_SLOW_GUMR_L_RDCR_32		0x0000c000
572#define UCC_SLOW_GUMR_L_RDCR_16	        0x00008000
573#define UCC_SLOW_GUMR_L_RDCR_8	        0x00004000
574#define UCC_SLOW_GUMR_L_RDCR_1		0x00000000
575#define UCC_SLOW_GUMR_L_RENC_NRZI	0x00000800
576#define UCC_SLOW_GUMR_L_RENC_NRZ	0x00000000
577#define UCC_SLOW_GUMR_L_TENC_NRZI	0x00000100
578#define UCC_SLOW_GUMR_L_TENC_NRZ	0x00000000
579#define UCC_SLOW_GUMR_L_DIAG_MASK	0x000000c0
580#define UCC_SLOW_GUMR_L_DIAG_LE	        0x000000c0
581#define UCC_SLOW_GUMR_L_DIAG_ECHO	0x00000080
582#define UCC_SLOW_GUMR_L_DIAG_LOOP	0x00000040
583#define UCC_SLOW_GUMR_L_DIAG_NORM	0x00000000
584#define UCC_SLOW_GUMR_L_ENR		0x00000020
585#define UCC_SLOW_GUMR_L_ENT		0x00000010
586#define UCC_SLOW_GUMR_L_MODE_MASK	0x0000000F
587#define UCC_SLOW_GUMR_L_MODE_BISYNC	0x00000008
588#define UCC_SLOW_GUMR_L_MODE_AHDLC	0x00000006
589#define UCC_SLOW_GUMR_L_MODE_UART	0x00000004
590#define UCC_SLOW_GUMR_L_MODE_QMC	0x00000002
591
592/* General UCC FAST Mode Register */
593#define UCC_FAST_GUMR_TCI	0x20000000
594#define UCC_FAST_GUMR_TRX	0x10000000
595#define UCC_FAST_GUMR_TTX	0x08000000
596#define UCC_FAST_GUMR_CDP	0x04000000
597#define UCC_FAST_GUMR_CTSP	0x02000000
598#define UCC_FAST_GUMR_CDS	0x01000000
599#define UCC_FAST_GUMR_CTSS	0x00800000
600#define UCC_FAST_GUMR_TXSY	0x00020000
601#define UCC_FAST_GUMR_RSYN	0x00010000
602#define UCC_FAST_GUMR_RTSM	0x00002000
603#define UCC_FAST_GUMR_REVD	0x00000400
604#define UCC_FAST_GUMR_ENR	0x00000020
605#define UCC_FAST_GUMR_ENT	0x00000010
606
607/* UART Slow UCC Event Register (UCCE) */
608#define UCC_UART_UCCE_AB	0x0200
609#define UCC_UART_UCCE_IDLE	0x0100
610#define UCC_UART_UCCE_GRA	0x0080
611#define UCC_UART_UCCE_BRKE	0x0040
612#define UCC_UART_UCCE_BRKS	0x0020
613#define UCC_UART_UCCE_CCR	0x0008
614#define UCC_UART_UCCE_BSY	0x0004
615#define UCC_UART_UCCE_TX	0x0002
616#define UCC_UART_UCCE_RX	0x0001
617
618/* HDLC Slow UCC Event Register (UCCE) */
619#define UCC_HDLC_UCCE_GLR	0x1000
620#define UCC_HDLC_UCCE_GLT	0x0800
621#define UCC_HDLC_UCCE_IDLE	0x0100
622#define UCC_HDLC_UCCE_BRKE	0x0040
623#define UCC_HDLC_UCCE_BRKS	0x0020
624#define UCC_HDLC_UCCE_TXE	0x0010
625#define UCC_HDLC_UCCE_RXF	0x0008
626#define UCC_HDLC_UCCE_BSY	0x0004
627#define UCC_HDLC_UCCE_TXB	0x0002
628#define UCC_HDLC_UCCE_RXB	0x0001
629
630/* BISYNC Slow UCC Event Register (UCCE) */
631#define UCC_BISYNC_UCCE_GRA	0x0080
632#define UCC_BISYNC_UCCE_TXE	0x0010
633#define UCC_BISYNC_UCCE_RCH	0x0008
634#define UCC_BISYNC_UCCE_BSY	0x0004
635#define UCC_BISYNC_UCCE_TXB	0x0002
636#define UCC_BISYNC_UCCE_RXB	0x0001
637
638/* Gigabit Ethernet Fast UCC Event Register (UCCE) */
639#define UCC_GETH_UCCE_MPD       0x80000000
640#define UCC_GETH_UCCE_SCAR      0x40000000
641#define UCC_GETH_UCCE_GRA       0x20000000
642#define UCC_GETH_UCCE_CBPR      0x10000000
643#define UCC_GETH_UCCE_BSY       0x08000000
644#define UCC_GETH_UCCE_RXC       0x04000000
645#define UCC_GETH_UCCE_TXC       0x02000000
646#define UCC_GETH_UCCE_TXE       0x01000000
647#define UCC_GETH_UCCE_TXB7      0x00800000
648#define UCC_GETH_UCCE_TXB6      0x00400000
649#define UCC_GETH_UCCE_TXB5      0x00200000
650#define UCC_GETH_UCCE_TXB4      0x00100000
651#define UCC_GETH_UCCE_TXB3      0x00080000
652#define UCC_GETH_UCCE_TXB2      0x00040000
653#define UCC_GETH_UCCE_TXB1      0x00020000
654#define UCC_GETH_UCCE_TXB0      0x00010000
655#define UCC_GETH_UCCE_RXB7      0x00008000
656#define UCC_GETH_UCCE_RXB6      0x00004000
657#define UCC_GETH_UCCE_RXB5      0x00002000
658#define UCC_GETH_UCCE_RXB4      0x00001000
659#define UCC_GETH_UCCE_RXB3      0x00000800
660#define UCC_GETH_UCCE_RXB2      0x00000400
661#define UCC_GETH_UCCE_RXB1      0x00000200
662#define UCC_GETH_UCCE_RXB0      0x00000100
663#define UCC_GETH_UCCE_RXF7      0x00000080
664#define UCC_GETH_UCCE_RXF6      0x00000040
665#define UCC_GETH_UCCE_RXF5      0x00000020
666#define UCC_GETH_UCCE_RXF4      0x00000010
667#define UCC_GETH_UCCE_RXF3      0x00000008
668#define UCC_GETH_UCCE_RXF2      0x00000004
669#define UCC_GETH_UCCE_RXF1      0x00000002
670#define UCC_GETH_UCCE_RXF0      0x00000001
671
672/* UCC Protocol Specific Mode Register (UPSMR), when used for UART */
673#define UCC_UART_UPSMR_FLC		0x8000
674#define UCC_UART_UPSMR_SL		0x4000
675#define UCC_UART_UPSMR_CL_MASK		0x3000
676#define UCC_UART_UPSMR_CL_8		0x3000
677#define UCC_UART_UPSMR_CL_7		0x2000
678#define UCC_UART_UPSMR_CL_6		0x1000
679#define UCC_UART_UPSMR_CL_5		0x0000
680#define UCC_UART_UPSMR_UM_MASK		0x0c00
681#define UCC_UART_UPSMR_UM_NORMAL	0x0000
682#define UCC_UART_UPSMR_UM_MAN_MULTI	0x0400
683#define UCC_UART_UPSMR_UM_AUTO_MULTI	0x0c00
684#define UCC_UART_UPSMR_FRZ		0x0200
685#define UCC_UART_UPSMR_RZS		0x0100
686#define UCC_UART_UPSMR_SYN		0x0080
687#define UCC_UART_UPSMR_DRT		0x0040
688#define UCC_UART_UPSMR_PEN		0x0010
689#define UCC_UART_UPSMR_RPM_MASK		0x000c
690#define UCC_UART_UPSMR_RPM_ODD		0x0000
691#define UCC_UART_UPSMR_RPM_LOW		0x0004
692#define UCC_UART_UPSMR_RPM_EVEN		0x0008
693#define UCC_UART_UPSMR_RPM_HIGH		0x000C
694#define UCC_UART_UPSMR_TPM_MASK		0x0003
695#define UCC_UART_UPSMR_TPM_ODD		0x0000
696#define UCC_UART_UPSMR_TPM_LOW		0x0001
697#define UCC_UART_UPSMR_TPM_EVEN		0x0002
698#define UCC_UART_UPSMR_TPM_HIGH		0x0003
699
700/* UCC Protocol Specific Mode Register (UPSMR), when used for Ethernet */
701#define UCC_GETH_UPSMR_FTFE     0x80000000
702#define UCC_GETH_UPSMR_PTPE     0x40000000
703#define UCC_GETH_UPSMR_ECM      0x04000000
704#define UCC_GETH_UPSMR_HSE      0x02000000
705#define UCC_GETH_UPSMR_PRO      0x00400000
706#define UCC_GETH_UPSMR_CAP      0x00200000
707#define UCC_GETH_UPSMR_RSH      0x00100000
708#define UCC_GETH_UPSMR_RPM      0x00080000
709#define UCC_GETH_UPSMR_R10M     0x00040000
710#define UCC_GETH_UPSMR_RLPB     0x00020000
711#define UCC_GETH_UPSMR_TBIM     0x00010000
712#define UCC_GETH_UPSMR_RES1     0x00002000
713#define UCC_GETH_UPSMR_RMM      0x00001000
714#define UCC_GETH_UPSMR_CAM      0x00000400
715#define UCC_GETH_UPSMR_BRO      0x00000200
716#define UCC_GETH_UPSMR_SMM	0x00000080
717#define UCC_GETH_UPSMR_SGMM	0x00000020
718
719/* UCC Transmit On Demand Register (UTODR) */
720#define UCC_SLOW_TOD	0x8000
721#define UCC_FAST_TOD	0x8000
722
723/* UCC Bus Mode Register masks */
724/* Not to be confused with the Bundle Mode Register */
725#define UCC_BMR_GBL		0x20
726#define UCC_BMR_BO_BE		0x10
727#define UCC_BMR_CETM		0x04
728#define UCC_BMR_DTB		0x02
729#define UCC_BMR_BDB		0x01
730
731/* Function code masks */
732#define FC_GBL				0x20
733#define FC_DTB_LCL			0x02
734#define UCC_FAST_FUNCTION_CODE_GBL	0x20
735#define UCC_FAST_FUNCTION_CODE_DTB_LCL	0x02
736#define UCC_FAST_FUNCTION_CODE_BDB_LCL	0x01
737
738#endif /* __KERNEL__ */
739#endif /* _ASM_POWERPC_QE_H */