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/arch/powerpc/include/asm/reg_a2.h

https://github.com/aicjofs/android_kernel_lge_v500_20d
C Header | 165 lines | 121 code | 20 blank | 24 comment | 0 complexity | 64ff696979484785db51556bb9aa5fb0 MD5 | raw file
  1/*
  2 *  Register definitions specific to the A2 core
  3 *
  4 *  Copyright (C) 2008 Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp.
  5 *
  6 *  This program is free software; you can redistribute it and/or
  7 *  modify it under the terms of the GNU General Public License
  8 *  as published by the Free Software Foundation; either version
  9 *  2 of the License, or (at your option) any later version.
 10 */
 11
 12#ifndef __ASM_POWERPC_REG_A2_H__
 13#define __ASM_POWERPC_REG_A2_H__
 14
 15#define SPRN_TENSR	0x1b5
 16#define SPRN_TENS	0x1b6	/* Thread ENable Set */
 17#define SPRN_TENC	0x1b7	/* Thread ENable Clear */
 18
 19#define SPRN_A2_CCR0	0x3f0	/* Core Configuration Register 0 */
 20#define SPRN_A2_CCR1	0x3f1	/* Core Configuration Register 1 */
 21#define SPRN_A2_CCR2	0x3f2	/* Core Configuration Register 2 */
 22#define SPRN_MMUCR0	0x3fc	/* MMU Control Register 0 */
 23#define SPRN_MMUCR1	0x3fd	/* MMU Control Register 1 */
 24#define SPRN_MMUCR2	0x3fe	/* MMU Control Register 2 */
 25#define SPRN_MMUCR3	0x3ff	/* MMU Control Register 3 */
 26
 27#define SPRN_IAR	0x372
 28
 29#define SPRN_IUCR0	0x3f3
 30#define IUCR0_ICBI_ACK	0x1000
 31
 32#define SPRN_XUCR0	0x3f6	/* Execution Unit Config Register 0 */
 33
 34#define A2_IERAT_SIZE	16
 35#define A2_DERAT_SIZE	32
 36
 37/* A2 MMUCR0 bits */
 38#define MMUCR0_ECL	0x80000000	/* Extended Class for TLB fills */
 39#define MMUCR0_TID_NZ	0x40000000	/* TID is non-zero */
 40#define MMUCR0_TS	0x10000000	/* Translation space for TLB fills */
 41#define MMUCR0_TGS	0x20000000	/* Guest space for TLB fills */
 42#define MMUCR0_TLBSEL	0x0c000000	/* TLB or ERAT target for TLB fills */
 43#define MMUCR0_TLBSEL_U	0x00000000	/*  TLBSEL = UTLB */
 44#define MMUCR0_TLBSEL_I	0x08000000	/*  TLBSEL = I-ERAT */
 45#define MMUCR0_TLBSEL_D	0x0c000000	/*  TLBSEL = D-ERAT */
 46#define MMUCR0_LOCKSRSH	0x02000000	/* Use TLB lock on tlbsx. */
 47#define MMUCR0_TID_MASK	0x000000ff	/* TID field */
 48
 49/* A2 MMUCR1 bits */
 50#define MMUCR1_IRRE		0x80000000	/* I-ERAT round robin enable */
 51#define MMUCR1_DRRE		0x40000000	/* D-ERAT round robin enable */
 52#define MMUCR1_REE		0x20000000	/* Reference Exception Enable*/
 53#define MMUCR1_CEE		0x10000000	/* Change exception enable */
 54#define MMUCR1_CSINV_ALL	0x00000000	/* Inval ERAT on all CS evts */
 55#define MMUCR1_CSINV_NISYNC	0x04000000	/* Inval ERAT on all ex isync*/
 56#define MMUCR1_CSINV_NEVER	0x0c000000	/* Don't inval ERAT on CS */
 57#define MMUCR1_ICTID		0x00080000	/* IERAT class field as TID */
 58#define MMUCR1_ITTID		0x00040000	/* IERAT thdid field as TID */
 59#define MMUCR1_DCTID		0x00020000	/* DERAT class field as TID */
 60#define MMUCR1_DTTID		0x00010000	/* DERAT thdid field as TID */
 61#define MMUCR1_DCCD		0x00008000	/* DERAT class ignore */
 62#define MMUCR1_TLBWE_BINV	0x00004000	/* back invalidate on tlbwe */
 63
 64/* A2 MMUCR2 bits */
 65#define MMUCR2_PSSEL_SHIFT	4
 66
 67/* A2 MMUCR3 bits */
 68#define MMUCR3_THID		0x0000000f	/* Thread ID */
 69
 70/* *** ERAT TLB bits definitions */
 71#define TLB0_EPN_MASK		ASM_CONST(0xfffffffffffff000)
 72#define TLB0_CLASS_MASK		ASM_CONST(0x0000000000000c00)
 73#define TLB0_CLASS_00		ASM_CONST(0x0000000000000000)
 74#define TLB0_CLASS_01		ASM_CONST(0x0000000000000400)
 75#define TLB0_CLASS_10		ASM_CONST(0x0000000000000800)
 76#define TLB0_CLASS_11		ASM_CONST(0x0000000000000c00)
 77#define TLB0_V			ASM_CONST(0x0000000000000200)
 78#define TLB0_X			ASM_CONST(0x0000000000000100)
 79#define TLB0_SIZE_MASK		ASM_CONST(0x00000000000000f0)
 80#define TLB0_SIZE_4K		ASM_CONST(0x0000000000000010)
 81#define TLB0_SIZE_64K		ASM_CONST(0x0000000000000030)
 82#define TLB0_SIZE_1M		ASM_CONST(0x0000000000000050)
 83#define TLB0_SIZE_16M		ASM_CONST(0x0000000000000070)
 84#define TLB0_SIZE_1G		ASM_CONST(0x00000000000000a0)
 85#define TLB0_THDID_MASK		ASM_CONST(0x000000000000000f)
 86#define TLB0_THDID_0		ASM_CONST(0x0000000000000001)
 87#define TLB0_THDID_1		ASM_CONST(0x0000000000000002)
 88#define TLB0_THDID_2		ASM_CONST(0x0000000000000004)
 89#define TLB0_THDID_3		ASM_CONST(0x0000000000000008)
 90#define TLB0_THDID_ALL		ASM_CONST(0x000000000000000f)
 91
 92#define TLB1_RESVATTR		ASM_CONST(0x00f0000000000000)
 93#define TLB1_U0			ASM_CONST(0x0008000000000000)
 94#define TLB1_U1			ASM_CONST(0x0004000000000000)
 95#define TLB1_U2			ASM_CONST(0x0002000000000000)
 96#define TLB1_U3			ASM_CONST(0x0001000000000000)
 97#define TLB1_R			ASM_CONST(0x0000800000000000)
 98#define TLB1_C			ASM_CONST(0x0000400000000000)
 99#define TLB1_RPN_MASK		ASM_CONST(0x000003fffffff000)
100#define TLB1_W			ASM_CONST(0x0000000000000800)
101#define TLB1_I			ASM_CONST(0x0000000000000400)
102#define TLB1_M			ASM_CONST(0x0000000000000200)
103#define TLB1_G			ASM_CONST(0x0000000000000100)
104#define TLB1_E			ASM_CONST(0x0000000000000080)
105#define TLB1_VF			ASM_CONST(0x0000000000000040)
106#define TLB1_UX			ASM_CONST(0x0000000000000020)
107#define TLB1_SX			ASM_CONST(0x0000000000000010)
108#define TLB1_UW			ASM_CONST(0x0000000000000008)
109#define TLB1_SW			ASM_CONST(0x0000000000000004)
110#define TLB1_UR			ASM_CONST(0x0000000000000002)
111#define TLB1_SR			ASM_CONST(0x0000000000000001)
112
113#ifdef CONFIG_PPC_EARLY_DEBUG_WSP
114#define WSP_UART_PHYS	0xffc000c000
115/* This needs to be careful chosen to hit a !0 congruence class
116 * in the TLB since we bolt it in way 3, which is already occupied
117 * by our linear mapping primary bolted entry in CC 0.
118 */
119#define WSP_UART_VIRT	0xf000000000001000
120#endif
121
122/* A2 erativax attributes definitions */
123#define ERATIVAX_RS_IS_ALL		0x000
124#define ERATIVAX_RS_IS_TID		0x040
125#define ERATIVAX_RS_IS_CLASS		0x080
126#define ERATIVAX_RS_IS_FULLMATCH	0x0c0
127#define ERATIVAX_CLASS_00		0x000
128#define ERATIVAX_CLASS_01		0x010
129#define ERATIVAX_CLASS_10		0x020
130#define ERATIVAX_CLASS_11		0x030
131#define ERATIVAX_PSIZE_4K		(TLB_PSIZE_4K >> 1)
132#define ERATIVAX_PSIZE_64K		(TLB_PSIZE_64K >> 1)
133#define ERATIVAX_PSIZE_1M		(TLB_PSIZE_1M >> 1)
134#define ERATIVAX_PSIZE_16M		(TLB_PSIZE_16M >> 1)
135#define ERATIVAX_PSIZE_1G		(TLB_PSIZE_1G >> 1)
136
137/* A2 eratilx attributes definitions */
138#define ERATILX_T_ALL			0
139#define ERATILX_T_TID			1
140#define ERATILX_T_TGS			2
141#define ERATILX_T_FULLMATCH		3
142#define ERATILX_T_CLASS0		4
143#define ERATILX_T_CLASS1		5
144#define ERATILX_T_CLASS2		6
145#define ERATILX_T_CLASS3		7
146
147/* XUCR0 bits */
148#define XUCR0_TRACE_UM_T0		0x40000000	/* Thread 0 */
149#define XUCR0_TRACE_UM_T1		0x20000000	/* Thread 1 */
150#define XUCR0_TRACE_UM_T2		0x10000000	/* Thread 2 */
151#define XUCR0_TRACE_UM_T3		0x08000000	/* Thread 3 */
152
153/* A2 CCR0 register */
154#define A2_CCR0_PME_DISABLED		0x00000000
155#define A2_CCR0_PME_SLEEP		0x40000000
156#define A2_CCR0_PME_RVW			0x80000000
157#define A2_CCR0_PME_DISABLED2		0xc0000000
158
159/* A2 CCR2 register */
160#define A2_CCR2_ERAT_ONLY_MODE		0x00000001
161#define A2_CCR2_ENABLE_ICSWX		0x00000002
162#define A2_CCR2_ENABLE_PC		0x20000000
163#define A2_CCR2_ENABLE_TRACE		0x40000000
164
165#endif /* __ASM_POWERPC_REG_A2_H__ */