/gcc-reload-optional.patch

# · Patch · 679 lines · 674 code · 5 blank · 0 comment · 0 complexity · 2fd7fcf83975a0fa80a87413e46a66ab MD5 · raw file 

    

  1. 2001-11-12  Jakub Jelinek  <jakub@redhat.com>
    2. 

  2. 

  3. 	* reload.c (find_reloads): Emit USE resp. CLOBBER insns if not
    4. 

  4. 	pushing any reloads if needed.
    5. 

  5. 

  6. 	* gcc.dg/20011024-1.c: New test.
    7. 

  7. 

  8. --- gcc/reload.c.jj	Wed Oct 24 21:25:01 2001
    9. 

  9. +++ gcc/reload.c	Mon Nov 12 12:43:52 2001
    10. 

  10. @@ -3621,53 +3621,144 @@ find_reloads (insn, replace, ind_levels,
    11. 

  11.  
    12. 

  12.    /* Now record reloads for all the operands that need them.  */
    13. 

  13.    for (i = 0; i < noperands; i++)
    14. 

  14. -    if (! goal_alternative_win[i])
    15. 

  15. -      {
    16. 

  16. -	/* Operands that match previous ones have already been handled.  */
    17. 

  17. -	if (goal_alternative_matches[i] >= 0)
    18. 

  18. -	  ;
    19. 

  19. -	/* Handle an operand with a nonoffsettable address
    20. 

  20. -	   appearing where an offsettable address will do
    21. 

  21. -	   by reloading the address into a base register.
    22. 

  22. -
    23. 

  23. -	   ??? We can also do this when the operand is a register and
    24. 

  24. -	   reg_equiv_mem is not offsettable, but this is a bit tricky,
    25. 

  25. -	   so we don't bother with it.  It may not be worth doing.  */
    26. 

  26. -	else if (goal_alternative_matched[i] == -1
    27. 

  27. -		 && goal_alternative_offmemok[i]
    28. 

  28. -		 && GET_CODE (recog_data.operand[i]) == MEM)
    29. 

  29. -	  {
    30. 

  30. -	    operand_reloadnum[i]
    31. 

  31. -	      = push_reload (XEXP (recog_data.operand[i], 0), NULL_RTX,
    32. 

  32. -			     &XEXP (recog_data.operand[i], 0), NULL_PTR,
    33. 

  33. -			     BASE_REG_CLASS,
    34. 

  34. -			     GET_MODE (XEXP (recog_data.operand[i], 0)),
    35. 

  35. -			     VOIDmode, 0, 0, i, RELOAD_FOR_INPUT);
    36. 

  36. -	    rld[operand_reloadnum[i]].inc
    37. 

  37. -	      = GET_MODE_SIZE (GET_MODE (recog_data.operand[i]));
    38. 

  38. -
    39. 

  39. -	    /* If this operand is an output, we will have made any
    40. 

  40. -	       reloads for its address as RELOAD_FOR_OUTPUT_ADDRESS, but
    41. 

  41. -	       now we are treating part of the operand as an input, so
    42. 

  42. -	       we must change these to RELOAD_FOR_INPUT_ADDRESS.  */
    43. 

  43. -
    44. 

  44. -	    if (modified[i] == RELOAD_WRITE)
    45. 

  45. -	      {
    46. 

  46. -		for (j = 0; j < n_reloads; j++)
    47. 

  47. -		  {
    48. 

  48. -		    if (rld[j].opnum == i)
    49. 

  49. -		      {
    50. 

  50. -			if (rld[j].when_needed == RELOAD_FOR_OUTPUT_ADDRESS)
    51. 

  51. -			  rld[j].when_needed = RELOAD_FOR_INPUT_ADDRESS;
    52. 

  52. -			else if (rld[j].when_needed
    53. 

  53. -				 == RELOAD_FOR_OUTADDR_ADDRESS)
    54. 

  54. -			  rld[j].when_needed = RELOAD_FOR_INPADDR_ADDRESS;
    55. 

  55. -		      }
    56. 

  56. -		  }
    57. 

  57. -	      }
    58. 

  58. -	  }
    59. 

  59. -	else if (goal_alternative_matched[i] == -1)
    60. 

  60. -	  {
    61. 

  61. +    {
    62. 

  62. +      if (! goal_alternative_win[i])
    63. 

  63. +	{
    64. 

  64. +	  /* Operands that match previous ones have already been handled.  */
    65. 

  65. +	  if (goal_alternative_matches[i] >= 0)
    66. 

  66. +	    ;
    67. 

  67. +	  /* Handle an operand with a nonoffsettable address
    68. 

  68. +	     appearing where an offsettable address will do
    69. 

  69. +	     by reloading the address into a base register.
    70. 

  70. +
    71. 

  71. +	     ??? We can also do this when the operand is a register and
    72. 

  72. +	     reg_equiv_mem is not offsettable, but this is a bit tricky,
    73. 

  73. +	     so we don't bother with it.  It may not be worth doing.  */
    74. 

  74. +	  else if (goal_alternative_matched[i] == -1
    75. 

  75. +		   && goal_alternative_offmemok[i]
    76. 

  76. +		   && GET_CODE (recog_data.operand[i]) == MEM)
    77. 

  77. +	    {
    78. 

  78. +	      operand_reloadnum[i]
    79. 

  79. +		= push_reload (XEXP (recog_data.operand[i], 0), NULL_RTX,
    80. 

  80. +			       &XEXP (recog_data.operand[i], 0), NULL_PTR,
    81. 

  81. +			       BASE_REG_CLASS,
    82. 

  82. +			       GET_MODE (XEXP (recog_data.operand[i], 0)),
    83. 

  83. +			       VOIDmode, 0, 0, i, RELOAD_FOR_INPUT);
    84. 

  84. +	      rld[operand_reloadnum[i]].inc
    85. 

  85. +		= GET_MODE_SIZE (GET_MODE (recog_data.operand[i]));
    86. 

  86. +
    87. 

  87. +	      /* If this operand is an output, we will have made any
    88. 

  88. +		 reloads for its address as RELOAD_FOR_OUTPUT_ADDRESS, but
    89. 

  89. +		 now we are treating part of the operand as an input, so
    90. 

  90. +		 we must change these to RELOAD_FOR_INPUT_ADDRESS.  */
    91. 

  91. +
    92. 

  92. +	      if (modified[i] == RELOAD_WRITE)
    93. 

  93. +		{
    94. 

  94. +		  for (j = 0; j < n_reloads; j++)
    95. 

  95. +		    {
    96. 

  96. +		      if (rld[j].opnum == i)
    97. 

  97. +			{
    98. 

  98. +			  if (rld[j].when_needed == RELOAD_FOR_OUTPUT_ADDRESS)
    99. 

  99. +			    rld[j].when_needed = RELOAD_FOR_INPUT_ADDRESS;
    100. 

  100. +			  else if (rld[j].when_needed
    101. 

  101. +				   == RELOAD_FOR_OUTADDR_ADDRESS)
    102. 

  102. +			    rld[j].when_needed = RELOAD_FOR_INPADDR_ADDRESS;
    103. 

  103. +			}
    104. 

  104. +		    }
    105. 

  105. +		}
    106. 

  106. +	    }
    107. 

  107. +	  else if (goal_alternative_matched[i] == -1)
    108. 

  108. +	    {
    109. 

  109. +	      operand_reloadnum[i]
    110. 

  110. +		= push_reload ((modified[i] != RELOAD_WRITE
    111. 

  111. +				? recog_data.operand[i] : 0),
    112. 

  112. +			       (modified[i] != RELOAD_READ
    113. 

  113. +				? recog_data.operand[i] : 0),
    114. 

  114. +			       (modified[i] != RELOAD_WRITE
    115. 

  115. +				? recog_data.operand_loc[i] : 0),
    116. 

  116. +			       (modified[i] != RELOAD_READ
    117. 

  117. +				? recog_data.operand_loc[i] : 0),
    118. 

  118. +			       (enum reg_class) goal_alternative[i],
    119. 

  119. +			       (modified[i] == RELOAD_WRITE
    120. 

  120. +				? VOIDmode : operand_mode[i]),
    121. 

  121. +			       (modified[i] == RELOAD_READ
    122. 

  122. +				? VOIDmode : operand_mode[i]),
    123. 

  123. +			       (insn_code_number < 0 ? 0
    124. 

  124. +				: insn_data[insn_code_number].operand[i].strict_low),
    125. 

  125. +			       0, i, operand_type[i]);
    126. 

  126. +	    }
    127. 

  127. +	  /* In a matching pair of operands, one must be input only
    128. 

  128. +	     and the other must be output only.
    129. 

  129. +	     Pass the input operand as IN and the other as OUT.  */
    130. 

  130. +	  else if (modified[i] == RELOAD_READ
    131. 

  131. +		   && modified[goal_alternative_matched[i]] == RELOAD_WRITE)
    132. 

  132. +	    {
    133. 

  133. +	      operand_reloadnum[i]
    134. 

  134. +		= push_reload (recog_data.operand[i],
    135. 

  135. +			       recog_data.operand[goal_alternative_matched[i]],
    136. 

  136. +			       recog_data.operand_loc[i],
    137. 

  137. +			       recog_data.operand_loc[goal_alternative_matched[i]],
    138. 

  138. +			       (enum reg_class) goal_alternative[i],
    139. 

  139. +			       operand_mode[i],
    140. 

  140. +			       operand_mode[goal_alternative_matched[i]],
    141. 

  141. +			       0, 0, i, RELOAD_OTHER);
    142. 

  142. +	      operand_reloadnum[goal_alternative_matched[i]] = output_reloadnum;
    143. 

  143. +	    }
    144. 

  144. +	  else if (modified[i] == RELOAD_WRITE
    145. 

  145. +		   && modified[goal_alternative_matched[i]] == RELOAD_READ)
    146. 

  146. +	    {
    147. 

  147. +	      operand_reloadnum[goal_alternative_matched[i]]
    148. 

  148. +		= push_reload (recog_data.operand[goal_alternative_matched[i]],
    149. 

  149. +			       recog_data.operand[i],
    150. 

  150. +			       recog_data.operand_loc[goal_alternative_matched[i]],
    151. 

  151. +			       recog_data.operand_loc[i],
    152. 

  152. +			       (enum reg_class) goal_alternative[i],
    153. 

  153. +			       operand_mode[goal_alternative_matched[i]],
    154. 

  154. +			       operand_mode[i],
    155. 

  155. +			       0, 0, i, RELOAD_OTHER);
    156. 

  156. +	      operand_reloadnum[i] = output_reloadnum;
    157. 

  157. +	    }
    158. 

  158. +	  else if (insn_code_number >= 0)
    159. 

  159. +	    abort ();
    160. 

  160. +	  else
    161. 

  161. +	    {
    162. 

  162. +	      error_for_asm (insn, "inconsistent operand constraints in an `asm'");
    163. 

  163. +	      /* Avoid further trouble with this insn.  */
    164. 

  164. +	      PATTERN (insn) = gen_rtx_USE (VOIDmode, const0_rtx);
    165. 

  165. +	      n_reloads = 0;
    166. 

  166. +	      return 0;
    167. 

  167. +	    }
    168. 

  168. +	}
    169. 

  169. +      else if (goal_alternative_matched[i] < 0
    170. 

  170. +	       && goal_alternative_matches[i] < 0
    171. 

  171. +	       && optimize)
    172. 

  172. +	{
    173. 

  173. +	  /* For each non-matching operand that's a MEM or a pseudo-register
    174. 

  174. +	     that didn't get a hard register, make an optional reload.
    175. 

  175. +	     This may get done even if the insn needs no reloads otherwise.  */
    176. 

  176. +
    177. 

  177. +	  rtx operand = recog_data.operand[i];
    178. 

  178. +
    179. 

  179. +	  while (GET_CODE (operand) == SUBREG)
    180. 

  180. +	    operand = SUBREG_REG (operand);
    181. 

  181. +	  if ((GET_CODE (operand) == MEM
    182. 

  182. +	       || (GET_CODE (operand) == REG
    183. 

  183. +		   && REGNO (operand) >= FIRST_PSEUDO_REGISTER))
    184. 

  184. +	      /* If this is only for an output, the optional reload would not
    185. 

  185. +		 actually cause us to use a register now, just note that
    186. 

  186. +		 something is stored here.  */
    187. 

  187. +	      && ((enum reg_class) goal_alternative[i] != NO_REGS
    188. 

  188. +		  || modified[i] == RELOAD_WRITE)
    189. 

  189. +	      && ! no_input_reloads
    190. 

  190. +	      /* An optional output reload might allow to delete INSN later.
    191. 

  191. +		 We mustn't make in-out reloads on insns that are not permitted
    192. 

  192. +		 output reloads.
    193. 

  193. +		 If this is an asm, we can't delete it; we must not even call
    194. 

  194. +		 push_reload for an optional output reload in this case,
    195. 

  195. +		 because we can't be sure that the constraint allows a register,
    196. 

  196. +		 and push_reload verifies the constraints for asms.  */
    197. 

  197. +	      && (modified[i] == RELOAD_READ
    198. 

  198. +		  || (! no_output_reloads && ! this_insn_is_asm)))
    199. 

  199.  	    operand_reloadnum[i]
    200. 

  200.  	      = push_reload ((modified[i] != RELOAD_WRITE
    201. 

  201.  			      ? recog_data.operand[i] : 0),
    202. 

  202. @@ -3684,150 +3775,69 @@ find_reloads (insn, replace, ind_levels,
    203. 

  203.  			      ? VOIDmode : operand_mode[i]),
    204. 

  204.  			     (insn_code_number < 0 ? 0
    205. 

  205.  			      : insn_data[insn_code_number].operand[i].strict_low),
    206. 

  206. -			     0, i, operand_type[i]);
    207. 

  207. -	  }
    208. 

  208. -	/* In a matching pair of operands, one must be input only
    209. 

  209. -	   and the other must be output only.
    210. 

  210. -	   Pass the input operand as IN and the other as OUT.  */
    211. 

  211. -	else if (modified[i] == RELOAD_READ
    212. 

  212. -		 && modified[goal_alternative_matched[i]] == RELOAD_WRITE)
    213. 

  213. -	  {
    214. 

  214. -	    operand_reloadnum[i]
    215. 

  215. -	      = push_reload (recog_data.operand[i],
    216. 

  216. -			     recog_data.operand[goal_alternative_matched[i]],
    217. 

  217. -			     recog_data.operand_loc[i],
    218. 

  218. -			     recog_data.operand_loc[goal_alternative_matched[i]],
    219. 

  219. -			     (enum reg_class) goal_alternative[i],
    220. 

  220. -			     operand_mode[i],
    221. 

  221. -			     operand_mode[goal_alternative_matched[i]],
    222. 

  222. -			     0, 0, i, RELOAD_OTHER);
    223. 

  223. -	    operand_reloadnum[goal_alternative_matched[i]] = output_reloadnum;
    224. 

  224. -	  }
    225. 

  225. -	else if (modified[i] == RELOAD_WRITE
    226. 

  226. -		 && modified[goal_alternative_matched[i]] == RELOAD_READ)
    227. 

  227. -	  {
    228. 

  228. -	    operand_reloadnum[goal_alternative_matched[i]]
    229. 

  229. -	      = push_reload (recog_data.operand[goal_alternative_matched[i]],
    230. 

  230. +			     1, i, operand_type[i]);
    231. 

  231. +	}
    232. 

  232. +      else if (goal_alternative_matches[i] >= 0
    233. 

  233. +	       && goal_alternative_win[goal_alternative_matches[i]]
    234. 

  234. +	       && modified[i] == RELOAD_READ
    235. 

  235. +	       && modified[goal_alternative_matches[i]] == RELOAD_WRITE
    236. 

  236. +	       && ! no_input_reloads && ! no_output_reloads
    237. 

  237. +	       && optimize)
    238. 

  238. +	{
    239. 

  239. +	  /* Similarly, make an optional reload for a pair of matching
    240. 

  240. +	     objects that are in MEM or a pseudo that didn't get a hard reg.  */
    241. 

  241. +
    242. 

  242. +	  rtx operand = recog_data.operand[i];
    243. 

  243. +
    244. 

  244. +	  while (GET_CODE (operand) == SUBREG)
    245. 

  245. +	    operand = SUBREG_REG (operand);
    246. 

  246. +	  if ((GET_CODE (operand) == MEM
    247. 

  247. +	       || (GET_CODE (operand) == REG
    248. 

  248. +		   && REGNO (operand) >= FIRST_PSEUDO_REGISTER))
    249. 

  249. +	      && ((enum reg_class) goal_alternative[goal_alternative_matches[i]]
    250. 

  250. +		  != NO_REGS))
    251. 

  251. +	    operand_reloadnum[i] = operand_reloadnum[goal_alternative_matches[i]]
    252. 

  252. +	      = push_reload (recog_data.operand[goal_alternative_matches[i]],
    253. 

  253.  			     recog_data.operand[i],
    254. 

  254. -			     recog_data.operand_loc[goal_alternative_matched[i]],
    255. 

  255. +			     recog_data.operand_loc[goal_alternative_matches[i]],
    256. 

  256.  			     recog_data.operand_loc[i],
    257. 

  257. -			     (enum reg_class) goal_alternative[i],
    258. 

  258. -			     operand_mode[goal_alternative_matched[i]],
    259. 

  259. +			     (enum reg_class) goal_alternative[goal_alternative_matches[i]],
    260. 

  260. +			     operand_mode[goal_alternative_matches[i]],
    261. 

  261.  			     operand_mode[i],
    262. 

  262. -			     0, 0, i, RELOAD_OTHER);
    263. 

  263. -	    operand_reloadnum[i] = output_reloadnum;
    264. 

  264. -	  }
    265. 

  265. -	else if (insn_code_number >= 0)
    266. 

  266. -	  abort ();
    267. 

  267. -	else
    268. 

  268. -	  {
    269. 

  269. -	    error_for_asm (insn, "inconsistent operand constraints in an `asm'");
    270. 

  270. -	    /* Avoid further trouble with this insn.  */
    271. 

  271. -	    PATTERN (insn) = gen_rtx_USE (VOIDmode, const0_rtx);
    272. 

  272. -	    n_reloads = 0;
    273. 

  273. -	    return 0;
    274. 

  274. -	  }
    275. 

  275. -      }
    276. 

  276. -    else if (goal_alternative_matched[i] < 0
    277. 

  277. -	     && goal_alternative_matches[i] < 0
    278. 

  278. -	     && optimize)
    279. 

  279. -      {
    280. 

  280. -	/* For each non-matching operand that's a MEM or a pseudo-register
    281. 

  281. -	   that didn't get a hard register, make an optional reload.
    282. 

  282. -	   This may get done even if the insn needs no reloads otherwise.  */
    283. 

  283. -
    284. 

  284. -	rtx operand = recog_data.operand[i];
    285. 

  285. -
    286. 

  286. -	while (GET_CODE (operand) == SUBREG)
    287. 

  287. -	  operand = SUBREG_REG (operand);
    288. 

  288. -	if ((GET_CODE (operand) == MEM
    289. 

  289. -	     || (GET_CODE (operand) == REG
    290. 

  290. -		 && REGNO (operand) >= FIRST_PSEUDO_REGISTER))
    291. 

  291. -	    /* If this is only for an output, the optional reload would not
    292. 

  292. -	       actually cause us to use a register now, just note that
    293. 

  293. -	       something is stored here.  */
    294. 

  294. -	    && ((enum reg_class) goal_alternative[i] != NO_REGS
    295. 

  295. -		|| modified[i] == RELOAD_WRITE)
    296. 

  296. -	    && ! no_input_reloads
    297. 

  297. -	    /* An optional output reload might allow to delete INSN later.
    298. 

  298. -	       We mustn't make in-out reloads on insns that are not permitted
    299. 

  299. -	       output reloads.
    300. 

  300. -	       If this is an asm, we can't delete it; we must not even call
    301. 

  301. -	       push_reload for an optional output reload in this case,
    302. 

  302. -	       because we can't be sure that the constraint allows a register,
    303. 

  303. -	       and push_reload verifies the constraints for asms.  */
    304. 

  304. -	    && (modified[i] == RELOAD_READ
    305. 

  305. -		|| (! no_output_reloads && ! this_insn_is_asm)))
    306. 

  306. -	  operand_reloadnum[i]
    307. 

  307. -	    = push_reload ((modified[i] != RELOAD_WRITE
    308. 

  308. -			    ? recog_data.operand[i] : 0),
    309. 

  309. -			   (modified[i] != RELOAD_READ
    310. 

  310. -			    ? recog_data.operand[i] : 0),
    311. 

  311. -			   (modified[i] != RELOAD_WRITE
    312. 

  312. -			    ? recog_data.operand_loc[i] : 0),
    313. 

  313. -			   (modified[i] != RELOAD_READ
    314. 

  314. -			    ? recog_data.operand_loc[i] : 0),
    315. 

  315. -			   (enum reg_class) goal_alternative[i],
    316. 

  316. -			   (modified[i] == RELOAD_WRITE
    317. 

  317. -			    ? VOIDmode : operand_mode[i]),
    318. 

  318. -			   (modified[i] == RELOAD_READ
    319. 

  319. -			    ? VOIDmode : operand_mode[i]),
    320. 

  320. -			   (insn_code_number < 0 ? 0
    321. 

  321. -			    : insn_data[insn_code_number].operand[i].strict_low),
    322. 

  322. -			   1, i, operand_type[i]);
    323. 

  323. -	/* If a memory reference remains (either as a MEM or a pseudo that
    324. 

  324. -	   did not get a hard register), yet we can't make an optional
    325. 

  325. -	   reload, check if this is actually a pseudo register reference;
    326. 

  326. -	   we then need to emit a USE and/or a CLOBBER so that reload
    327. 

  327. -	   inheritance will do the right thing.  */
    328. 

  328. -	else if (replace
    329. 

  329. -		 && (GET_CODE (operand) == MEM
    330. 

  330. -		     || (GET_CODE (operand) == REG
    331. 

  331. -			 && REGNO (operand) >= FIRST_PSEUDO_REGISTER
    332. 

  332. -			 && reg_renumber [REGNO (operand)] < 0)))
    333. 

  333. -	  {
    334. 

  334. -	    operand = *recog_data.operand_loc[i];
    335. 

  335. -
    336. 

  336. -	    while (GET_CODE (operand) == SUBREG)
    337. 

  337. -	      operand = SUBREG_REG (operand);
    338. 

  338. -	    if (GET_CODE (operand) == REG)
    339. 

  339. -	      {
    340. 

  340. -		if (modified[i] != RELOAD_WRITE)
    341. 

  341. -		  emit_insn_before (gen_rtx_USE (VOIDmode, operand), insn);
    342. 

  342. -		if (modified[i] != RELOAD_READ)
    343. 

  343. -		  emit_insn_after (gen_rtx_CLOBBER (VOIDmode, operand), insn);
    344. 

  344. -	      }
    345. 

  345. -	  }
    346. 

  346. -      }
    347. 

  347. -    else if (goal_alternative_matches[i] >= 0
    348. 

  348. -	     && goal_alternative_win[goal_alternative_matches[i]]
    349. 

  349. -	     && modified[i] == RELOAD_READ
    350. 

  350. -	     && modified[goal_alternative_matches[i]] == RELOAD_WRITE
    351. 

  351. -	     && ! no_input_reloads && ! no_output_reloads
    352. 

  352. -	     && optimize)
    353. 

  353. -      {
    354. 

  354. -	/* Similarly, make an optional reload for a pair of matching
    355. 

  355. -	   objects that are in MEM or a pseudo that didn't get a hard reg.  */
    356. 

  356. -
    357. 

  357. -	rtx operand = recog_data.operand[i];
    358. 

  358. -
    359. 

  359. -	while (GET_CODE (operand) == SUBREG)
    360. 

  360. -	  operand = SUBREG_REG (operand);
    361. 

  361. -	if ((GET_CODE (operand) == MEM
    362. 

  362. -	     || (GET_CODE (operand) == REG
    363. 

  363. -		 && REGNO (operand) >= FIRST_PSEUDO_REGISTER))
    364. 

  364. -	    && ((enum reg_class) goal_alternative[goal_alternative_matches[i]]
    365. 

  365. -		!= NO_REGS))
    366. 

  366. -	  operand_reloadnum[i] = operand_reloadnum[goal_alternative_matches[i]]
    367. 

  367. -	    = push_reload (recog_data.operand[goal_alternative_matches[i]],
    368. 

  368. -			   recog_data.operand[i],
    369. 

  369. -			   recog_data.operand_loc[goal_alternative_matches[i]],
    370. 

  370. -			   recog_data.operand_loc[i],
    371. 

  371. -			   (enum reg_class) goal_alternative[goal_alternative_matches[i]],
    372. 

  372. -			   operand_mode[goal_alternative_matches[i]],
    373. 

  373. -			   operand_mode[i],
    374. 

  374. -			   0, 1, goal_alternative_matches[i], RELOAD_OTHER);
    375. 

  375. -      }
    376. 

  376. +			     0, 1, goal_alternative_matches[i], RELOAD_OTHER);
    377. 

  377. +	}
    378. 

  378. +
    379. 

  379. +      /* If a memory reference remains (either as a MEM or a pseudo that
    380. 

  380. +	 did not get a hard register), yet we can't make an optional
    381. 

  381. +	 reload, check if this is actually a pseudo register reference;
    382. 

  382. +	 we then need to emit a USE and/or a CLOBBER so that reload
    383. 

  383. +	 inheritance will do the right thing.  */
    384. 

  384. +      if (operand_reloadnum[i] == -1 && replace)
    385. 

  385. +	{
    386. 

  386. +	  rtx operand = recog_data.operand[i];
    387. 

  387. +
    388. 

  388. +	  while (GET_CODE (operand) == SUBREG)
    389. 

  389. +	    operand = SUBREG_REG (operand);
    390. 

  390. +	  
    391. 

  391. +	  if (GET_CODE (operand) == MEM
    392. 

  392. +	      || (GET_CODE (operand) == REG
    393. 

  393. +		  && REGNO (operand) >= FIRST_PSEUDO_REGISTER
    394. 

  394. +		  && reg_renumber [REGNO (operand)] < 0))
    395. 

  395. +	    {
    396. 

  396. +	      operand = *recog_data.operand_loc[i];
    397. 

  397. +
    398. 

  398. +	      while (GET_CODE (operand) == SUBREG)
    399. 

  399. +		operand = SUBREG_REG (operand);
    400. 

  400. +	      if (GET_CODE (operand) == REG)
    401. 

  401. +		{
    402. 

  402. +		  if (modified[i] != RELOAD_WRITE)
    403. 

  403. +		    emit_insn_before (gen_rtx_USE (VOIDmode, operand), insn);
    404. 

  404. +		  if (modified[i] != RELOAD_READ)
    405. 

  405. +		    emit_insn_after (gen_rtx_CLOBBER (VOIDmode, operand), insn);
    406. 

  406. +		}
    407. 

  407. +	    }
    408. 

  408. +	}
    409. 

  409. +    }
    410. 

  410.  
    411. 

  411.    /* Perform whatever substitutions on the operands we are supposed
    412. 

  412.       to make due to commutativity or replacement of registers
    413. 

  413. --- gcc/testsuite/gcc.dg/20011024-1.c.jj	Thu Aug 30 22:30:55 2001
    414. 

  414. +++ gcc/testsuite/gcc.dg/20011024-1.c	Fri Oct 19 18:33:49 2001
    415. 

  415. @@ -0,0 +1,264 @@
    416. 

  416. +/* { dg-do run { target i?86-*-* } } */
    417. 

  417. +/* { dg-options "-O2 -fomit-frame-pointer -march=i686" } */
    418. 

  418. +
    419. 

  419. +typedef struct {
    420. 

  420. +  void *s1a;
    421. 

  421. +} s1;
    422. 

  422. +typedef struct {
    423. 

  423. +  unsigned int s2a;
    424. 

  424. +  unsigned long long s2b;
    425. 

  425. +  unsigned int s2c;
    426. 

  426. +  unsigned int s2d;
    427. 

  427. +  unsigned short s2e;
    428. 

  428. +  unsigned char s2f;
    429. 

  429. +  s1 *s2g;
    430. 

  430. +  unsigned char s2h;
    431. 

  431. +} s2;
    432. 

  432. +typedef struct
    433. 

  433. +{
    434. 

  434. +  unsigned int s3a;
    435. 

  435. +  unsigned int s3b;
    436. 

  436. +  unsigned int s3c;
    437. 

  437. +  unsigned int s3d;
    438. 

  438. +  unsigned int s3e[2];
    439. 

  439. +  unsigned int s3f[3];
    440. 

  440. +  unsigned int s3g;
    441. 

  441. +  unsigned int s3h;
    442. 

  442. +  unsigned int s3i;
    443. 

  443. +  unsigned int s3j;
    444. 

  444. +  unsigned int s3k;
    445. 

  445. +} s3;
    446. 

  446. +typedef struct
    447. 

  447. +{
    448. 

  448. +  unsigned int s4a;
    449. 

  449. +  unsigned int s4b;
    450. 

  450. +  unsigned int s4c;
    451. 

  451. +  unsigned int s4d;
    452. 

  452. +  unsigned int s4e;
    453. 

  453. +  unsigned int s4f;
    454. 

  454. +  unsigned int s4g;
    455. 

  455. +  unsigned int s4h;
    456. 

  456. +  unsigned int s4i;
    457. 

  457. +  unsigned int s4j;
    458. 

  458. +  unsigned int s4k[64];
    459. 

  459. +} s4;
    460. 

  460. +typedef struct
    461. 

  461. +{
    462. 

  462. +  unsigned int s5a;
    463. 

  463. +  unsigned int s5b;
    464. 

  464. +} s5;
    465. 

  465. +typedef struct
    466. 

  466. +{
    467. 

  467. +  unsigned int s6a;
    468. 

  468. +  unsigned short s6b;
    469. 

  469. +  unsigned short s6c;
    470. 

  470. +  unsigned int s6d;
    471. 

  471. +  unsigned int s6e;
    472. 

  472. +} s6;
    473. 

  473. +typedef struct
    474. 

  474. +{
    475. 

  475. +  unsigned long long s7a;
    476. 

  476. +  unsigned int s7b;
    477. 

  477. +} s7;
    478. 

  478. +
    479. 

  479. +char buffer[1024];
    480. 

  480. +
    481. 

  481. +void f1 (void *x, int y, unsigned int z)
    482. 

  482. +{
    483. 

  483. +}
    484. 

  484. +
    485. 

  485. +static inline const unsigned int f2 (unsigned int x)
    486. 

  486. +{
    487. 

  487. +  asm("" : "=r" (x) : "0" (x));
    488. 

  488. +  return x;
    489. 

  489. +}
    490. 

  490. +
    491. 

  491. +int f3 (s2 *x, void *y, long long z, s1 **p)
    492. 

  492. +{
    493. 

  493. +  return 0;
    494. 

  494. +}
    495. 

  495. +
    496. 

  496. +void *f4(s2 *x, unsigned int y)
    497. 

  497. +{
    498. 

  498. +  return 0;
    499. 

  499. +}
    500. 

  500. +
    501. 

  501. +int f5(void *x)
    502. 

  502. +{
    503. 

  503. +  return 0;
    504. 

  504. +}
    505. 

  505. +
    506. 

  506. +int f6(s2 *x, s1 *y)
    507. 

  507. +{
    508. 

  508. +  static int i;
    509. 

  509. +
    510. 

  510. +  return i++;
    511. 

  511. +}
    512. 

  512. +
    513. 

  513. +s1 *foo (void *x, long long y, unsigned int z, int v)
    514. 

  514. +{
    515. 

  515. +  static s1 a;
    516. 

  516. +  static int b;
    517. 

  517. +
    518. 

  518. +  if (v != 0x2204 || x != buffer)
    519. 

  519. +    abort ();
    520. 

  520. +  if (y != 0x2c5e780000000200LL + b)
    521. 

  521. +    abort ();
    522. 

  522. +  b += 0x200;
    523. 

  523. +  a.s1a = (char *) x + 32;
    524. 

  524. +  return &a;
    525. 

  525. +}
    526. 

  526. +
    527. 

  527. +int test (s2 *x, s7 *y)
    528. 

  528. +{
    529. 

  529. +  s1 *v1;
    530. 

  530. +  s3 *v3;
    531. 

  531. +  s4 *v4;
    532. 

  532. +  s5 *v5;
    533. 

  533. +  s6 *v6;
    534. 

  534. +  unsigned int a, b, c;
    535. 

  535. +  int d, e, f, g, h, i;
    536. 

  536. +  unsigned int j, k;
    537. 

  537. +  unsigned long long l, m, n;
    538. 

  538. +  void *o;
    539. 

  539. +
    540. 

  540. +  l = y->s7a;
    541. 

  541. +  h = y->s7b;
    542. 

  542. +  f = h - x->s2f;
    543. 

  543. +  g = f3 (x, x->s2g, (l << x->s2h) - 1, &v1);
    544. 

  544. +  if (g)
    545. 

  545. +    return g;
    546. 

  546. +
    547. 

  547. +  m = l;
    548. 

  548. +  j = m + 1;
    549. 

  549. +  m = y->s7a - x->s2b;
    550. 

  550. +  k = x->s2d;
    551. 

  551. +  o = f4 (x, 14);
    552. 

  552. +  g = f5 (o);
    553. 

  553. +  if (g)
    554. 

  554. +    return g;
    555. 

  555. +
    556. 

  556. +  i = ((unsigned long long) x->s2e + 511) >> 9;
    557. 

  557. +  d = x->s2a;
    558. 

  558. +
    559. 

  559. +  n = 0;
    560. 

  560. +  for (a = j - 1; a >= k; a--, m -= b) {
    561. 

  561. +    v1 = foo (x->s2g->s1a,
    562. 

  562. +	      ((((unsigned long long) a * x->s2c) << x->s2h) + 1LL) << 9,
    563. 

  563. +	      i << 9, 0x2204);
    564. 

  564. +    v3 = (s3 *)v1->s1a;
    565. 

  565. +    f1 (v3, 0, x->s2e);
    566. 

  566. +    v3->s3a = 0x58414746;
    567. 

  567. +    v3->s3a = f2 (v3->s3a);
    568. 

  568. +    v3->s3b = 1;
    569. 

  569. +    v3->s3b = f2 (v3->s3b);
    570. 

  570. +    v3->s3c = a;
    571. 

  571. +    v3->s3c = f2 (v3->s3c);
    572. 

  572. +    if (a == j - 1)
    573. 

  573. +      b = l - a * (unsigned long long) x->s2c;
    574. 

  574. +    else
    575. 

  575. +      b = x->s2c;
    576. 

  576. +    v3->s3d = b;
    577. 

  577. +    v3->s3d = f2 (v3->s3d);
    578. 

  578. +    v3->s3e[0] = (3LL >> x->s2h) + 1;
    579. 

  579. +    v3->s3e[0] = f2 (v3->s3e[0]);
    580. 

  580. +    v3->s3e[1] = (3LL >> x->s2h) + 2;
    581. 

  581. +    v3->s3e[1] = f2 (v3->s3e[1]);
    582. 

  582. +    v3->s3f[0] = 1;
    583. 

  583. +    v3->s3f[0] = f2 (v3->s3f[0]);
    584. 

  584. +    v3->s3f[1] = 1;
    585. 

  585. +    v3->s3f[1] = f2 (v3->s3f[1]);
    586. 

  586. +    v3->s3g = 0;
    587. 

  587. +    v3->s3g = f2 (v3->s3g);
    588. 

  588. +    v3->s3h = 512 / sizeof (unsigned int) - 1;
    589. 

  589. +    v3->s3h = f2 (v3->s3h);
    590. 

  590. +    v3->s3i = 0;
    591. 

  591. +    v3->s3i = f2 (v3->s3i);
    592. 

  592. +    c = b - ((unsigned int) (3LL >> x->s2h)) - 4;
    593. 

  593. +    v3->s3j = c;
    594. 

  594. +    v3->s3j = f2 (v3->s3j);
    595. 

  595. +    v3->s3k = c;
    596. 

  596. +    v3->s3k = f2 (v3->s3k);
    597. 

  597. +    g = f6 (x, v1);
    598. 

  598. +    if (g)
    599. 

  599. +      goto l0;
    600. 

  600. +
    601. 

  601. +    v1 = foo (x->s2g->s1a,
    602. 

  602. +	      ((((unsigned long long) a * x->s2c) << x->s2h) + 2LL) << 9,
    603. 

  603. +	      i << 9, 0x2204);
    604. 

  604. +    v4 = (s4 *)v1->s1a;
    605. 

  605. +    f1 (v4, 0, x->s2e);
    606. 

  606. +    v4->s4a = 0x58414749;
    607. 

  607. +    v4->s4a = f2 (v4->s4a);
    608. 

  608. +    v4->s4b = 1;
    609. 

  609. +    v4->s4b = f2 (v4->s4b);
    610. 

  610. +    v4->s4c = a;
    611. 

  611. +    v4->s4c = f2 (v4->s4c);
    612. 

  612. +    v4->s4d = b;
    613. 

  613. +    v4->s4d = f2 (v4->s4d);
    614. 

  614. +    v4->s4e = 0;
    615. 

  615. +    v4->s4e = f2 (v4->s4e);
    616. 

  616. +    v4->s4f = (3LL >> x->s2h) + 3;
    617. 

  617. +    v4->s4f = f2 (v4->s4f);
    618. 

  618. +    v4->s4g = 1;
    619. 

  619. +    v4->s4g = f2 (v4->s4g);
    620. 

  620. +    v4->s4h = 0;
    621. 

  621. +    v4->s4h = f2 (v4->s4h);
    622. 

  622. +    v4->s4i = -1;
    623. 

  623. +    v4->s4i = f2 (v4->s4i);
    624. 

  624. +    v4->s4j = -1;
    625. 

  625. +    v4->s4j = f2 (v4->s4j);
    626. 

  626. +    for (e = 0; e < 64; e++)
    627. 

  627. +      {
    628. 

  628. +        v4->s4k[e] = -1;
    629. 

  629. +        v4->s4k[e] = f2 (v4->s4k[e]);
    630. 

  630. +      }
    631. 

  631. +    g = f6 (x, v1);
    632. 

  632. +    if (g)
    633. 

  633. +      goto l0;
    634. 

  634. +
    635. 

  635. +    v1 = foo (x->s2g->s1a,
    636. 

  636. +	      (((unsigned long long) a * x->s2c
    637. 

  637. +		+ (unsigned int) ((3LL >> x->s2h) + 1)) << x->s2h) << 9,
    638. 

  638. +	      (((unsigned long long) d + 511) >> 9) << 9, 0x2204);
    639. 

  639. +    v6 = (s6 *)v1->s1a;
    640. 

  640. +    f1 (v6, 0, d);
    641. 

  641. +    v6->s6a = 0x41425442;
    642. 

  642. +    v6->s6a = f2 (v6->s6a);
    643. 

  643. +    v6->s6b = 0;
    644. 

  644. +    v6->s6b = f2 (v6->s6b);
    645. 

  645. +    v6->s6c = 1;
    646. 

  646. +    v6->s6c = f2 (v6->s6c);
    647. 

  647. +    v6->s6d = -1;
    648. 

  648. +    v6->s6d = f2 (v6->s6d);
    649. 

  649. +    v6->s6e = -1;
    650. 

  650. +    v6->s6e = f2 (v6->s6e);
    651. 

  651. +    v5 = (s5 *) ((char *) v6 + 24);
    652. 

  652. +    v5->s5a = (3LL >> x->s2h) + 4;
    653. 

  653. +    v5->s5a = f2 (v5->s5a);
    654. 

  654. +    v5->s5b = b - v5->s5a;
    655. 

  655. +    g = f6 (x, v1);
    656. 

  656. +    if (g)
    657. 

  657. +      goto l0;
    658. 

  658. +  }
    659. 

  659. +  return 0;
    660. 

  660. +
    661. 

  661. +l0:
    662. 

  662. +  return g;
    663. 

  663. +}
    664. 

  664. +
    665. 

  665. +s2 a;
    666. 

  666. +s7 b;
    667. 

  667. +s1 c;
    668. 

  668. +
    669. 

  669. +int main (void)
    670. 

  670. +{
    671. 

  671. +  b.s7a = 66;
    672. 

  672. +  a.s2c = 0xabcdef;
    673. 

  673. +  a.s2g = &c;
    674. 

  674. +  a.s2h = 33;
    675. 

  675. +  c.s1a = buffer;
    676. 

  676. +  if (test (&a, &b) != 1)
    677. 

  677. +    abort ();
    678. 

  678. +  exit (0);
    679. 

  679. +}
    680.