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/vendor/gc/libatomic_ops-1.2/src/atomic_ops/sysdeps/ibmc/powerpc.h

http://github.com/feyeleanor/RubyGoLightly
C++ Header | 126 lines | 78 code | 26 blank | 22 comment | 0 complexity | 7f2025239e6c70906e0b919180606d49 MD5 | raw file
  1/* FIXME.  This is only a placeholder for the AIX compiler.  		*/
  2/* It doesn't work.  Please send a patch.				*/
  3/* Memory model documented at http://www-106.ibm.com/developerworks/	*/
  4/* eserver/articles/archguide.html and (clearer)			*/
  5/* http://www-106.ibm.com/developerworks/eserver/articles/powerpc.html. */
  6/* There appears to be no implicit ordering between any kind of		*/
  7/* independent memory references.					*/
  8/* Architecture enforces some ordering based on control dependence.	*/
  9/* I don't know if that could help. 					*/
 10/* Data-dependent loads are always ordered.				*/
 11/* Based on the above references, eieio is intended for use on		*/
 12/* uncached memory, which we don't support.  It does not order loads	*/
 13/* from cached memory.							*/
 14/* Thanks to Maged Michael, Doug Lea, and Roger Hoover for helping to 	*/
 15/* track some of this down and correcting my misunderstandings. -HB	*/
 16
 17#include "../all_aligned_atomic_load_store.h"
 18
 19void AO_sync(void);
 20#pragma mc_func AO_sync { "7c0004ac" }
 21
 22void AO_lwsync(void);
 23#pragma mc_func AO_lwsync { "7c2004ac" }
 24
 25#define AO_nop_write() AO_lwsync()
 26#define AO_HAVE_nop_write
 27
 28#define AO_nop_read() AO_lwsync()
 29#define AO_HAVE_nop_read
 30
 31/* We explicitly specify load_acquire and store_release, since these	*/
 32/* rely on the fact that lwsync is also a LoadStore barrier.		*/
 33AO_INLINE AO_t
 34AO_load_acquire(volatile AO_t *addr)
 35{
 36  AO_t result = *addr;
 37  AO_lwsync();
 38  return result;
 39}
 40
 41#define AO_HAVE_load_acquire
 42
 43AO_INLINE void
 44AO_store_release(volatile AO_t *addr, AO_t value)
 45{
 46  AO_lwsync();
 47  *addr = value;
 48}
 49
 50#define AO_HAVE_load_acquire
 51
 52/* This is similar to the code in the garbage collector.  Deleting 	*/
 53/* this and having it synthesized from compare_and_swap would probably	*/
 54/* only cost us a load immediate instruction.				*/
 55AO_INLINE AO_TS_VAL_t
 56AO_test_and_set(volatile AO_TS_t *addr) {
 57# error Implement me
 58}
 59
 60#define AO_have_test_and_set
 61
 62AO_INLINE AO_TS_VAL_t
 63AO_test_and_set_acquire(volatile AO_TS_t *addr) {
 64  AO_TS_VAL_t result = AO_test_and_set(addr);
 65  AO_lwsync();
 66  return result;
 67}
 68
 69#define AO_HAVE_test_and_set_acquire
 70
 71AO_INLINE AO_TS_VAL_t
 72AO_test_and_set_release(volatile AO_TS_t *addr) {
 73  AO_lwsync();
 74  return AO_test_and_set(addr);
 75}
 76
 77#define AO_HAVE_test_and_set_release
 78
 79AO_INLINE AO_TS_VAL_t
 80AO_test_and_set_full(volatile AO_TS_t *addr) {
 81  AO_TS_VAL_t result;
 82  AO_lwsync();
 83  result = AO_test_and_set(addr);
 84  AO_lwsync();
 85  return result;
 86}
 87
 88#define AO_HAVE_test_and_set_full
 89
 90AO_INLINE AO_t
 91AO_compare_and_swap(volatile AO_t *addr, AO_t old, AO_t new_val) {
 92# error Implement me
 93}
 94
 95#define AO_HAVE_compare_and_swap
 96
 97AO_INLINE AO_t
 98AO_compare_and_swap_acquire(volatile AO_t *addr, AO_t old, AO_t new_val) {
 99  AO_t result = AO_compare_and_swap(addr, old, new_val);
100  AO_lwsync();
101  return result;
102}
103
104#define AO_HAVE_compare_and_swap_acquire
105
106AO_INLINE AO_t
107AO_compare_and_swap_release(volatile AO_t *addr, AO_t old, AO_t new_val) {
108  AO_lwsync();
109  return AO_compare_and_swap(addr, old, new_val);
110}
111
112#define AO_HAVE_compare_and_swap_release
113
114AO_INLINE AO_t
115AO_compare_and_swap_full(volatile AO_t *addr, AO_t old, AO_t new_val) {
116  AO_t result;
117  AO_lwsync();
118  result = AO_compare_and_swap(addr, old, new_val);
119  AO_lwsync();
120  return result;
121}
122
123#define AO_HAVE_compare_and_swap_full
124
125/* FIXME: We should also implement fetch_and_add and or primitives	*/
126/* directly.								*/