/vendor/gc/libatomic_ops-1.2/src/atomic_ops/sysdeps/gcc/s390.h

http://github.com/feyeleanor/RubyGoLightly · C++ Header · 63 lines · 21 code · 7 blank · 35 comment · 1 complexity · ad6b9ad0d2f8f7e3449ce98b49321456 MD5 · raw file 

    

  1. /* 
    2. 

  2.  * Copyright (c) 1991-1994 by Xerox Corporation.  All rights reserved.
    3. 

  3.  * Copyright (c) 1996-1999 by Silicon Graphics.  All rights reserved.
    4. 

  4.  * Copyright (c) 1999-2003 by Hewlett-Packard Company. All rights reserved.
    5. 

  5.  *
    6. 

  6.  *
    7. 

  7.  * THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY EXPRESSED
    8. 

  8.  * OR IMPLIED.  ANY USE IS AT YOUR OWN RISK.
    9. 

  9.  *
    10. 

  10.  * Permission is hereby granted to use or copy this program
    11. 

  11.  * for any purpose,  provided the above notices are retained on all copies.
    12. 

  12.  * Permission to modify the code and to distribute modified code is granted,
    13. 

  13.  * provided the above notices are retained, and a notice that the code was
    14. 

  14.  * modified is included with the above copyright notice.
    15. 

  15.  *
    16. 

  16.  */
    17. 

  17. 

  18. /* FIXME: untested.						*/
    19. 

  19. /* The relevant documentation appears to be at			*/
    20. 

  20. /* http://publibz.boulder.ibm.com/epubs/pdf/dz9zr003.pdf	*/
    21. 

  21. /* around page 5-96.  Apparently:				*/
    22. 

  22. /* - Memory references in general are atomic only for a single 	*/
    23. 

  23. /*   byte.  But it appears that the most common load/store	*/
    24. 

  24. /*   instructions also guarantee atomicity for aligned 		*/
    25. 

  25. /*   operands of standard types.  WE FOOLISHLY ASSUME that	*/
    26. 

  26. /*   compilers only generate those.  If that turns out to be	*/
    27. 

  27. /*   wrong, we need inline assembly code for AO_load and	*/
    28. 

  28. /*   AO_store.							*/
    29. 

  29. /* - A store followed by a load is unordered since the store	*/
    30. 

  30. /*   may be delayed.  Otherwise everything is ordered.		*/
    31. 

  31. /* - There is a hardware compare-and-swap (CS) instruction.	*/
    32. 

  32. 

  33. #include "ordered_except_wr.h"
    34. 

  34. #include "all_aligned_atomic_load_store.h"
    35. 

  35. 

  36. #include "../test_and_set_t_is_ao_t.h"
    37. 

  37. /* FIXME: Is there a way to do byte-sized test-and-set?	*/
    38. 

  38. 

  39. /* FIXME: AO_nop_full should probably be implemented directly.	*/
    40. 

  40. /* It appears that certain BCR instructions have that effect.	*/
    41. 

  41. /* Presumably they're cheaper than CS?				*/
    42. 

  42. 

  43. AO_INLINE AO_t AO_compare_and_swap_full(volatile AO_t *addr,
    44. 

  44.                                                AO_t old, AO_t new_val)
    45. 

  45. {
    46. 

  46.   int retval;
    47. 

  47.   __asm__ __volatile__ (
    48. 

  48. # ifndef __s390x__
    49. 

  49.     "     cs  %1,%2,0(%3)\n"
    50. 

  50. # else
    51. 

  51.     "     csg %1,%2,0(%3)\n"
    52. 

  52. # endif
    53. 

  53.   "     ipm %0\n"
    54. 

  54.   "     srl %0,28\n"
    55. 

  55.   : "=&d" (retval), "+d" (old)
    56. 

  56.   : "d" (new_val), "a" (addr)
    57. 

  57.   : "cc", "memory");
    58. 

  58.   return retval == 0;
    59. 

  59. }
    60. 

  60. 

  61. #define AO_HAVE_compare_and_swap_full
    62. 

  62. 

  63. /* FIXME: Add double-wide compare-and-swap for 32-bit executables.	*/
    64.