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/arch/sh/include/cpu-sh4/cpu/freq.h

http://github.com/mirrors/linux
C Header | 74 lines | 62 code | 6 blank | 6 comment | 4 complexity | 076f3432872454997b4abf23bbc0aaeb MD5 | raw file
 1/* SPDX-License-Identifier: GPL-2.0
 2 *
 3 * include/asm-sh/cpu-sh4/freq.h
 4 *
 5 * Copyright (C) 2002, 2003 Paul Mundt
 6 */
 7#ifndef __ASM_CPU_SH4_FREQ_H
 8#define __ASM_CPU_SH4_FREQ_H
 9
10#if defined(CONFIG_CPU_SUBTYPE_SH7722) || \
11    defined(CONFIG_CPU_SUBTYPE_SH7723) || \
12    defined(CONFIG_CPU_SUBTYPE_SH7343) || \
13    defined(CONFIG_CPU_SUBTYPE_SH7366)
14#define FRQCR		        0xa4150000
15#define VCLKCR			0xa4150004
16#define SCLKACR			0xa4150008
17#define SCLKBCR			0xa415000c
18#define IrDACLKCR		0xa4150010
19#define MSTPCR0			0xa4150030
20#define MSTPCR1			0xa4150034
21#define MSTPCR2			0xa4150038
22#elif defined(CONFIG_CPU_SUBTYPE_SH7757)
23#define	FRQCR			0xffc80000
24#define	OSCCR			0xffc80018
25#define	PLLCR			0xffc80024
26#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
27      defined(CONFIG_CPU_SUBTYPE_SH7780)
28#define	FRQCR			0xffc80000
29#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
30#define FRQCRA			0xa4150000
31#define FRQCRB			0xa4150004
32#define VCLKCR			0xa4150048
33
34#define FCLKACR			0xa4150008
35#define FCLKBCR			0xa415000c
36#define FRQCR			FRQCRA
37#define SCLKACR			FCLKACR
38#define SCLKBCR			FCLKBCR
39#define FCLKACR			0xa4150008
40#define FCLKBCR			0xa415000c
41#define IrDACLKCR		0xa4150018
42
43#define MSTPCR0			0xa4150030
44#define MSTPCR1			0xa4150034
45#define MSTPCR2			0xa4150038
46
47#elif defined(CONFIG_CPU_SUBTYPE_SH7734)
48#define FRQCR0			0xffc80000
49#define FRQCR2			0xffc80008
50#define FRQMR1			0xffc80014
51#define FRQMR2			0xffc80018
52#elif defined(CONFIG_CPU_SUBTYPE_SH7785)
53#define FRQCR0			0xffc80000
54#define FRQCR1			0xffc80004
55#define FRQMR1			0xffc80014
56#elif defined(CONFIG_CPU_SUBTYPE_SH7786)
57#define FRQCR0			0xffc40000
58#define FRQCR1			0xffc40004
59#define FRQMR1			0xffc40014
60#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
61#define FRQCR0			0xffc00000
62#define FRQCR1			0xffc00004
63#define FRQMR1			0xffc00014
64#else
65#define FRQCR			0xffc00000
66#define FRQCR_PSTBY		0x0200
67#define FRQCR_PLLEN		0x0400
68#define FRQCR_CKOEN		0x0800
69#endif
70#define MIN_DIVISOR_NR		0
71#define MAX_DIVISOR_NR		3
72
73#endif /* __ASM_CPU_SH4_FREQ_H */
74