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/arch/alpha/kernel/sys_wildfire.c

http://github.com/mirrors/linux
C | 347 lines | 221 code | 57 blank | 69 comment | 16 complexity | 90f87da24156d8e151ac2306ac84a296 MD5 | raw file
  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 *  linux/arch/alpha/kernel/sys_wildfire.c
  4 *
  5 *  Wildfire support.
  6 *
  7 *  Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
  8 */
  9
 10#include <linux/kernel.h>
 11#include <linux/types.h>
 12#include <linux/mm.h>
 13#include <linux/sched.h>
 14#include <linux/pci.h>
 15#include <linux/init.h>
 16#include <linux/bitops.h>
 17
 18#include <asm/ptrace.h>
 19#include <asm/dma.h>
 20#include <asm/irq.h>
 21#include <asm/mmu_context.h>
 22#include <asm/io.h>
 23#include <asm/pgtable.h>
 24#include <asm/core_wildfire.h>
 25#include <asm/hwrpb.h>
 26#include <asm/tlbflush.h>
 27
 28#include "proto.h"
 29#include "irq_impl.h"
 30#include "pci_impl.h"
 31#include "machvec_impl.h"
 32
 33static unsigned long cached_irq_mask[WILDFIRE_NR_IRQS/(sizeof(long)*8)];
 34
 35DEFINE_SPINLOCK(wildfire_irq_lock);
 36
 37static int doing_init_irq_hw = 0;
 38
 39static void
 40wildfire_update_irq_hw(unsigned int irq)
 41{
 42	int qbbno = (irq >> 8) & (WILDFIRE_MAX_QBB - 1);
 43	int pcano = (irq >> 6) & (WILDFIRE_PCA_PER_QBB - 1);
 44	wildfire_pca *pca;
 45	volatile unsigned long * enable0;
 46
 47	if (!WILDFIRE_PCA_EXISTS(qbbno, pcano)) {
 48		if (!doing_init_irq_hw) {
 49			printk(KERN_ERR "wildfire_update_irq_hw:"
 50			       " got irq %d for non-existent PCA %d"
 51			       " on QBB %d.\n",
 52			       irq, pcano, qbbno);
 53		}
 54		return;
 55	}
 56
 57	pca = WILDFIRE_pca(qbbno, pcano);
 58	enable0 = (unsigned long *) &pca->pca_int[0].enable; /* ??? */
 59
 60	*enable0 = cached_irq_mask[qbbno * WILDFIRE_PCA_PER_QBB + pcano];
 61	mb();
 62	*enable0;
 63}
 64
 65static void __init
 66wildfire_init_irq_hw(void)
 67{
 68#if 0
 69	register wildfire_pca * pca = WILDFIRE_pca(0, 0);
 70	volatile unsigned long * enable0, * enable1, * enable2, *enable3;
 71	volatile unsigned long * target0, * target1, * target2, *target3;
 72
 73	enable0 = (unsigned long *) &pca->pca_int[0].enable;
 74	enable1 = (unsigned long *) &pca->pca_int[1].enable;
 75	enable2 = (unsigned long *) &pca->pca_int[2].enable;
 76	enable3 = (unsigned long *) &pca->pca_int[3].enable;
 77
 78	target0 = (unsigned long *) &pca->pca_int[0].target;
 79	target1 = (unsigned long *) &pca->pca_int[1].target;
 80	target2 = (unsigned long *) &pca->pca_int[2].target;
 81	target3 = (unsigned long *) &pca->pca_int[3].target;
 82
 83	*enable0 = *enable1 = *enable2 = *enable3 = 0;
 84
 85	*target0 = (1UL<<8) | WILDFIRE_QBB(0);
 86	*target1 = *target2 = *target3 = 0;
 87
 88	mb();
 89
 90	*enable0; *enable1; *enable2; *enable3;
 91	*target0; *target1; *target2; *target3;
 92
 93#else
 94	int i;
 95
 96	doing_init_irq_hw = 1;
 97
 98	/* Need to update only once for every possible PCA. */
 99	for (i = 0; i < WILDFIRE_NR_IRQS; i+=WILDFIRE_IRQ_PER_PCA)
100		wildfire_update_irq_hw(i);
101
102	doing_init_irq_hw = 0;
103#endif
104}
105
106static void
107wildfire_enable_irq(struct irq_data *d)
108{
109	unsigned int irq = d->irq;
110
111	if (irq < 16)
112		i8259a_enable_irq(d);
113
114	spin_lock(&wildfire_irq_lock);
115	set_bit(irq, &cached_irq_mask);
116	wildfire_update_irq_hw(irq);
117	spin_unlock(&wildfire_irq_lock);
118}
119
120static void
121wildfire_disable_irq(struct irq_data *d)
122{
123	unsigned int irq = d->irq;
124
125	if (irq < 16)
126		i8259a_disable_irq(d);
127
128	spin_lock(&wildfire_irq_lock);
129	clear_bit(irq, &cached_irq_mask);
130	wildfire_update_irq_hw(irq);
131	spin_unlock(&wildfire_irq_lock);
132}
133
134static void
135wildfire_mask_and_ack_irq(struct irq_data *d)
136{
137	unsigned int irq = d->irq;
138
139	if (irq < 16)
140		i8259a_mask_and_ack_irq(d);
141
142	spin_lock(&wildfire_irq_lock);
143	clear_bit(irq, &cached_irq_mask);
144	wildfire_update_irq_hw(irq);
145	spin_unlock(&wildfire_irq_lock);
146}
147
148static struct irq_chip wildfire_irq_type = {
149	.name		= "WILDFIRE",
150	.irq_unmask	= wildfire_enable_irq,
151	.irq_mask	= wildfire_disable_irq,
152	.irq_mask_ack	= wildfire_mask_and_ack_irq,
153};
154
155static void __init
156wildfire_init_irq_per_pca(int qbbno, int pcano)
157{
158	int i, irq_bias;
159
160	irq_bias = qbbno * (WILDFIRE_PCA_PER_QBB * WILDFIRE_IRQ_PER_PCA)
161		 + pcano * WILDFIRE_IRQ_PER_PCA;
162
163#if 0
164	unsigned long io_bias;
165
166	/* Only need the following for first PCI bus per PCA. */
167	io_bias = WILDFIRE_IO(qbbno, pcano<<1) - WILDFIRE_IO_BIAS;
168
169	outb(0, DMA1_RESET_REG + io_bias);
170	outb(0, DMA2_RESET_REG + io_bias);
171	outb(DMA_MODE_CASCADE, DMA2_MODE_REG + io_bias);
172	outb(0, DMA2_MASK_REG + io_bias);
173#endif
174
175#if 0
176	/* ??? Not sure how to do this, yet... */
177	init_i8259a_irqs(); /* ??? */
178#endif
179
180	for (i = 0; i < 16; ++i) {
181		if (i == 2)
182			continue;
183		irq_set_chip_and_handler(i + irq_bias, &wildfire_irq_type,
184					 handle_level_irq);
185		irq_set_status_flags(i + irq_bias, IRQ_LEVEL);
186	}
187
188	irq_set_chip_and_handler(36 + irq_bias, &wildfire_irq_type,
189				 handle_level_irq);
190	irq_set_status_flags(36 + irq_bias, IRQ_LEVEL);
191	for (i = 40; i < 64; ++i) {
192		irq_set_chip_and_handler(i + irq_bias, &wildfire_irq_type,
193					 handle_level_irq);
194		irq_set_status_flags(i + irq_bias, IRQ_LEVEL);
195	}
196
197	if (request_irq(32 + irq_bias, no_action, 0, "isa_enable", NULL))
198		pr_err("Failed to register isa_enable interrupt\n");
199}
200
201static void __init
202wildfire_init_irq(void)
203{
204	int qbbno, pcano;
205
206#if 1
207	wildfire_init_irq_hw();
208	init_i8259a_irqs();
209#endif
210
211	for (qbbno = 0; qbbno < WILDFIRE_MAX_QBB; qbbno++) {
212	  if (WILDFIRE_QBB_EXISTS(qbbno)) {
213	    for (pcano = 0; pcano < WILDFIRE_PCA_PER_QBB; pcano++) {
214	      if (WILDFIRE_PCA_EXISTS(qbbno, pcano)) {
215		wildfire_init_irq_per_pca(qbbno, pcano);
216	      }
217	    }
218	  }
219	}
220}
221
222static void 
223wildfire_device_interrupt(unsigned long vector)
224{
225	int irq;
226
227	irq = (vector - 0x800) >> 4;
228
229	/*
230	 * bits 10-8:	source QBB ID
231	 * bits 7-6:	PCA
232	 * bits 5-0:	irq in PCA
233	 */
234
235	handle_irq(irq);
236	return;
237}
238
239/*
240 * PCI Fixup configuration.
241 *
242 * Summary per PCA (2 PCI or HIPPI buses):
243 *
244 * Bit      Meaning
245 * 0-15     ISA
246 *
247 *32        ISA summary
248 *33        SMI
249 *34        NMI
250 *36        builtin QLogic SCSI (or slot 0 if no IO module)
251 *40        Interrupt Line A from slot 2 PCI0
252 *41        Interrupt Line B from slot 2 PCI0
253 *42        Interrupt Line C from slot 2 PCI0
254 *43        Interrupt Line D from slot 2 PCI0
255 *44        Interrupt Line A from slot 3 PCI0
256 *45        Interrupt Line B from slot 3 PCI0
257 *46        Interrupt Line C from slot 3 PCI0
258 *47        Interrupt Line D from slot 3 PCI0
259 *
260 *48        Interrupt Line A from slot 4 PCI1
261 *49        Interrupt Line B from slot 4 PCI1
262 *50        Interrupt Line C from slot 4 PCI1
263 *51        Interrupt Line D from slot 4 PCI1
264 *52        Interrupt Line A from slot 5 PCI1
265 *53        Interrupt Line B from slot 5 PCI1
266 *54        Interrupt Line C from slot 5 PCI1
267 *55        Interrupt Line D from slot 5 PCI1
268 *56        Interrupt Line A from slot 6 PCI1
269 *57        Interrupt Line B from slot 6 PCI1
270 *58        Interrupt Line C from slot 6 PCI1
271 *50        Interrupt Line D from slot 6 PCI1
272 *60        Interrupt Line A from slot 7 PCI1
273 *61        Interrupt Line B from slot 7 PCI1
274 *62        Interrupt Line C from slot 7 PCI1
275 *63        Interrupt Line D from slot 7 PCI1
276 * 
277 *
278 * IdSel	
279 *   0	 Cypress Bridge I/O (ISA summary interrupt)
280 *   1	 64 bit PCI 0 option slot 1 (SCSI QLogic builtin)
281 *   2	 64 bit PCI 0 option slot 2
282 *   3	 64 bit PCI 0 option slot 3
283 *   4	 64 bit PCI 1 option slot 4
284 *   5	 64 bit PCI 1 option slot 5
285 *   6	 64 bit PCI 1 option slot 6
286 *   7	 64 bit PCI 1 option slot 7
287 */
288
289static int
290wildfire_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
291{
292	static char irq_tab[8][5] = {
293		/*INT    INTA   INTB   INTC   INTD */
294		{ -1,    -1,    -1,    -1,    -1}, /* IdSel 0 ISA Bridge */
295		{ 36,    36,    36+1, 36+2, 36+3}, /* IdSel 1 SCSI builtin */
296		{ 40,    40,    40+1, 40+2, 40+3}, /* IdSel 2 PCI 0 slot 2 */
297		{ 44,    44,    44+1, 44+2, 44+3}, /* IdSel 3 PCI 0 slot 3 */
298		{ 48,    48,    48+1, 48+2, 48+3}, /* IdSel 4 PCI 1 slot 4 */
299		{ 52,    52,    52+1, 52+2, 52+3}, /* IdSel 5 PCI 1 slot 5 */
300		{ 56,    56,    56+1, 56+2, 56+3}, /* IdSel 6 PCI 1 slot 6 */
301		{ 60,    60,    60+1, 60+2, 60+3}, /* IdSel 7 PCI 1 slot 7 */
302	};
303	long min_idsel = 0, max_idsel = 7, irqs_per_slot = 5;
304
305	struct pci_controller *hose = dev->sysdata;
306	int irq = COMMON_TABLE_LOOKUP;
307
308	if (irq > 0) {
309		int qbbno = hose->index >> 3;
310		int pcano = (hose->index >> 1) & 3;
311		irq += (qbbno << 8) + (pcano << 6);
312	}
313	return irq;
314}
315
316
317/*
318 * The System Vectors
319 */
320
321struct alpha_machine_vector wildfire_mv __initmv = {
322	.vector_name		= "WILDFIRE",
323	DO_EV6_MMU,
324	DO_DEFAULT_RTC,
325	DO_WILDFIRE_IO,
326	.machine_check		= wildfire_machine_check,
327	.max_isa_dma_address	= ALPHA_MAX_ISA_DMA_ADDRESS,
328	.min_io_address		= DEFAULT_IO_BASE,
329	.min_mem_address	= DEFAULT_MEM_BASE,
330
331	.nr_irqs		= WILDFIRE_NR_IRQS,
332	.device_interrupt	= wildfire_device_interrupt,
333
334	.init_arch		= wildfire_init_arch,
335	.init_irq		= wildfire_init_irq,
336	.init_rtc		= common_init_rtc,
337	.init_pci		= common_init_pci,
338	.kill_arch		= wildfire_kill_arch,
339	.pci_map_irq		= wildfire_map_irq,
340	.pci_swizzle		= common_swizzle,
341
342	.pa_to_nid		= wildfire_pa_to_nid,
343	.cpuid_to_nid		= wildfire_cpuid_to_nid,
344	.node_mem_start		= wildfire_node_mem_start,
345	.node_mem_size		= wildfire_node_mem_size,
346};
347ALIAS_MV(wildfire)