/arch/alpha/kernel/core_mcpcia.c

http://github.com/mirrors/linux · C · 616 lines · 442 code · 86 blank · 88 comment · 30 complexity · fc126be77c0473a84a40644d24fee996 MD5 · raw file

  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * linux/arch/alpha/kernel/core_mcpcia.c
  4. *
  5. * Based on code written by David A Rusling (david.rusling@reo.mts.dec.com).
  6. *
  7. * Code common to all MCbus-PCI Adaptor core logic chipsets
  8. */
  9. #define __EXTERN_INLINE inline
  10. #include <asm/io.h>
  11. #include <asm/core_mcpcia.h>
  12. #undef __EXTERN_INLINE
  13. #include <linux/types.h>
  14. #include <linux/pci.h>
  15. #include <linux/sched.h>
  16. #include <linux/init.h>
  17. #include <linux/delay.h>
  18. #include <asm/ptrace.h>
  19. #include "proto.h"
  20. #include "pci_impl.h"
  21. /*
  22. * NOTE: Herein lie back-to-back mb instructions. They are magic.
  23. * One plausible explanation is that the i/o controller does not properly
  24. * handle the system transaction. Another involves timing. Ho hum.
  25. */
  26. /*
  27. * BIOS32-style PCI interface:
  28. */
  29. #define DEBUG_CFG 0
  30. #if DEBUG_CFG
  31. # define DBG_CFG(args) printk args
  32. #else
  33. # define DBG_CFG(args)
  34. #endif
  35. /*
  36. * Given a bus, device, and function number, compute resulting
  37. * configuration space address and setup the MCPCIA_HAXR2 register
  38. * accordingly. It is therefore not safe to have concurrent
  39. * invocations to configuration space access routines, but there
  40. * really shouldn't be any need for this.
  41. *
  42. * Type 0:
  43. *
  44. * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
  45. * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
  46. * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
  47. * | | |D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|0|
  48. * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
  49. *
  50. * 31:11 Device select bit.
  51. * 10:8 Function number
  52. * 7:2 Register number
  53. *
  54. * Type 1:
  55. *
  56. * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
  57. * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
  58. * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
  59. * | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1|
  60. * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
  61. *
  62. * 31:24 reserved
  63. * 23:16 bus number (8 bits = 128 possible buses)
  64. * 15:11 Device number (5 bits)
  65. * 10:8 function number
  66. * 7:2 register number
  67. *
  68. * Notes:
  69. * The function number selects which function of a multi-function device
  70. * (e.g., SCSI and Ethernet).
  71. *
  72. * The register selects a DWORD (32 bit) register offset. Hence it
  73. * doesn't get shifted by 2 bits as we want to "drop" the bottom two
  74. * bits.
  75. */
  76. static unsigned int
  77. conf_read(unsigned long addr, unsigned char type1,
  78. struct pci_controller *hose)
  79. {
  80. unsigned long flags;
  81. unsigned long mid = MCPCIA_HOSE2MID(hose->index);
  82. unsigned int stat0, value, cpu;
  83. cpu = smp_processor_id();
  84. local_irq_save(flags);
  85. DBG_CFG(("conf_read(addr=0x%lx, type1=%d, hose=%d)\n",
  86. addr, type1, mid));
  87. /* Reset status register to avoid losing errors. */
  88. stat0 = *(vuip)MCPCIA_CAP_ERR(mid);
  89. *(vuip)MCPCIA_CAP_ERR(mid) = stat0;
  90. mb();
  91. *(vuip)MCPCIA_CAP_ERR(mid);
  92. DBG_CFG(("conf_read: MCPCIA_CAP_ERR(%d) was 0x%x\n", mid, stat0));
  93. mb();
  94. draina();
  95. mcheck_expected(cpu) = 1;
  96. mcheck_taken(cpu) = 0;
  97. mcheck_extra(cpu) = mid;
  98. mb();
  99. /* Access configuration space. */
  100. value = *((vuip)addr);
  101. mb();
  102. mb(); /* magic */
  103. if (mcheck_taken(cpu)) {
  104. mcheck_taken(cpu) = 0;
  105. value = 0xffffffffU;
  106. mb();
  107. }
  108. mcheck_expected(cpu) = 0;
  109. mb();
  110. DBG_CFG(("conf_read(): finished\n"));
  111. local_irq_restore(flags);
  112. return value;
  113. }
  114. static void
  115. conf_write(unsigned long addr, unsigned int value, unsigned char type1,
  116. struct pci_controller *hose)
  117. {
  118. unsigned long flags;
  119. unsigned long mid = MCPCIA_HOSE2MID(hose->index);
  120. unsigned int stat0, cpu;
  121. cpu = smp_processor_id();
  122. local_irq_save(flags); /* avoid getting hit by machine check */
  123. /* Reset status register to avoid losing errors. */
  124. stat0 = *(vuip)MCPCIA_CAP_ERR(mid);
  125. *(vuip)MCPCIA_CAP_ERR(mid) = stat0; mb();
  126. *(vuip)MCPCIA_CAP_ERR(mid);
  127. DBG_CFG(("conf_write: MCPCIA CAP_ERR(%d) was 0x%x\n", mid, stat0));
  128. draina();
  129. mcheck_expected(cpu) = 1;
  130. mcheck_extra(cpu) = mid;
  131. mb();
  132. /* Access configuration space. */
  133. *((vuip)addr) = value;
  134. mb();
  135. mb(); /* magic */
  136. *(vuip)MCPCIA_CAP_ERR(mid); /* read to force the write */
  137. mcheck_expected(cpu) = 0;
  138. mb();
  139. DBG_CFG(("conf_write(): finished\n"));
  140. local_irq_restore(flags);
  141. }
  142. static int
  143. mk_conf_addr(struct pci_bus *pbus, unsigned int devfn, int where,
  144. struct pci_controller *hose, unsigned long *pci_addr,
  145. unsigned char *type1)
  146. {
  147. u8 bus = pbus->number;
  148. unsigned long addr;
  149. DBG_CFG(("mk_conf_addr(bus=%d,devfn=0x%x,hose=%d,where=0x%x,"
  150. " pci_addr=0x%p, type1=0x%p)\n",
  151. bus, devfn, hose->index, where, pci_addr, type1));
  152. /* Type 1 configuration cycle for *ALL* busses. */
  153. *type1 = 1;
  154. if (!pbus->parent) /* No parent means peer PCI bus. */
  155. bus = 0;
  156. addr = (bus << 16) | (devfn << 8) | (where);
  157. addr <<= 5; /* swizzle for SPARSE */
  158. addr |= hose->config_space_base;
  159. *pci_addr = addr;
  160. DBG_CFG(("mk_conf_addr: returning pci_addr 0x%lx\n", addr));
  161. return 0;
  162. }
  163. static int
  164. mcpcia_read_config(struct pci_bus *bus, unsigned int devfn, int where,
  165. int size, u32 *value)
  166. {
  167. struct pci_controller *hose = bus->sysdata;
  168. unsigned long addr, w;
  169. unsigned char type1;
  170. if (mk_conf_addr(bus, devfn, where, hose, &addr, &type1))
  171. return PCIBIOS_DEVICE_NOT_FOUND;
  172. addr |= (size - 1) * 8;
  173. w = conf_read(addr, type1, hose);
  174. switch (size) {
  175. case 1:
  176. *value = __kernel_extbl(w, where & 3);
  177. break;
  178. case 2:
  179. *value = __kernel_extwl(w, where & 3);
  180. break;
  181. case 4:
  182. *value = w;
  183. break;
  184. }
  185. return PCIBIOS_SUCCESSFUL;
  186. }
  187. static int
  188. mcpcia_write_config(struct pci_bus *bus, unsigned int devfn, int where,
  189. int size, u32 value)
  190. {
  191. struct pci_controller *hose = bus->sysdata;
  192. unsigned long addr;
  193. unsigned char type1;
  194. if (mk_conf_addr(bus, devfn, where, hose, &addr, &type1))
  195. return PCIBIOS_DEVICE_NOT_FOUND;
  196. addr |= (size - 1) * 8;
  197. value = __kernel_insql(value, where & 3);
  198. conf_write(addr, value, type1, hose);
  199. return PCIBIOS_SUCCESSFUL;
  200. }
  201. struct pci_ops mcpcia_pci_ops =
  202. {
  203. .read = mcpcia_read_config,
  204. .write = mcpcia_write_config,
  205. };
  206. void
  207. mcpcia_pci_tbi(struct pci_controller *hose, dma_addr_t start, dma_addr_t end)
  208. {
  209. wmb();
  210. *(vuip)MCPCIA_SG_TBIA(MCPCIA_HOSE2MID(hose->index)) = 0;
  211. mb();
  212. }
  213. static int __init
  214. mcpcia_probe_hose(int h)
  215. {
  216. int cpu = smp_processor_id();
  217. int mid = MCPCIA_HOSE2MID(h);
  218. unsigned int pci_rev;
  219. /* Gotta be REAL careful. If hose is absent, we get an mcheck. */
  220. mb();
  221. mb();
  222. draina();
  223. wrmces(7);
  224. mcheck_expected(cpu) = 2; /* indicates probing */
  225. mcheck_taken(cpu) = 0;
  226. mcheck_extra(cpu) = mid;
  227. mb();
  228. /* Access the bus revision word. */
  229. pci_rev = *(vuip)MCPCIA_REV(mid);
  230. mb();
  231. mb(); /* magic */
  232. if (mcheck_taken(cpu)) {
  233. mcheck_taken(cpu) = 0;
  234. pci_rev = 0xffffffff;
  235. mb();
  236. }
  237. mcheck_expected(cpu) = 0;
  238. mb();
  239. return (pci_rev >> 16) == PCI_CLASS_BRIDGE_HOST;
  240. }
  241. static void __init
  242. mcpcia_new_hose(int h)
  243. {
  244. struct pci_controller *hose;
  245. struct resource *io, *mem, *hae_mem;
  246. int mid = MCPCIA_HOSE2MID(h);
  247. hose = alloc_pci_controller();
  248. if (h == 0)
  249. pci_isa_hose = hose;
  250. io = alloc_resource();
  251. mem = alloc_resource();
  252. hae_mem = alloc_resource();
  253. hose->io_space = io;
  254. hose->mem_space = hae_mem;
  255. hose->sparse_mem_base = MCPCIA_SPARSE(mid) - IDENT_ADDR;
  256. hose->dense_mem_base = MCPCIA_DENSE(mid) - IDENT_ADDR;
  257. hose->sparse_io_base = MCPCIA_IO(mid) - IDENT_ADDR;
  258. hose->dense_io_base = 0;
  259. hose->config_space_base = MCPCIA_CONF(mid);
  260. hose->index = h;
  261. io->start = MCPCIA_IO(mid) - MCPCIA_IO_BIAS;
  262. io->end = io->start + 0xffff;
  263. io->name = pci_io_names[h];
  264. io->flags = IORESOURCE_IO;
  265. mem->start = MCPCIA_DENSE(mid) - MCPCIA_MEM_BIAS;
  266. mem->end = mem->start + 0xffffffff;
  267. mem->name = pci_mem_names[h];
  268. mem->flags = IORESOURCE_MEM;
  269. hae_mem->start = mem->start;
  270. hae_mem->end = mem->start + MCPCIA_MEM_MASK;
  271. hae_mem->name = pci_hae0_name;
  272. hae_mem->flags = IORESOURCE_MEM;
  273. if (request_resource(&ioport_resource, io) < 0)
  274. printk(KERN_ERR "Failed to request IO on hose %d\n", h);
  275. if (request_resource(&iomem_resource, mem) < 0)
  276. printk(KERN_ERR "Failed to request MEM on hose %d\n", h);
  277. if (request_resource(mem, hae_mem) < 0)
  278. printk(KERN_ERR "Failed to request HAE_MEM on hose %d\n", h);
  279. }
  280. static void
  281. mcpcia_pci_clr_err(int mid)
  282. {
  283. *(vuip)MCPCIA_CAP_ERR(mid);
  284. *(vuip)MCPCIA_CAP_ERR(mid) = 0xffffffff; /* Clear them all. */
  285. mb();
  286. *(vuip)MCPCIA_CAP_ERR(mid); /* Re-read for force write. */
  287. }
  288. static void __init
  289. mcpcia_startup_hose(struct pci_controller *hose)
  290. {
  291. int mid = MCPCIA_HOSE2MID(hose->index);
  292. unsigned int tmp;
  293. mcpcia_pci_clr_err(mid);
  294. /*
  295. * Set up error reporting.
  296. */
  297. tmp = *(vuip)MCPCIA_CAP_ERR(mid);
  298. tmp |= 0x0006; /* master/target abort */
  299. *(vuip)MCPCIA_CAP_ERR(mid) = tmp;
  300. mb();
  301. tmp = *(vuip)MCPCIA_CAP_ERR(mid);
  302. /*
  303. * Set up the PCI->physical memory translation windows.
  304. *
  305. * Window 0 is scatter-gather 8MB at 8MB (for isa)
  306. * Window 1 is scatter-gather (up to) 1GB at 1GB (for pci)
  307. * Window 2 is direct access 2GB at 2GB
  308. */
  309. hose->sg_isa = iommu_arena_new(hose, 0x00800000, 0x00800000,
  310. SMP_CACHE_BYTES);
  311. hose->sg_pci = iommu_arena_new(hose, 0x40000000,
  312. size_for_memory(0x40000000),
  313. SMP_CACHE_BYTES);
  314. __direct_map_base = 0x80000000;
  315. __direct_map_size = 0x80000000;
  316. *(vuip)MCPCIA_W0_BASE(mid) = hose->sg_isa->dma_base | 3;
  317. *(vuip)MCPCIA_W0_MASK(mid) = (hose->sg_isa->size - 1) & 0xfff00000;
  318. *(vuip)MCPCIA_T0_BASE(mid) = virt_to_phys(hose->sg_isa->ptes) >> 8;
  319. *(vuip)MCPCIA_W1_BASE(mid) = hose->sg_pci->dma_base | 3;
  320. *(vuip)MCPCIA_W1_MASK(mid) = (hose->sg_pci->size - 1) & 0xfff00000;
  321. *(vuip)MCPCIA_T1_BASE(mid) = virt_to_phys(hose->sg_pci->ptes) >> 8;
  322. *(vuip)MCPCIA_W2_BASE(mid) = __direct_map_base | 1;
  323. *(vuip)MCPCIA_W2_MASK(mid) = (__direct_map_size - 1) & 0xfff00000;
  324. *(vuip)MCPCIA_T2_BASE(mid) = 0;
  325. *(vuip)MCPCIA_W3_BASE(mid) = 0x0;
  326. mcpcia_pci_tbi(hose, 0, -1);
  327. *(vuip)MCPCIA_HBASE(mid) = 0x0;
  328. mb();
  329. *(vuip)MCPCIA_HAE_MEM(mid) = 0U;
  330. mb();
  331. *(vuip)MCPCIA_HAE_MEM(mid); /* read it back. */
  332. *(vuip)MCPCIA_HAE_IO(mid) = 0;
  333. mb();
  334. *(vuip)MCPCIA_HAE_IO(mid); /* read it back. */
  335. }
  336. void __init
  337. mcpcia_init_arch(void)
  338. {
  339. /* With multiple PCI busses, we play with I/O as physical addrs. */
  340. ioport_resource.end = ~0UL;
  341. /* Allocate hose 0. That's the one that all the ISA junk hangs
  342. off of, from which we'll be registering stuff here in a bit.
  343. Other hose detection is done in mcpcia_init_hoses, which is
  344. called from init_IRQ. */
  345. mcpcia_new_hose(0);
  346. }
  347. /* This is called from init_IRQ, since we cannot take interrupts
  348. before then. Which means we cannot do this in init_arch. */
  349. void __init
  350. mcpcia_init_hoses(void)
  351. {
  352. struct pci_controller *hose;
  353. int hose_count;
  354. int h;
  355. /* First, find how many hoses we have. */
  356. hose_count = 0;
  357. for (h = 0; h < MCPCIA_MAX_HOSES; ++h) {
  358. if (mcpcia_probe_hose(h)) {
  359. if (h != 0)
  360. mcpcia_new_hose(h);
  361. hose_count++;
  362. }
  363. }
  364. printk("mcpcia_init_hoses: found %d hoses\n", hose_count);
  365. /* Now do init for each hose. */
  366. for (hose = hose_head; hose; hose = hose->next)
  367. mcpcia_startup_hose(hose);
  368. }
  369. static void
  370. mcpcia_print_uncorrectable(struct el_MCPCIA_uncorrected_frame_mcheck *logout)
  371. {
  372. struct el_common_EV5_uncorrectable_mcheck *frame;
  373. int i;
  374. frame = &logout->procdata;
  375. /* Print PAL fields */
  376. for (i = 0; i < 24; i += 2) {
  377. printk(" paltmp[%d-%d] = %16lx %16lx\n",
  378. i, i+1, frame->paltemp[i], frame->paltemp[i+1]);
  379. }
  380. for (i = 0; i < 8; i += 2) {
  381. printk(" shadow[%d-%d] = %16lx %16lx\n",
  382. i, i+1, frame->shadow[i],
  383. frame->shadow[i+1]);
  384. }
  385. printk(" Addr of excepting instruction = %16lx\n",
  386. frame->exc_addr);
  387. printk(" Summary of arithmetic traps = %16lx\n",
  388. frame->exc_sum);
  389. printk(" Exception mask = %16lx\n",
  390. frame->exc_mask);
  391. printk(" Base address for PALcode = %16lx\n",
  392. frame->pal_base);
  393. printk(" Interrupt Status Reg = %16lx\n",
  394. frame->isr);
  395. printk(" CURRENT SETUP OF EV5 IBOX = %16lx\n",
  396. frame->icsr);
  397. printk(" I-CACHE Reg %s parity error = %16lx\n",
  398. (frame->ic_perr_stat & 0x800L) ?
  399. "Data" : "Tag",
  400. frame->ic_perr_stat);
  401. printk(" D-CACHE error Reg = %16lx\n",
  402. frame->dc_perr_stat);
  403. if (frame->dc_perr_stat & 0x2) {
  404. switch (frame->dc_perr_stat & 0x03c) {
  405. case 8:
  406. printk(" Data error in bank 1\n");
  407. break;
  408. case 4:
  409. printk(" Data error in bank 0\n");
  410. break;
  411. case 20:
  412. printk(" Tag error in bank 1\n");
  413. break;
  414. case 10:
  415. printk(" Tag error in bank 0\n");
  416. break;
  417. }
  418. }
  419. printk(" Effective VA = %16lx\n",
  420. frame->va);
  421. printk(" Reason for D-stream = %16lx\n",
  422. frame->mm_stat);
  423. printk(" EV5 SCache address = %16lx\n",
  424. frame->sc_addr);
  425. printk(" EV5 SCache TAG/Data parity = %16lx\n",
  426. frame->sc_stat);
  427. printk(" EV5 BC_TAG_ADDR = %16lx\n",
  428. frame->bc_tag_addr);
  429. printk(" EV5 EI_ADDR: Phys addr of Xfer = %16lx\n",
  430. frame->ei_addr);
  431. printk(" Fill Syndrome = %16lx\n",
  432. frame->fill_syndrome);
  433. printk(" EI_STAT reg = %16lx\n",
  434. frame->ei_stat);
  435. printk(" LD_LOCK = %16lx\n",
  436. frame->ld_lock);
  437. }
  438. static void
  439. mcpcia_print_system_area(unsigned long la_ptr)
  440. {
  441. struct el_common *frame;
  442. struct pci_controller *hose;
  443. struct IOD_subpacket {
  444. unsigned long base;
  445. unsigned int whoami;
  446. unsigned int rsvd1;
  447. unsigned int pci_rev;
  448. unsigned int cap_ctrl;
  449. unsigned int hae_mem;
  450. unsigned int hae_io;
  451. unsigned int int_ctl;
  452. unsigned int int_reg;
  453. unsigned int int_mask0;
  454. unsigned int int_mask1;
  455. unsigned int mc_err0;
  456. unsigned int mc_err1;
  457. unsigned int cap_err;
  458. unsigned int rsvd2;
  459. unsigned int pci_err1;
  460. unsigned int mdpa_stat;
  461. unsigned int mdpa_syn;
  462. unsigned int mdpb_stat;
  463. unsigned int mdpb_syn;
  464. unsigned int rsvd3;
  465. unsigned int rsvd4;
  466. unsigned int rsvd5;
  467. } *iodpp;
  468. frame = (struct el_common *)la_ptr;
  469. iodpp = (struct IOD_subpacket *) (la_ptr + frame->sys_offset);
  470. for (hose = hose_head; hose; hose = hose->next, iodpp++) {
  471. printk("IOD %d Register Subpacket - Bridge Base Address %16lx\n",
  472. hose->index, iodpp->base);
  473. printk(" WHOAMI = %8x\n", iodpp->whoami);
  474. printk(" PCI_REV = %8x\n", iodpp->pci_rev);
  475. printk(" CAP_CTRL = %8x\n", iodpp->cap_ctrl);
  476. printk(" HAE_MEM = %8x\n", iodpp->hae_mem);
  477. printk(" HAE_IO = %8x\n", iodpp->hae_io);
  478. printk(" INT_CTL = %8x\n", iodpp->int_ctl);
  479. printk(" INT_REG = %8x\n", iodpp->int_reg);
  480. printk(" INT_MASK0 = %8x\n", iodpp->int_mask0);
  481. printk(" INT_MASK1 = %8x\n", iodpp->int_mask1);
  482. printk(" MC_ERR0 = %8x\n", iodpp->mc_err0);
  483. printk(" MC_ERR1 = %8x\n", iodpp->mc_err1);
  484. printk(" CAP_ERR = %8x\n", iodpp->cap_err);
  485. printk(" PCI_ERR1 = %8x\n", iodpp->pci_err1);
  486. printk(" MDPA_STAT = %8x\n", iodpp->mdpa_stat);
  487. printk(" MDPA_SYN = %8x\n", iodpp->mdpa_syn);
  488. printk(" MDPB_STAT = %8x\n", iodpp->mdpb_stat);
  489. printk(" MDPB_SYN = %8x\n", iodpp->mdpb_syn);
  490. }
  491. }
  492. void
  493. mcpcia_machine_check(unsigned long vector, unsigned long la_ptr)
  494. {
  495. struct el_MCPCIA_uncorrected_frame_mcheck *mchk_logout;
  496. unsigned int cpu = smp_processor_id();
  497. int expected;
  498. mchk_logout = (struct el_MCPCIA_uncorrected_frame_mcheck *)la_ptr;
  499. expected = mcheck_expected(cpu);
  500. mb();
  501. mb(); /* magic */
  502. draina();
  503. switch (expected) {
  504. case 0:
  505. {
  506. /* FIXME: how do we figure out which hose the
  507. error was on? */
  508. struct pci_controller *hose;
  509. for (hose = hose_head; hose; hose = hose->next)
  510. mcpcia_pci_clr_err(MCPCIA_HOSE2MID(hose->index));
  511. break;
  512. }
  513. case 1:
  514. mcpcia_pci_clr_err(mcheck_extra(cpu));
  515. break;
  516. default:
  517. /* Otherwise, we're being called from mcpcia_probe_hose
  518. and there's no hose clear an error from. */
  519. break;
  520. }
  521. wrmces(0x7);
  522. mb();
  523. process_mcheck_info(vector, la_ptr, "MCPCIA", expected != 0);
  524. if (!expected && vector != 0x620 && vector != 0x630) {
  525. mcpcia_print_uncorrectable(mchk_logout);
  526. mcpcia_print_system_area(la_ptr);
  527. }
  528. }