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/arch/mips/kernel/asm-offsets.c

http://github.com/mirrors/linux
C | 405 lines | 372 code | 22 blank | 11 comment | 0 complexity | ac4010d2e6a7261a8e9225186821778f MD5 | raw file
  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * asm-offsets.c: Calculate pt_regs and task_struct offsets.
  4 *
  5 * Copyright (C) 1996 David S. Miller
  6 * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002, 2003 Ralf Baechle
  7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
  8 *
  9 * Kevin Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
 10 * Copyright (C) 2000 MIPS Technologies, Inc.
 11 */
 12#include <linux/compat.h>
 13#include <linux/types.h>
 14#include <linux/sched.h>
 15#include <linux/mm.h>
 16#include <linux/kbuild.h>
 17#include <linux/suspend.h>
 18#include <asm/cpu-info.h>
 19#include <asm/pm.h>
 20#include <asm/ptrace.h>
 21#include <asm/processor.h>
 22#include <asm/smp-cps.h>
 23
 24#include <linux/kvm_host.h>
 25
 26void output_ptreg_defines(void)
 27{
 28	COMMENT("MIPS pt_regs offsets.");
 29	OFFSET(PT_R0, pt_regs, regs[0]);
 30	OFFSET(PT_R1, pt_regs, regs[1]);
 31	OFFSET(PT_R2, pt_regs, regs[2]);
 32	OFFSET(PT_R3, pt_regs, regs[3]);
 33	OFFSET(PT_R4, pt_regs, regs[4]);
 34	OFFSET(PT_R5, pt_regs, regs[5]);
 35	OFFSET(PT_R6, pt_regs, regs[6]);
 36	OFFSET(PT_R7, pt_regs, regs[7]);
 37	OFFSET(PT_R8, pt_regs, regs[8]);
 38	OFFSET(PT_R9, pt_regs, regs[9]);
 39	OFFSET(PT_R10, pt_regs, regs[10]);
 40	OFFSET(PT_R11, pt_regs, regs[11]);
 41	OFFSET(PT_R12, pt_regs, regs[12]);
 42	OFFSET(PT_R13, pt_regs, regs[13]);
 43	OFFSET(PT_R14, pt_regs, regs[14]);
 44	OFFSET(PT_R15, pt_regs, regs[15]);
 45	OFFSET(PT_R16, pt_regs, regs[16]);
 46	OFFSET(PT_R17, pt_regs, regs[17]);
 47	OFFSET(PT_R18, pt_regs, regs[18]);
 48	OFFSET(PT_R19, pt_regs, regs[19]);
 49	OFFSET(PT_R20, pt_regs, regs[20]);
 50	OFFSET(PT_R21, pt_regs, regs[21]);
 51	OFFSET(PT_R22, pt_regs, regs[22]);
 52	OFFSET(PT_R23, pt_regs, regs[23]);
 53	OFFSET(PT_R24, pt_regs, regs[24]);
 54	OFFSET(PT_R25, pt_regs, regs[25]);
 55	OFFSET(PT_R26, pt_regs, regs[26]);
 56	OFFSET(PT_R27, pt_regs, regs[27]);
 57	OFFSET(PT_R28, pt_regs, regs[28]);
 58	OFFSET(PT_R29, pt_regs, regs[29]);
 59	OFFSET(PT_R30, pt_regs, regs[30]);
 60	OFFSET(PT_R31, pt_regs, regs[31]);
 61	OFFSET(PT_LO, pt_regs, lo);
 62	OFFSET(PT_HI, pt_regs, hi);
 63#ifdef CONFIG_CPU_HAS_SMARTMIPS
 64	OFFSET(PT_ACX, pt_regs, acx);
 65#endif
 66	OFFSET(PT_EPC, pt_regs, cp0_epc);
 67	OFFSET(PT_BVADDR, pt_regs, cp0_badvaddr);
 68	OFFSET(PT_STATUS, pt_regs, cp0_status);
 69	OFFSET(PT_CAUSE, pt_regs, cp0_cause);
 70#ifdef CONFIG_CPU_CAVIUM_OCTEON
 71	OFFSET(PT_MPL, pt_regs, mpl);
 72	OFFSET(PT_MTP, pt_regs, mtp);
 73#endif /* CONFIG_CPU_CAVIUM_OCTEON */
 74	DEFINE(PT_SIZE, sizeof(struct pt_regs));
 75	BLANK();
 76}
 77
 78void output_task_defines(void)
 79{
 80	COMMENT("MIPS task_struct offsets.");
 81	OFFSET(TASK_STATE, task_struct, state);
 82	OFFSET(TASK_THREAD_INFO, task_struct, stack);
 83	OFFSET(TASK_FLAGS, task_struct, flags);
 84	OFFSET(TASK_MM, task_struct, mm);
 85	OFFSET(TASK_PID, task_struct, pid);
 86#if defined(CONFIG_STACKPROTECTOR)
 87	OFFSET(TASK_STACK_CANARY, task_struct, stack_canary);
 88#endif
 89	DEFINE(TASK_STRUCT_SIZE, sizeof(struct task_struct));
 90	BLANK();
 91}
 92
 93void output_thread_info_defines(void)
 94{
 95	COMMENT("MIPS thread_info offsets.");
 96	OFFSET(TI_TASK, thread_info, task);
 97	OFFSET(TI_FLAGS, thread_info, flags);
 98	OFFSET(TI_TP_VALUE, thread_info, tp_value);
 99	OFFSET(TI_CPU, thread_info, cpu);
100	OFFSET(TI_PRE_COUNT, thread_info, preempt_count);
101	OFFSET(TI_ADDR_LIMIT, thread_info, addr_limit);
102	OFFSET(TI_REGS, thread_info, regs);
103	DEFINE(_THREAD_SIZE, THREAD_SIZE);
104	DEFINE(_THREAD_MASK, THREAD_MASK);
105	DEFINE(_IRQ_STACK_SIZE, IRQ_STACK_SIZE);
106	DEFINE(_IRQ_STACK_START, IRQ_STACK_START);
107	BLANK();
108}
109
110void output_thread_defines(void)
111{
112	COMMENT("MIPS specific thread_struct offsets.");
113	OFFSET(THREAD_REG16, task_struct, thread.reg16);
114	OFFSET(THREAD_REG17, task_struct, thread.reg17);
115	OFFSET(THREAD_REG18, task_struct, thread.reg18);
116	OFFSET(THREAD_REG19, task_struct, thread.reg19);
117	OFFSET(THREAD_REG20, task_struct, thread.reg20);
118	OFFSET(THREAD_REG21, task_struct, thread.reg21);
119	OFFSET(THREAD_REG22, task_struct, thread.reg22);
120	OFFSET(THREAD_REG23, task_struct, thread.reg23);
121	OFFSET(THREAD_REG29, task_struct, thread.reg29);
122	OFFSET(THREAD_REG30, task_struct, thread.reg30);
123	OFFSET(THREAD_REG31, task_struct, thread.reg31);
124	OFFSET(THREAD_STATUS, task_struct,
125	       thread.cp0_status);
126
127	OFFSET(THREAD_BVADDR, task_struct, \
128	       thread.cp0_badvaddr);
129	OFFSET(THREAD_BUADDR, task_struct, \
130	       thread.cp0_baduaddr);
131	OFFSET(THREAD_ECODE, task_struct, \
132	       thread.error_code);
133	OFFSET(THREAD_TRAPNO, task_struct, thread.trap_nr);
134	BLANK();
135}
136
137#ifdef CONFIG_MIPS_FP_SUPPORT
138void output_thread_fpu_defines(void)
139{
140	OFFSET(THREAD_FPU, task_struct, thread.fpu);
141
142	OFFSET(THREAD_FPR0, task_struct, thread.fpu.fpr[0]);
143	OFFSET(THREAD_FPR1, task_struct, thread.fpu.fpr[1]);
144	OFFSET(THREAD_FPR2, task_struct, thread.fpu.fpr[2]);
145	OFFSET(THREAD_FPR3, task_struct, thread.fpu.fpr[3]);
146	OFFSET(THREAD_FPR4, task_struct, thread.fpu.fpr[4]);
147	OFFSET(THREAD_FPR5, task_struct, thread.fpu.fpr[5]);
148	OFFSET(THREAD_FPR6, task_struct, thread.fpu.fpr[6]);
149	OFFSET(THREAD_FPR7, task_struct, thread.fpu.fpr[7]);
150	OFFSET(THREAD_FPR8, task_struct, thread.fpu.fpr[8]);
151	OFFSET(THREAD_FPR9, task_struct, thread.fpu.fpr[9]);
152	OFFSET(THREAD_FPR10, task_struct, thread.fpu.fpr[10]);
153	OFFSET(THREAD_FPR11, task_struct, thread.fpu.fpr[11]);
154	OFFSET(THREAD_FPR12, task_struct, thread.fpu.fpr[12]);
155	OFFSET(THREAD_FPR13, task_struct, thread.fpu.fpr[13]);
156	OFFSET(THREAD_FPR14, task_struct, thread.fpu.fpr[14]);
157	OFFSET(THREAD_FPR15, task_struct, thread.fpu.fpr[15]);
158	OFFSET(THREAD_FPR16, task_struct, thread.fpu.fpr[16]);
159	OFFSET(THREAD_FPR17, task_struct, thread.fpu.fpr[17]);
160	OFFSET(THREAD_FPR18, task_struct, thread.fpu.fpr[18]);
161	OFFSET(THREAD_FPR19, task_struct, thread.fpu.fpr[19]);
162	OFFSET(THREAD_FPR20, task_struct, thread.fpu.fpr[20]);
163	OFFSET(THREAD_FPR21, task_struct, thread.fpu.fpr[21]);
164	OFFSET(THREAD_FPR22, task_struct, thread.fpu.fpr[22]);
165	OFFSET(THREAD_FPR23, task_struct, thread.fpu.fpr[23]);
166	OFFSET(THREAD_FPR24, task_struct, thread.fpu.fpr[24]);
167	OFFSET(THREAD_FPR25, task_struct, thread.fpu.fpr[25]);
168	OFFSET(THREAD_FPR26, task_struct, thread.fpu.fpr[26]);
169	OFFSET(THREAD_FPR27, task_struct, thread.fpu.fpr[27]);
170	OFFSET(THREAD_FPR28, task_struct, thread.fpu.fpr[28]);
171	OFFSET(THREAD_FPR29, task_struct, thread.fpu.fpr[29]);
172	OFFSET(THREAD_FPR30, task_struct, thread.fpu.fpr[30]);
173	OFFSET(THREAD_FPR31, task_struct, thread.fpu.fpr[31]);
174
175	OFFSET(THREAD_FCR31, task_struct, thread.fpu.fcr31);
176	OFFSET(THREAD_MSA_CSR, task_struct, thread.fpu.msacsr);
177	BLANK();
178}
179#endif
180
181void output_mm_defines(void)
182{
183	COMMENT("Size of struct page");
184	DEFINE(STRUCT_PAGE_SIZE, sizeof(struct page));
185	BLANK();
186	COMMENT("Linux mm_struct offsets.");
187	OFFSET(MM_USERS, mm_struct, mm_users);
188	OFFSET(MM_PGD, mm_struct, pgd);
189	OFFSET(MM_CONTEXT, mm_struct, context);
190	BLANK();
191	DEFINE(_PGD_T_SIZE, sizeof(pgd_t));
192	DEFINE(_PMD_T_SIZE, sizeof(pmd_t));
193	DEFINE(_PTE_T_SIZE, sizeof(pte_t));
194	BLANK();
195	DEFINE(_PGD_T_LOG2, PGD_T_LOG2);
196#ifndef __PAGETABLE_PMD_FOLDED
197	DEFINE(_PMD_T_LOG2, PMD_T_LOG2);
198#endif
199	DEFINE(_PTE_T_LOG2, PTE_T_LOG2);
200	BLANK();
201	DEFINE(_PGD_ORDER, PGD_ORDER);
202#ifndef __PAGETABLE_PMD_FOLDED
203	DEFINE(_PMD_ORDER, PMD_ORDER);
204#endif
205	DEFINE(_PTE_ORDER, PTE_ORDER);
206	BLANK();
207	DEFINE(_PMD_SHIFT, PMD_SHIFT);
208	DEFINE(_PGDIR_SHIFT, PGDIR_SHIFT);
209	BLANK();
210	DEFINE(_PTRS_PER_PGD, PTRS_PER_PGD);
211	DEFINE(_PTRS_PER_PMD, PTRS_PER_PMD);
212	DEFINE(_PTRS_PER_PTE, PTRS_PER_PTE);
213	BLANK();
214	DEFINE(_PAGE_SHIFT, PAGE_SHIFT);
215	DEFINE(_PAGE_SIZE, PAGE_SIZE);
216	BLANK();
217}
218
219#ifdef CONFIG_32BIT
220void output_sc_defines(void)
221{
222	COMMENT("Linux sigcontext offsets.");
223	OFFSET(SC_REGS, sigcontext, sc_regs);
224	OFFSET(SC_FPREGS, sigcontext, sc_fpregs);
225	OFFSET(SC_ACX, sigcontext, sc_acx);
226	OFFSET(SC_MDHI, sigcontext, sc_mdhi);
227	OFFSET(SC_MDLO, sigcontext, sc_mdlo);
228	OFFSET(SC_PC, sigcontext, sc_pc);
229	OFFSET(SC_FPC_CSR, sigcontext, sc_fpc_csr);
230	OFFSET(SC_FPC_EIR, sigcontext, sc_fpc_eir);
231	OFFSET(SC_HI1, sigcontext, sc_hi1);
232	OFFSET(SC_LO1, sigcontext, sc_lo1);
233	OFFSET(SC_HI2, sigcontext, sc_hi2);
234	OFFSET(SC_LO2, sigcontext, sc_lo2);
235	OFFSET(SC_HI3, sigcontext, sc_hi3);
236	OFFSET(SC_LO3, sigcontext, sc_lo3);
237	BLANK();
238}
239#endif
240
241#ifdef CONFIG_64BIT
242void output_sc_defines(void)
243{
244	COMMENT("Linux sigcontext offsets.");
245	OFFSET(SC_REGS, sigcontext, sc_regs);
246	OFFSET(SC_FPREGS, sigcontext, sc_fpregs);
247	OFFSET(SC_MDHI, sigcontext, sc_mdhi);
248	OFFSET(SC_MDLO, sigcontext, sc_mdlo);
249	OFFSET(SC_PC, sigcontext, sc_pc);
250	OFFSET(SC_FPC_CSR, sigcontext, sc_fpc_csr);
251	BLANK();
252}
253#endif
254
255void output_signal_defined(void)
256{
257	COMMENT("Linux signal numbers.");
258	DEFINE(_SIGHUP, SIGHUP);
259	DEFINE(_SIGINT, SIGINT);
260	DEFINE(_SIGQUIT, SIGQUIT);
261	DEFINE(_SIGILL, SIGILL);
262	DEFINE(_SIGTRAP, SIGTRAP);
263	DEFINE(_SIGIOT, SIGIOT);
264	DEFINE(_SIGABRT, SIGABRT);
265	DEFINE(_SIGEMT, SIGEMT);
266	DEFINE(_SIGFPE, SIGFPE);
267	DEFINE(_SIGKILL, SIGKILL);
268	DEFINE(_SIGBUS, SIGBUS);
269	DEFINE(_SIGSEGV, SIGSEGV);
270	DEFINE(_SIGSYS, SIGSYS);
271	DEFINE(_SIGPIPE, SIGPIPE);
272	DEFINE(_SIGALRM, SIGALRM);
273	DEFINE(_SIGTERM, SIGTERM);
274	DEFINE(_SIGUSR1, SIGUSR1);
275	DEFINE(_SIGUSR2, SIGUSR2);
276	DEFINE(_SIGCHLD, SIGCHLD);
277	DEFINE(_SIGPWR, SIGPWR);
278	DEFINE(_SIGWINCH, SIGWINCH);
279	DEFINE(_SIGURG, SIGURG);
280	DEFINE(_SIGIO, SIGIO);
281	DEFINE(_SIGSTOP, SIGSTOP);
282	DEFINE(_SIGTSTP, SIGTSTP);
283	DEFINE(_SIGCONT, SIGCONT);
284	DEFINE(_SIGTTIN, SIGTTIN);
285	DEFINE(_SIGTTOU, SIGTTOU);
286	DEFINE(_SIGVTALRM, SIGVTALRM);
287	DEFINE(_SIGPROF, SIGPROF);
288	DEFINE(_SIGXCPU, SIGXCPU);
289	DEFINE(_SIGXFSZ, SIGXFSZ);
290	BLANK();
291}
292
293#ifdef CONFIG_CPU_CAVIUM_OCTEON
294void output_octeon_cop2_state_defines(void)
295{
296	COMMENT("Octeon specific octeon_cop2_state offsets.");
297	OFFSET(OCTEON_CP2_CRC_IV,	octeon_cop2_state, cop2_crc_iv);
298	OFFSET(OCTEON_CP2_CRC_LENGTH,	octeon_cop2_state, cop2_crc_length);
299	OFFSET(OCTEON_CP2_CRC_POLY,	octeon_cop2_state, cop2_crc_poly);
300	OFFSET(OCTEON_CP2_LLM_DAT,	octeon_cop2_state, cop2_llm_dat);
301	OFFSET(OCTEON_CP2_3DES_IV,	octeon_cop2_state, cop2_3des_iv);
302	OFFSET(OCTEON_CP2_3DES_KEY,	octeon_cop2_state, cop2_3des_key);
303	OFFSET(OCTEON_CP2_3DES_RESULT,	octeon_cop2_state, cop2_3des_result);
304	OFFSET(OCTEON_CP2_AES_INP0,	octeon_cop2_state, cop2_aes_inp0);
305	OFFSET(OCTEON_CP2_AES_IV,	octeon_cop2_state, cop2_aes_iv);
306	OFFSET(OCTEON_CP2_AES_KEY,	octeon_cop2_state, cop2_aes_key);
307	OFFSET(OCTEON_CP2_AES_KEYLEN,	octeon_cop2_state, cop2_aes_keylen);
308	OFFSET(OCTEON_CP2_AES_RESULT,	octeon_cop2_state, cop2_aes_result);
309	OFFSET(OCTEON_CP2_GFM_MULT,	octeon_cop2_state, cop2_gfm_mult);
310	OFFSET(OCTEON_CP2_GFM_POLY,	octeon_cop2_state, cop2_gfm_poly);
311	OFFSET(OCTEON_CP2_GFM_RESULT,	octeon_cop2_state, cop2_gfm_result);
312	OFFSET(OCTEON_CP2_HSH_DATW,	octeon_cop2_state, cop2_hsh_datw);
313	OFFSET(OCTEON_CP2_HSH_IVW,	octeon_cop2_state, cop2_hsh_ivw);
314	OFFSET(OCTEON_CP2_SHA3,		octeon_cop2_state, cop2_sha3);
315	OFFSET(THREAD_CP2,	task_struct, thread.cp2);
316	OFFSET(THREAD_CVMSEG,	task_struct, thread.cvmseg.cvmseg);
317	BLANK();
318}
319#endif
320
321#ifdef CONFIG_HIBERNATION
322void output_pbe_defines(void)
323{
324	COMMENT(" Linux struct pbe offsets. ");
325	OFFSET(PBE_ADDRESS, pbe, address);
326	OFFSET(PBE_ORIG_ADDRESS, pbe, orig_address);
327	OFFSET(PBE_NEXT, pbe, next);
328	DEFINE(PBE_SIZE, sizeof(struct pbe));
329	BLANK();
330}
331#endif
332
333#ifdef CONFIG_CPU_PM
334void output_pm_defines(void)
335{
336	COMMENT(" PM offsets. ");
337#ifdef CONFIG_EVA
338	OFFSET(SSS_SEGCTL0,	mips_static_suspend_state, segctl[0]);
339	OFFSET(SSS_SEGCTL1,	mips_static_suspend_state, segctl[1]);
340	OFFSET(SSS_SEGCTL2,	mips_static_suspend_state, segctl[2]);
341#endif
342	OFFSET(SSS_SP,		mips_static_suspend_state, sp);
343	BLANK();
344}
345#endif
346
347#ifdef CONFIG_MIPS_FP_SUPPORT
348void output_kvm_defines(void)
349{
350	COMMENT(" KVM/MIPS Specific offsets. ");
351
352	OFFSET(VCPU_FPR0, kvm_vcpu_arch, fpu.fpr[0]);
353	OFFSET(VCPU_FPR1, kvm_vcpu_arch, fpu.fpr[1]);
354	OFFSET(VCPU_FPR2, kvm_vcpu_arch, fpu.fpr[2]);
355	OFFSET(VCPU_FPR3, kvm_vcpu_arch, fpu.fpr[3]);
356	OFFSET(VCPU_FPR4, kvm_vcpu_arch, fpu.fpr[4]);
357	OFFSET(VCPU_FPR5, kvm_vcpu_arch, fpu.fpr[5]);
358	OFFSET(VCPU_FPR6, kvm_vcpu_arch, fpu.fpr[6]);
359	OFFSET(VCPU_FPR7, kvm_vcpu_arch, fpu.fpr[7]);
360	OFFSET(VCPU_FPR8, kvm_vcpu_arch, fpu.fpr[8]);
361	OFFSET(VCPU_FPR9, kvm_vcpu_arch, fpu.fpr[9]);
362	OFFSET(VCPU_FPR10, kvm_vcpu_arch, fpu.fpr[10]);
363	OFFSET(VCPU_FPR11, kvm_vcpu_arch, fpu.fpr[11]);
364	OFFSET(VCPU_FPR12, kvm_vcpu_arch, fpu.fpr[12]);
365	OFFSET(VCPU_FPR13, kvm_vcpu_arch, fpu.fpr[13]);
366	OFFSET(VCPU_FPR14, kvm_vcpu_arch, fpu.fpr[14]);
367	OFFSET(VCPU_FPR15, kvm_vcpu_arch, fpu.fpr[15]);
368	OFFSET(VCPU_FPR16, kvm_vcpu_arch, fpu.fpr[16]);
369	OFFSET(VCPU_FPR17, kvm_vcpu_arch, fpu.fpr[17]);
370	OFFSET(VCPU_FPR18, kvm_vcpu_arch, fpu.fpr[18]);
371	OFFSET(VCPU_FPR19, kvm_vcpu_arch, fpu.fpr[19]);
372	OFFSET(VCPU_FPR20, kvm_vcpu_arch, fpu.fpr[20]);
373	OFFSET(VCPU_FPR21, kvm_vcpu_arch, fpu.fpr[21]);
374	OFFSET(VCPU_FPR22, kvm_vcpu_arch, fpu.fpr[22]);
375	OFFSET(VCPU_FPR23, kvm_vcpu_arch, fpu.fpr[23]);
376	OFFSET(VCPU_FPR24, kvm_vcpu_arch, fpu.fpr[24]);
377	OFFSET(VCPU_FPR25, kvm_vcpu_arch, fpu.fpr[25]);
378	OFFSET(VCPU_FPR26, kvm_vcpu_arch, fpu.fpr[26]);
379	OFFSET(VCPU_FPR27, kvm_vcpu_arch, fpu.fpr[27]);
380	OFFSET(VCPU_FPR28, kvm_vcpu_arch, fpu.fpr[28]);
381	OFFSET(VCPU_FPR29, kvm_vcpu_arch, fpu.fpr[29]);
382	OFFSET(VCPU_FPR30, kvm_vcpu_arch, fpu.fpr[30]);
383	OFFSET(VCPU_FPR31, kvm_vcpu_arch, fpu.fpr[31]);
384
385	OFFSET(VCPU_FCR31, kvm_vcpu_arch, fpu.fcr31);
386	OFFSET(VCPU_MSA_CSR, kvm_vcpu_arch, fpu.msacsr);
387	BLANK();
388}
389#endif
390
391#ifdef CONFIG_MIPS_CPS
392void output_cps_defines(void)
393{
394	COMMENT(" MIPS CPS offsets. ");
395
396	OFFSET(COREBOOTCFG_VPEMASK, core_boot_config, vpe_mask);
397	OFFSET(COREBOOTCFG_VPECONFIG, core_boot_config, vpe_config);
398	DEFINE(COREBOOTCFG_SIZE, sizeof(struct core_boot_config));
399
400	OFFSET(VPEBOOTCFG_PC, vpe_boot_config, pc);
401	OFFSET(VPEBOOTCFG_SP, vpe_boot_config, sp);
402	OFFSET(VPEBOOTCFG_GP, vpe_boot_config, gp);
403	DEFINE(VPEBOOTCFG_SIZE, sizeof(struct vpe_boot_config));
404}
405#endif