/arch/mips/mm/sc-ip22.c

http://github.com/mirrors/linux · C · 191 lines · 157 code · 21 blank · 13 comment · 5 complexity · b5c65871054656207962a620e258b498 MD5 · raw file

  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * sc-ip22.c: Indy cache management functions.
  4. *
  5. * Copyright (C) 1997, 2001 Ralf Baechle (ralf@gnu.org),
  6. * derived from r4xx0.c by David S. Miller (davem@davemloft.net).
  7. */
  8. #include <linux/init.h>
  9. #include <linux/kernel.h>
  10. #include <linux/sched.h>
  11. #include <linux/mm.h>
  12. #include <asm/bcache.h>
  13. #include <asm/page.h>
  14. #include <asm/pgtable.h>
  15. #include <asm/bootinfo.h>
  16. #include <asm/sgi/ip22.h>
  17. #include <asm/sgi/mc.h>
  18. /* Secondary cache size in bytes, if present. */
  19. static unsigned long scache_size;
  20. #undef DEBUG_CACHE
  21. #define SC_SIZE 0x00080000
  22. #define SC_LINE 32
  23. #define CI_MASK (SC_SIZE - SC_LINE)
  24. #define SC_INDEX(n) ((n) & CI_MASK)
  25. static inline void indy_sc_wipe(unsigned long first, unsigned long last)
  26. {
  27. unsigned long tmp;
  28. __asm__ __volatile__(
  29. " .set push # indy_sc_wipe \n"
  30. " .set noreorder \n"
  31. " .set mips3 \n"
  32. " .set noat \n"
  33. " mfc0 %2, $12 \n"
  34. " li $1, 0x80 # Go 64 bit \n"
  35. " mtc0 $1, $12 \n"
  36. " \n"
  37. " # \n"
  38. " # Open code a dli $1, 0x9000000080000000 \n"
  39. " # \n"
  40. " # Required because binutils 2.25 will happily accept \n"
  41. " # 64 bit instructions in .set mips3 mode but puke on \n"
  42. " # 64 bit constants when generating 32 bit ELF \n"
  43. " # \n"
  44. " lui $1,0x9000 \n"
  45. " dsll $1,$1,0x10 \n"
  46. " ori $1,$1,0x8000 \n"
  47. " dsll $1,$1,0x10 \n"
  48. " \n"
  49. " or %0, $1 # first line to flush \n"
  50. " or %1, $1 # last line to flush \n"
  51. " .set at \n"
  52. " \n"
  53. "1: sw $0, 0(%0) \n"
  54. " bne %0, %1, 1b \n"
  55. " daddu %0, 32 \n"
  56. " \n"
  57. " mtc0 %2, $12 # Back to 32 bit \n"
  58. " nop # pipeline hazard \n"
  59. " nop \n"
  60. " nop \n"
  61. " nop \n"
  62. " .set pop \n"
  63. : "=r" (first), "=r" (last), "=&r" (tmp)
  64. : "0" (first), "1" (last));
  65. }
  66. static void indy_sc_wback_invalidate(unsigned long addr, unsigned long size)
  67. {
  68. unsigned long first_line, last_line;
  69. unsigned long flags;
  70. #ifdef DEBUG_CACHE
  71. printk("indy_sc_wback_invalidate[%08lx,%08lx]", addr, size);
  72. #endif
  73. /* Catch bad driver code */
  74. BUG_ON(size == 0);
  75. /* Which lines to flush? */
  76. first_line = SC_INDEX(addr);
  77. last_line = SC_INDEX(addr + size - 1);
  78. local_irq_save(flags);
  79. if (first_line <= last_line) {
  80. indy_sc_wipe(first_line, last_line);
  81. goto out;
  82. }
  83. indy_sc_wipe(first_line, SC_SIZE - SC_LINE);
  84. indy_sc_wipe(0, last_line);
  85. out:
  86. local_irq_restore(flags);
  87. }
  88. static void indy_sc_enable(void)
  89. {
  90. unsigned long addr, tmp1, tmp2;
  91. /* This is really cool... */
  92. #ifdef DEBUG_CACHE
  93. printk("Enabling R4600 SCACHE\n");
  94. #endif
  95. __asm__ __volatile__(
  96. ".set\tpush\n\t"
  97. ".set\tnoreorder\n\t"
  98. ".set\tmips3\n\t"
  99. "mfc0\t%2, $12\n\t"
  100. "nop; nop; nop; nop;\n\t"
  101. "li\t%1, 0x80\n\t"
  102. "mtc0\t%1, $12\n\t"
  103. "nop; nop; nop; nop;\n\t"
  104. "li\t%0, 0x1\n\t"
  105. "dsll\t%0, 31\n\t"
  106. "lui\t%1, 0x9000\n\t"
  107. "dsll32\t%1, 0\n\t"
  108. "or\t%0, %1, %0\n\t"
  109. "sb\t$0, 0(%0)\n\t"
  110. "mtc0\t$0, $12\n\t"
  111. "nop; nop; nop; nop;\n\t"
  112. "mtc0\t%2, $12\n\t"
  113. "nop; nop; nop; nop;\n\t"
  114. ".set\tpop"
  115. : "=r" (tmp1), "=r" (tmp2), "=r" (addr));
  116. }
  117. static void indy_sc_disable(void)
  118. {
  119. unsigned long tmp1, tmp2, tmp3;
  120. #ifdef DEBUG_CACHE
  121. printk("Disabling R4600 SCACHE\n");
  122. #endif
  123. __asm__ __volatile__(
  124. ".set\tpush\n\t"
  125. ".set\tnoreorder\n\t"
  126. ".set\tmips3\n\t"
  127. "li\t%0, 0x1\n\t"
  128. "dsll\t%0, 31\n\t"
  129. "lui\t%1, 0x9000\n\t"
  130. "dsll32\t%1, 0\n\t"
  131. "or\t%0, %1, %0\n\t"
  132. "mfc0\t%2, $12\n\t"
  133. "nop; nop; nop; nop\n\t"
  134. "li\t%1, 0x80\n\t"
  135. "mtc0\t%1, $12\n\t"
  136. "nop; nop; nop; nop\n\t"
  137. "sh\t$0, 0(%0)\n\t"
  138. "mtc0\t$0, $12\n\t"
  139. "nop; nop; nop; nop\n\t"
  140. "mtc0\t%2, $12\n\t"
  141. "nop; nop; nop; nop\n\t"
  142. ".set\tpop"
  143. : "=r" (tmp1), "=r" (tmp2), "=r" (tmp3));
  144. }
  145. static inline int __init indy_sc_probe(void)
  146. {
  147. unsigned int size = ip22_eeprom_read(&sgimc->eeprom, 17);
  148. if (size == 0)
  149. return 0;
  150. size <<= PAGE_SHIFT;
  151. printk(KERN_INFO "R4600/R5000 SCACHE size %dK, linesize 32 bytes.\n",
  152. size >> 10);
  153. scache_size = size;
  154. return 1;
  155. }
  156. /* XXX Check with wje if the Indy caches can differentiate between
  157. writeback + invalidate and just invalidate. */
  158. static struct bcache_ops indy_sc_ops = {
  159. .bc_enable = indy_sc_enable,
  160. .bc_disable = indy_sc_disable,
  161. .bc_wback_inv = indy_sc_wback_invalidate,
  162. .bc_inv = indy_sc_wback_invalidate
  163. };
  164. void indy_sc_init(void)
  165. {
  166. if (indy_sc_probe()) {
  167. indy_sc_enable();
  168. bcops = &indy_sc_ops;
  169. }
  170. }