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/arch/mips/ar7/clock.c

http://github.com/mirrors/linux
C | 494 lines | 408 code | 70 blank | 16 comment | 45 complexity | be773116040db32790c3126fce512a8c MD5 | raw file
  1// SPDX-License-Identifier: GPL-2.0-or-later
  2/*
  3 * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
  4 * Copyright (C) 2007 Eugene Konev <ejka@openwrt.org>
  5 * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
  6 */
  7
  8#include <linux/kernel.h>
  9#include <linux/init.h>
 10#include <linux/types.h>
 11#include <linux/export.h>
 12#include <linux/delay.h>
 13#include <linux/gcd.h>
 14#include <linux/io.h>
 15#include <linux/err.h>
 16#include <linux/clk.h>
 17
 18#include <asm/addrspace.h>
 19#include <asm/mach-ar7/ar7.h>
 20
 21#define BOOT_PLL_SOURCE_MASK	0x3
 22#define CPU_PLL_SOURCE_SHIFT	16
 23#define BUS_PLL_SOURCE_SHIFT	14
 24#define USB_PLL_SOURCE_SHIFT	18
 25#define DSP_PLL_SOURCE_SHIFT	22
 26#define BOOT_PLL_SOURCE_AFE	0
 27#define BOOT_PLL_SOURCE_BUS	0
 28#define BOOT_PLL_SOURCE_REF	1
 29#define BOOT_PLL_SOURCE_XTAL	2
 30#define BOOT_PLL_SOURCE_CPU	3
 31#define BOOT_PLL_BYPASS		0x00000020
 32#define BOOT_PLL_ASYNC_MODE	0x02000000
 33#define BOOT_PLL_2TO1_MODE	0x00008000
 34
 35#define TNETD7200_CLOCK_ID_CPU	0
 36#define TNETD7200_CLOCK_ID_DSP	1
 37#define TNETD7200_CLOCK_ID_USB	2
 38
 39#define TNETD7200_DEF_CPU_CLK	211000000
 40#define TNETD7200_DEF_DSP_CLK	125000000
 41#define TNETD7200_DEF_USB_CLK	48000000
 42
 43struct tnetd7300_clock {
 44	u32 ctrl;
 45#define PREDIV_MASK	0x001f0000
 46#define PREDIV_SHIFT	16
 47#define POSTDIV_MASK	0x0000001f
 48	u32 unused1[3];
 49	u32 pll;
 50#define MUL_MASK	0x0000f000
 51#define MUL_SHIFT	12
 52#define PLL_MODE_MASK	0x00000001
 53#define PLL_NDIV	0x00000800
 54#define PLL_DIV		0x00000002
 55#define PLL_STATUS	0x00000001
 56	u32 unused2[3];
 57};
 58
 59struct tnetd7300_clocks {
 60	struct tnetd7300_clock bus;
 61	struct tnetd7300_clock cpu;
 62	struct tnetd7300_clock usb;
 63	struct tnetd7300_clock dsp;
 64};
 65
 66struct tnetd7200_clock {
 67	u32 ctrl;
 68	u32 unused1[3];
 69#define DIVISOR_ENABLE_MASK 0x00008000
 70	u32 mul;
 71	u32 prediv;
 72	u32 postdiv;
 73	u32 postdiv2;
 74	u32 unused2[6];
 75	u32 cmd;
 76	u32 status;
 77	u32 cmden;
 78	u32 padding[15];
 79};
 80
 81struct tnetd7200_clocks {
 82	struct tnetd7200_clock cpu;
 83	struct tnetd7200_clock dsp;
 84	struct tnetd7200_clock usb;
 85};
 86
 87static struct clk bus_clk = {
 88	.rate	= 125000000,
 89};
 90
 91static struct clk cpu_clk = {
 92	.rate	= 150000000,
 93};
 94
 95static struct clk dsp_clk;
 96static struct clk vbus_clk;
 97
 98static void approximate(int base, int target, int *prediv,
 99			int *postdiv, int *mul)
100{
101	int i, j, k, freq, res = target;
102	for (i = 1; i <= 16; i++)
103		for (j = 1; j <= 32; j++)
104			for (k = 1; k <= 32; k++) {
105				freq = abs(base / j * i / k - target);
106				if (freq < res) {
107					res = freq;
108					*mul = i;
109					*prediv = j;
110					*postdiv = k;
111				}
112			}
113}
114
115static void calculate(int base, int target, int *prediv, int *postdiv,
116	int *mul)
117{
118	int tmp_gcd, tmp_base, tmp_freq;
119
120	for (*prediv = 1; *prediv <= 32; (*prediv)++) {
121		tmp_base = base / *prediv;
122		tmp_gcd = gcd(target, tmp_base);
123		*mul = target / tmp_gcd;
124		*postdiv = tmp_base / tmp_gcd;
125		if ((*mul < 1) || (*mul >= 16))
126			continue;
127		if ((*postdiv > 0) & (*postdiv <= 32))
128			break;
129	}
130
131	if (base / *prediv * *mul / *postdiv != target) {
132		approximate(base, target, prediv, postdiv, mul);
133		tmp_freq = base / *prediv * *mul / *postdiv;
134		printk(KERN_WARNING
135		       "Adjusted requested frequency %d to %d\n",
136		       target, tmp_freq);
137	}
138
139	printk(KERN_DEBUG "Clocks: prediv: %d, postdiv: %d, mul: %d\n",
140	       *prediv, *postdiv, *mul);
141}
142
143static int tnetd7300_dsp_clock(void)
144{
145	u32 didr1, didr2;
146	u8 rev = ar7_chip_rev();
147	didr1 = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x18));
148	didr2 = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x1c));
149	if (didr2 & (1 << 23))
150		return 0;
151	if ((rev >= 0x23) && (rev != 0x57))
152		return 250000000;
153	if ((((didr2 & 0x1fff) << 10) | ((didr1 & 0xffc00000) >> 22))
154	    > 4208000)
155		return 250000000;
156	return 0;
157}
158
159static int tnetd7300_get_clock(u32 shift, struct tnetd7300_clock *clock,
160	u32 *bootcr, u32 bus_clock)
161{
162	int product;
163	int base_clock = AR7_REF_CLOCK;
164	u32 ctrl = readl(&clock->ctrl);
165	u32 pll = readl(&clock->pll);
166	int prediv = ((ctrl & PREDIV_MASK) >> PREDIV_SHIFT) + 1;
167	int postdiv = (ctrl & POSTDIV_MASK) + 1;
168	int divisor = prediv * postdiv;
169	int mul = ((pll & MUL_MASK) >> MUL_SHIFT) + 1;
170
171	switch ((*bootcr & (BOOT_PLL_SOURCE_MASK << shift)) >> shift) {
172	case BOOT_PLL_SOURCE_BUS:
173		base_clock = bus_clock;
174		break;
175	case BOOT_PLL_SOURCE_REF:
176		base_clock = AR7_REF_CLOCK;
177		break;
178	case BOOT_PLL_SOURCE_XTAL:
179		base_clock = AR7_XTAL_CLOCK;
180		break;
181	case BOOT_PLL_SOURCE_CPU:
182		base_clock = cpu_clk.rate;
183		break;
184	}
185
186	if (*bootcr & BOOT_PLL_BYPASS)
187		return base_clock / divisor;
188
189	if ((pll & PLL_MODE_MASK) == 0)
190		return (base_clock >> (mul / 16 + 1)) / divisor;
191
192	if ((pll & (PLL_NDIV | PLL_DIV)) == (PLL_NDIV | PLL_DIV)) {
193		product = (mul & 1) ?
194			(base_clock * mul) >> 1 :
195			(base_clock * (mul - 1)) >> 2;
196		return product / divisor;
197	}
198
199	if (mul == 16)
200		return base_clock / divisor;
201
202	return base_clock * mul / divisor;
203}
204
205static void tnetd7300_set_clock(u32 shift, struct tnetd7300_clock *clock,
206	u32 *bootcr, u32 frequency)
207{
208	int prediv, postdiv, mul;
209	int base_clock = bus_clk.rate;
210
211	switch ((*bootcr & (BOOT_PLL_SOURCE_MASK << shift)) >> shift) {
212	case BOOT_PLL_SOURCE_BUS:
213		base_clock = bus_clk.rate;
214		break;
215	case BOOT_PLL_SOURCE_REF:
216		base_clock = AR7_REF_CLOCK;
217		break;
218	case BOOT_PLL_SOURCE_XTAL:
219		base_clock = AR7_XTAL_CLOCK;
220		break;
221	case BOOT_PLL_SOURCE_CPU:
222		base_clock = cpu_clk.rate;
223		break;
224	}
225
226	calculate(base_clock, frequency, &prediv, &postdiv, &mul);
227
228	writel(((prediv - 1) << PREDIV_SHIFT) | (postdiv - 1), &clock->ctrl);
229	mdelay(1);
230	writel(4, &clock->pll);
231	while (readl(&clock->pll) & PLL_STATUS)
232		;
233	writel(((mul - 1) << MUL_SHIFT) | (0xff << 3) | 0x0e, &clock->pll);
234	mdelay(75);
235}
236
237static void __init tnetd7300_init_clocks(void)
238{
239	u32 *bootcr = (u32 *)ioremap(AR7_REGS_DCL, 4);
240	struct tnetd7300_clocks *clocks =
241					ioremap(UR8_REGS_CLOCKS,
242					sizeof(struct tnetd7300_clocks));
243
244	bus_clk.rate = tnetd7300_get_clock(BUS_PLL_SOURCE_SHIFT,
245		&clocks->bus, bootcr, AR7_AFE_CLOCK);
246
247	if (*bootcr & BOOT_PLL_ASYNC_MODE)
248		cpu_clk.rate = tnetd7300_get_clock(CPU_PLL_SOURCE_SHIFT,
249			&clocks->cpu, bootcr, AR7_AFE_CLOCK);
250	else
251		cpu_clk.rate = bus_clk.rate;
252
253	if (dsp_clk.rate == 250000000)
254		tnetd7300_set_clock(DSP_PLL_SOURCE_SHIFT, &clocks->dsp,
255			bootcr, dsp_clk.rate);
256
257	iounmap(clocks);
258	iounmap(bootcr);
259}
260
261static void tnetd7200_set_clock(int base, struct tnetd7200_clock *clock,
262	int prediv, int postdiv, int postdiv2, int mul, u32 frequency)
263{
264	printk(KERN_INFO
265		"Clocks: base = %d, frequency = %u, prediv = %d, "
266		"postdiv = %d, postdiv2 = %d, mul = %d\n",
267		base, frequency, prediv, postdiv, postdiv2, mul);
268
269	writel(0, &clock->ctrl);
270	writel(DIVISOR_ENABLE_MASK | ((prediv - 1) & 0x1F), &clock->prediv);
271	writel((mul - 1) & 0xF, &clock->mul);
272
273	while (readl(&clock->status) & 0x1)
274		; /* nop */
275
276	writel(DIVISOR_ENABLE_MASK | ((postdiv - 1) & 0x1F), &clock->postdiv);
277
278	writel(readl(&clock->cmden) | 1, &clock->cmden);
279	writel(readl(&clock->cmd) | 1, &clock->cmd);
280
281	while (readl(&clock->status) & 0x1)
282		; /* nop */
283
284	writel(DIVISOR_ENABLE_MASK | ((postdiv2 - 1) & 0x1F), &clock->postdiv2);
285
286	writel(readl(&clock->cmden) | 1, &clock->cmden);
287	writel(readl(&clock->cmd) | 1, &clock->cmd);
288
289	while (readl(&clock->status) & 0x1)
290		; /* nop */
291
292	writel(readl(&clock->ctrl) | 1, &clock->ctrl);
293}
294
295static int tnetd7200_get_clock_base(int clock_id, u32 *bootcr)
296{
297	if (*bootcr & BOOT_PLL_ASYNC_MODE)
298		/* Async */
299		switch (clock_id) {
300		case TNETD7200_CLOCK_ID_DSP:
301			return AR7_REF_CLOCK;
302		default:
303			return AR7_AFE_CLOCK;
304		}
305	else
306		/* Sync */
307		if (*bootcr & BOOT_PLL_2TO1_MODE)
308			/* 2:1 */
309			switch (clock_id) {
310			case TNETD7200_CLOCK_ID_DSP:
311				return AR7_REF_CLOCK;
312			default:
313				return AR7_AFE_CLOCK;
314			}
315		else
316			/* 1:1 */
317			return AR7_REF_CLOCK;
318}
319
320
321static void __init tnetd7200_init_clocks(void)
322{
323	u32 *bootcr = (u32 *)ioremap(AR7_REGS_DCL, 4);
324	struct tnetd7200_clocks *clocks =
325					ioremap(AR7_REGS_CLOCKS,
326					sizeof(struct tnetd7200_clocks));
327	int cpu_base, cpu_mul, cpu_prediv, cpu_postdiv;
328	int dsp_base, dsp_mul, dsp_prediv, dsp_postdiv;
329	int usb_base, usb_mul, usb_prediv, usb_postdiv;
330
331	cpu_base = tnetd7200_get_clock_base(TNETD7200_CLOCK_ID_CPU, bootcr);
332	dsp_base = tnetd7200_get_clock_base(TNETD7200_CLOCK_ID_DSP, bootcr);
333
334	if (*bootcr & BOOT_PLL_ASYNC_MODE) {
335		printk(KERN_INFO "Clocks: Async mode\n");
336
337		printk(KERN_INFO "Clocks: Setting DSP clock\n");
338		calculate(dsp_base, TNETD7200_DEF_DSP_CLK,
339			&dsp_prediv, &dsp_postdiv, &dsp_mul);
340		bus_clk.rate =
341			((dsp_base / dsp_prediv) * dsp_mul) / dsp_postdiv;
342		tnetd7200_set_clock(dsp_base, &clocks->dsp,
343			dsp_prediv, dsp_postdiv * 2, dsp_postdiv, dsp_mul * 2,
344			bus_clk.rate);
345
346		printk(KERN_INFO "Clocks: Setting CPU clock\n");
347		calculate(cpu_base, TNETD7200_DEF_CPU_CLK, &cpu_prediv,
348			&cpu_postdiv, &cpu_mul);
349		cpu_clk.rate =
350			((cpu_base / cpu_prediv) * cpu_mul) / cpu_postdiv;
351		tnetd7200_set_clock(cpu_base, &clocks->cpu,
352			cpu_prediv, cpu_postdiv, -1, cpu_mul,
353			cpu_clk.rate);
354
355	} else
356		if (*bootcr & BOOT_PLL_2TO1_MODE) {
357			printk(KERN_INFO "Clocks: Sync 2:1 mode\n");
358
359			printk(KERN_INFO "Clocks: Setting CPU clock\n");
360			calculate(cpu_base, TNETD7200_DEF_CPU_CLK, &cpu_prediv,
361				&cpu_postdiv, &cpu_mul);
362			cpu_clk.rate = ((cpu_base / cpu_prediv) * cpu_mul)
363								/ cpu_postdiv;
364			tnetd7200_set_clock(cpu_base, &clocks->cpu,
365				cpu_prediv, cpu_postdiv, -1, cpu_mul,
366				cpu_clk.rate);
367
368			printk(KERN_INFO "Clocks: Setting DSP clock\n");
369			calculate(dsp_base, TNETD7200_DEF_DSP_CLK, &dsp_prediv,
370				&dsp_postdiv, &dsp_mul);
371			bus_clk.rate = cpu_clk.rate / 2;
372			tnetd7200_set_clock(dsp_base, &clocks->dsp,
373				dsp_prediv, dsp_postdiv * 2, dsp_postdiv,
374				dsp_mul * 2, bus_clk.rate);
375		} else {
376			printk(KERN_INFO "Clocks: Sync 1:1 mode\n");
377
378			printk(KERN_INFO "Clocks: Setting DSP clock\n");
379			calculate(dsp_base, TNETD7200_DEF_DSP_CLK, &dsp_prediv,
380				&dsp_postdiv, &dsp_mul);
381			bus_clk.rate = ((dsp_base / dsp_prediv) * dsp_mul)
382								/ dsp_postdiv;
383			tnetd7200_set_clock(dsp_base, &clocks->dsp,
384				dsp_prediv, dsp_postdiv * 2, dsp_postdiv,
385				dsp_mul * 2, bus_clk.rate);
386
387			cpu_clk.rate = bus_clk.rate;
388		}
389
390	printk(KERN_INFO "Clocks: Setting USB clock\n");
391	usb_base = bus_clk.rate;
392	calculate(usb_base, TNETD7200_DEF_USB_CLK, &usb_prediv,
393		&usb_postdiv, &usb_mul);
394	tnetd7200_set_clock(usb_base, &clocks->usb,
395		usb_prediv, usb_postdiv, -1, usb_mul,
396		TNETD7200_DEF_USB_CLK);
397
398	dsp_clk.rate = cpu_clk.rate;
399
400	iounmap(clocks);
401	iounmap(bootcr);
402}
403
404/*
405 * Linux clock API
406 */
407int clk_enable(struct clk *clk)
408{
409	return 0;
410}
411EXPORT_SYMBOL(clk_enable);
412
413void clk_disable(struct clk *clk)
414{
415}
416EXPORT_SYMBOL(clk_disable);
417
418unsigned long clk_get_rate(struct clk *clk)
419{
420	if (!clk)
421		return 0;
422
423	return clk->rate;
424}
425EXPORT_SYMBOL(clk_get_rate);
426
427struct clk *clk_get(struct device *dev, const char *id)
428{
429	if (!strcmp(id, "bus"))
430		return &bus_clk;
431	/* cpmac and vbus share the same rate */
432	if (!strcmp(id, "cpmac"))
433		return &vbus_clk;
434	if (!strcmp(id, "cpu"))
435		return &cpu_clk;
436	if (!strcmp(id, "dsp"))
437		return &dsp_clk;
438	if (!strcmp(id, "vbus"))
439		return &vbus_clk;
440	return ERR_PTR(-ENOENT);
441}
442EXPORT_SYMBOL(clk_get);
443
444void clk_put(struct clk *clk)
445{
446}
447EXPORT_SYMBOL(clk_put);
448
449void __init ar7_init_clocks(void)
450{
451	switch (ar7_chip_id()) {
452	case AR7_CHIP_7100:
453	case AR7_CHIP_7200:
454		tnetd7200_init_clocks();
455		break;
456	case AR7_CHIP_7300:
457		dsp_clk.rate = tnetd7300_dsp_clock();
458		tnetd7300_init_clocks();
459		break;
460	default:
461		break;
462	}
463	/* adjust vbus clock rate */
464	vbus_clk.rate = bus_clk.rate / 2;
465}
466
467/* dummy functions, should not be called */
468long clk_round_rate(struct clk *clk, unsigned long rate)
469{
470	WARN_ON(clk);
471	return 0;
472}
473EXPORT_SYMBOL(clk_round_rate);
474
475int clk_set_rate(struct clk *clk, unsigned long rate)
476{
477	WARN_ON(clk);
478	return 0;
479}
480EXPORT_SYMBOL(clk_set_rate);
481
482int clk_set_parent(struct clk *clk, struct clk *parent)
483{
484	WARN_ON(clk);
485	return 0;
486}
487EXPORT_SYMBOL(clk_set_parent);
488
489struct clk *clk_get_parent(struct clk *clk)
490{
491	WARN_ON(clk);
492	return NULL;
493}
494EXPORT_SYMBOL(clk_get_parent);