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/arch/mips/bcm47xx/irq.c

http://github.com/mirrors/linux
C | 98 lines | 57 code | 10 blank | 31 comment | 9 complexity | 7e3a7a708bf545cf8a2cba914b915ea3 MD5 | raw file
 1/*
 2 *  Copyright (C) 2004 Florian Schirmer <jolt@tuxbox.org>
 3 *
 4 *  This program is free software; you can redistribute  it and/or modify it
 5 *  under  the terms of  the GNU General  Public License as published by the
 6 *  Free Software Foundation;  either version 2 of the  License, or (at your
 7 *  option) any later version.
 8 *
 9 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
10 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
11 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
12 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
13 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
14 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
15 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
16 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
17 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
18 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
19 *
20 *  You should have received a copy of the  GNU General Public License along
21 *  with this program; if not, write  to the Free Software Foundation, Inc.,
22 *  675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25#include "bcm47xx_private.h"
26
27#include <linux/types.h>
28#include <linux/interrupt.h>
29#include <linux/irq.h>
30#include <asm/setup.h>
31#include <asm/irq_cpu.h>
32#include <bcm47xx.h>
33
34asmlinkage void plat_irq_dispatch(void)
35{
36	u32 cause;
37
38	cause = read_c0_cause() & read_c0_status() & CAUSEF_IP;
39
40	clear_c0_status(cause);
41
42	if (cause & CAUSEF_IP7)
43		do_IRQ(7);
44	if (cause & CAUSEF_IP2)
45		do_IRQ(2);
46	if (cause & CAUSEF_IP3)
47		do_IRQ(3);
48	if (cause & CAUSEF_IP4)
49		do_IRQ(4);
50	if (cause & CAUSEF_IP5)
51		do_IRQ(5);
52	if (cause & CAUSEF_IP6)
53		do_IRQ(6);
54}
55
56#define DEFINE_HWx_IRQDISPATCH(x)					\
57	static void bcm47xx_hw ## x ## _irqdispatch(void)		\
58	{								\
59		do_IRQ(x);						\
60	}
61DEFINE_HWx_IRQDISPATCH(2)
62DEFINE_HWx_IRQDISPATCH(3)
63DEFINE_HWx_IRQDISPATCH(4)
64DEFINE_HWx_IRQDISPATCH(5)
65DEFINE_HWx_IRQDISPATCH(6)
66DEFINE_HWx_IRQDISPATCH(7)
67
68void __init arch_init_irq(void)
69{
70	/*
71	 * This is the first arch callback after mm_init (we can use kmalloc),
72	 * so let's finish bus initialization now.
73	 */
74	bcm47xx_bus_setup();
75
76#ifdef CONFIG_BCM47XX_BCMA
77	if (bcm47xx_bus_type == BCM47XX_BUS_TYPE_BCMA) {
78		bcma_write32(bcm47xx_bus.bcma.bus.drv_mips.core,
79			     BCMA_MIPS_MIPS74K_INTMASK(5), 1 << 31);
80		/*
81		 * the kernel reads the timer irq from some register and thinks
82		 * it's #5, but we offset it by 2 and route to #7
83		 */
84		cp0_compare_irq = 7;
85	}
86#endif
87	mips_cpu_irq_init();
88
89	if (cpu_has_vint) {
90		pr_info("Setting up vectored interrupts\n");
91		set_vi_handler(2, bcm47xx_hw2_irqdispatch);
92		set_vi_handler(3, bcm47xx_hw3_irqdispatch);
93		set_vi_handler(4, bcm47xx_hw4_irqdispatch);
94		set_vi_handler(5, bcm47xx_hw5_irqdispatch);
95		set_vi_handler(6, bcm47xx_hw6_irqdispatch);
96		set_vi_handler(7, bcm47xx_hw7_irqdispatch);
97	}
98}