/arch/mips/include/asm/mach-sibyte/war.h

http://github.com/mirrors/linux · C Header · 38 lines · 22 code · 9 blank · 7 comment · 0 complexity · dc2046a5f2c3cc0715bce251c55a78b4 MD5 · raw file 

    

  1. /*
    2. 

  2.  * This file is subject to the terms and conditions of the GNU General Public
    3. 

  3.  * License.  See the file "COPYING" in the main directory of this archive
    4. 

  4.  * for more details.
    5. 

  5.  *
    6. 

  6.  * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
    7. 

  7.  */
    8. 

  8. #ifndef __ASM_MIPS_MACH_SIBYTE_WAR_H
    9. 

  9. #define __ASM_MIPS_MACH_SIBYTE_WAR_H
    10. 

  10. 

  11. #define R4600_V1_INDEX_ICACHEOP_WAR	0
    12. 

  12. #define R4600_V1_HIT_CACHEOP_WAR	0
    13. 

  13. #define R4600_V2_HIT_CACHEOP_WAR	0
    14. 

  14. 

  15. #if defined(CONFIG_SB1_PASS_2_WORKAROUNDS)
    16. 

  16. 

  17. #ifndef __ASSEMBLY__
    18. 

  18. extern int sb1250_m3_workaround_needed(void);
    19. 

  19. #endif
    20. 

  20. 

  21. #define BCM1250_M3_WAR	sb1250_m3_workaround_needed()
    22. 

  22. #define SIBYTE_1956_WAR 1
    23. 

  23. 

  24. #else
    25. 

  25. 

  26. #define BCM1250_M3_WAR	0
    27. 

  27. #define SIBYTE_1956_WAR 0
    28. 

  28. 

  29. #endif
    30. 

  30. 

  31. #define MIPS4K_ICACHE_REFILL_WAR	0
    32. 

  32. #define MIPS_CACHE_SYNC_WAR		0
    33. 

  33. #define TX49XX_ICACHE_INDEX_INV_WAR	0
    34. 

  34. #define ICACHE_REFILLS_WORKAROUND_WAR	0
    35. 

  35. #define R10000_LLSC_WAR			0
    36. 

  36. #define MIPS34K_MISSED_ITLB_WAR		0
    37. 

  37. 

  38. #endif /* __ASM_MIPS_MACH_SIBYTE_WAR_H */
    39.