/arch/mips/include/asm/mach-rc32434/rb.h

http://github.com/mirrors/linux · C Header · 75 lines · 60 code · 8 blank · 7 comment · 0 complexity · ba908faf0699d34814d5ef9574425341 MD5 · raw file 

    

  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
    2. 

  2. /*
    3. 

  3.  *
    4. 

  4.  *  Copyright (C) 2004 IDT Inc.
    5. 

  5.  *  Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
    6. 

  6.  */
    7. 

  7. #ifndef __ASM_RC32434_RB_H
    8. 

  8. #define __ASM_RC32434_RB_H
    9. 

  9. 

  10. #include <linux/genhd.h>
    11. 

  11. 

  12. #define REGBASE		0x18000000
    13. 

  13. #define IDT434_REG_BASE ((volatile void *) KSEG1ADDR(REGBASE))
    14. 

  14. #define UART0BASE	0x58000
    15. 

  15. #define RST		(1 << 15)
    16. 

  16. #define DEV0BASE	0x010000
    17. 

  17. #define DEV0MASK	0x010004
    18. 

  18. #define DEV0C		0x010008
    19. 

  19. #define DEV0T		0x01000C
    20. 

  20. #define DEV1BASE	0x010010
    21. 

  21. #define DEV1MASK	0x010014
    22. 

  22. #define DEV1C		0x010018
    23. 

  23. #define DEV1TC		0x01001C
    24. 

  24. #define DEV2BASE	0x010020
    25. 

  25. #define DEV2MASK	0x010024
    26. 

  26. #define DEV2C		0x010028
    27. 

  27. #define DEV2TC		0x01002C
    28. 

  28. #define DEV3BASE	0x010030
    29. 

  29. #define DEV3MASK	0x010034
    30. 

  30. #define DEV3C		0x010038
    31. 

  31. #define DEV3TC		0x01003C
    32. 

  32. #define BTCS		0x010040
    33. 

  33. #define BTCOMPARE	0x010044
    34. 

  34. #define GPIOBASE	0x050000
    35. 

  35. /* Offsets relative to GPIOBASE */
    36. 

  36. #define GPIOFUNC	0x00
    37. 

  37. #define GPIOCFG		0x04
    38. 

  38. #define GPIOD		0x08
    39. 

  39. #define GPIOILEVEL	0x0C
    40. 

  40. #define GPIOISTAT	0x10
    41. 

  41. #define GPIONMIEN	0x14
    42. 

  42. #define IMASK6		0x38
    43. 

  43. #define LO_WPX		(1 << 0)
    44. 

  44. #define LO_ALE		(1 << 1)
    45. 

  45. #define LO_CLE		(1 << 2)
    46. 

  46. #define LO_CEX		(1 << 3)
    47. 

  47. #define LO_FOFF		(1 << 5)
    48. 

  48. #define LO_SPICS	(1 << 6)
    49. 

  49. #define LO_ULED		(1 << 7)
    50. 

  50. 

  51. #define BIT_TO_MASK(x)	(1 << x)
    52. 

  52. 

  53. struct dev_reg {
    54. 

  54. 	u32	base;
    55. 

  55. 	u32	mask;
    56. 

  56. 	u32	ctl;
    57. 

  57. 	u32	timing;
    58. 

  58. };
    59. 

  59. 

  60. struct korina_device {
    61. 

  61. 	char *name;
    62. 

  62. 	unsigned char mac[6];
    63. 

  63. 	struct net_device *dev;
    64. 

  64. };
    65. 

  65. 

  66. struct mpmc_device {
    67. 

  67. 	unsigned char	state;
    68. 

  68. 	spinlock_t	lock;
    69. 

  69. 	void __iomem	*base;
    70. 

  70. };
    71. 

  71. 

  72. extern void set_latch_u5(unsigned char or_mask, unsigned char nand_mask);
    73. 

  73. extern unsigned char get_latch_u5(void);
    74. 

  74. 

  75. #endif	/* __ASM_RC32434_RB_H */
    76.