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/arch/mips/include/asm/octeon/cvmx-pow-defs.h

http://github.com/mirrors/linux
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   1/***********************license start***************
   2 * Author: Cavium Networks
   3 *
   4 * Contact: support@caviumnetworks.com
   5 * This file is part of the OCTEON SDK
   6 *
   7 * Copyright (c) 2003-2012 Cavium Networks
   8 *
   9 * This file is free software; you can redistribute it and/or modify
  10 * it under the terms of the GNU General Public License, Version 2, as
  11 * published by the Free Software Foundation.
  12 *
  13 * This file is distributed in the hope that it will be useful, but
  14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16 * NONINFRINGEMENT.  See the GNU General Public License for more
  17 * details.
  18 *
  19 * You should have received a copy of the GNU General Public License
  20 * along with this file; if not, write to the Free Software
  21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  22 * or visit http://www.gnu.org/licenses/.
  23 *
  24 * This file may also be available under a different license from Cavium.
  25 * Contact Cavium Networks for more information
  26 ***********************license end**************************************/
  27
  28#ifndef __CVMX_POW_DEFS_H__
  29#define __CVMX_POW_DEFS_H__
  30
  31#define CVMX_POW_BIST_STAT (CVMX_ADD_IO_SEG(0x00016700000003F8ull))
  32#define CVMX_POW_DS_PC (CVMX_ADD_IO_SEG(0x0001670000000398ull))
  33#define CVMX_POW_ECC_ERR (CVMX_ADD_IO_SEG(0x0001670000000218ull))
  34#define CVMX_POW_INT_CTL (CVMX_ADD_IO_SEG(0x0001670000000220ull))
  35#define CVMX_POW_IQ_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001670000000340ull) + ((offset) & 7) * 8)
  36#define CVMX_POW_IQ_COM_CNT (CVMX_ADD_IO_SEG(0x0001670000000388ull))
  37#define CVMX_POW_IQ_INT (CVMX_ADD_IO_SEG(0x0001670000000238ull))
  38#define CVMX_POW_IQ_INT_EN (CVMX_ADD_IO_SEG(0x0001670000000240ull))
  39#define CVMX_POW_IQ_THRX(offset) (CVMX_ADD_IO_SEG(0x00016700000003A0ull) + ((offset) & 7) * 8)
  40#define CVMX_POW_NOS_CNT (CVMX_ADD_IO_SEG(0x0001670000000228ull))
  41#define CVMX_POW_NW_TIM (CVMX_ADD_IO_SEG(0x0001670000000210ull))
  42#define CVMX_POW_PF_RST_MSK (CVMX_ADD_IO_SEG(0x0001670000000230ull))
  43#define CVMX_POW_PP_GRP_MSKX(offset) (CVMX_ADD_IO_SEG(0x0001670000000000ull) + ((offset) & 15) * 8)
  44#define CVMX_POW_QOS_RNDX(offset) (CVMX_ADD_IO_SEG(0x00016700000001C0ull) + ((offset) & 7) * 8)
  45#define CVMX_POW_QOS_THRX(offset) (CVMX_ADD_IO_SEG(0x0001670000000180ull) + ((offset) & 7) * 8)
  46#define CVMX_POW_TS_PC (CVMX_ADD_IO_SEG(0x0001670000000390ull))
  47#define CVMX_POW_WA_COM_PC (CVMX_ADD_IO_SEG(0x0001670000000380ull))
  48#define CVMX_POW_WA_PCX(offset) (CVMX_ADD_IO_SEG(0x0001670000000300ull) + ((offset) & 7) * 8)
  49#define CVMX_POW_WQ_INT (CVMX_ADD_IO_SEG(0x0001670000000200ull))
  50#define CVMX_POW_WQ_INT_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001670000000100ull) + ((offset) & 15) * 8)
  51#define CVMX_POW_WQ_INT_PC (CVMX_ADD_IO_SEG(0x0001670000000208ull))
  52#define CVMX_POW_WQ_INT_THRX(offset) (CVMX_ADD_IO_SEG(0x0001670000000080ull) + ((offset) & 15) * 8)
  53#define CVMX_POW_WS_PCX(offset) (CVMX_ADD_IO_SEG(0x0001670000000280ull) + ((offset) & 15) * 8)
  54
  55#define CVMX_SSO_WQ_INT (CVMX_ADD_IO_SEG(0x0001670000001000ull))
  56#define CVMX_SSO_WQ_IQ_DIS (CVMX_ADD_IO_SEG(0x0001670000001010ull))
  57#define CVMX_SSO_WQ_INT_PC (CVMX_ADD_IO_SEG(0x0001670000001020ull))
  58#define CVMX_SSO_PPX_GRP_MSK(offset) (CVMX_ADD_IO_SEG(0x0001670000006000ull) + ((offset) & 31) * 8)
  59#define CVMX_SSO_WQ_INT_THRX(offset) (CVMX_ADD_IO_SEG(0x0001670000007000ull) + ((offset) & 63) * 8)
  60
  61union cvmx_pow_bist_stat {
  62	uint64_t u64;
  63	struct cvmx_pow_bist_stat_s {
  64#ifdef __BIG_ENDIAN_BITFIELD
  65		uint64_t reserved_32_63:32;
  66		uint64_t pp:16;
  67		uint64_t reserved_0_15:16;
  68#else
  69		uint64_t reserved_0_15:16;
  70		uint64_t pp:16;
  71		uint64_t reserved_32_63:32;
  72#endif
  73	} s;
  74	struct cvmx_pow_bist_stat_cn30xx {
  75#ifdef __BIG_ENDIAN_BITFIELD
  76		uint64_t reserved_17_63:47;
  77		uint64_t pp:1;
  78		uint64_t reserved_9_15:7;
  79		uint64_t cam:1;
  80		uint64_t nbt1:1;
  81		uint64_t nbt0:1;
  82		uint64_t index:1;
  83		uint64_t fidx:1;
  84		uint64_t nbr1:1;
  85		uint64_t nbr0:1;
  86		uint64_t pend:1;
  87		uint64_t adr:1;
  88#else
  89		uint64_t adr:1;
  90		uint64_t pend:1;
  91		uint64_t nbr0:1;
  92		uint64_t nbr1:1;
  93		uint64_t fidx:1;
  94		uint64_t index:1;
  95		uint64_t nbt0:1;
  96		uint64_t nbt1:1;
  97		uint64_t cam:1;
  98		uint64_t reserved_9_15:7;
  99		uint64_t pp:1;
 100		uint64_t reserved_17_63:47;
 101#endif
 102	} cn30xx;
 103	struct cvmx_pow_bist_stat_cn31xx {
 104#ifdef __BIG_ENDIAN_BITFIELD
 105		uint64_t reserved_18_63:46;
 106		uint64_t pp:2;
 107		uint64_t reserved_9_15:7;
 108		uint64_t cam:1;
 109		uint64_t nbt1:1;
 110		uint64_t nbt0:1;
 111		uint64_t index:1;
 112		uint64_t fidx:1;
 113		uint64_t nbr1:1;
 114		uint64_t nbr0:1;
 115		uint64_t pend:1;
 116		uint64_t adr:1;
 117#else
 118		uint64_t adr:1;
 119		uint64_t pend:1;
 120		uint64_t nbr0:1;
 121		uint64_t nbr1:1;
 122		uint64_t fidx:1;
 123		uint64_t index:1;
 124		uint64_t nbt0:1;
 125		uint64_t nbt1:1;
 126		uint64_t cam:1;
 127		uint64_t reserved_9_15:7;
 128		uint64_t pp:2;
 129		uint64_t reserved_18_63:46;
 130#endif
 131	} cn31xx;
 132	struct cvmx_pow_bist_stat_cn38xx {
 133#ifdef __BIG_ENDIAN_BITFIELD
 134		uint64_t reserved_32_63:32;
 135		uint64_t pp:16;
 136		uint64_t reserved_10_15:6;
 137		uint64_t cam:1;
 138		uint64_t nbt:1;
 139		uint64_t index:1;
 140		uint64_t fidx:1;
 141		uint64_t nbr1:1;
 142		uint64_t nbr0:1;
 143		uint64_t pend1:1;
 144		uint64_t pend0:1;
 145		uint64_t adr1:1;
 146		uint64_t adr0:1;
 147#else
 148		uint64_t adr0:1;
 149		uint64_t adr1:1;
 150		uint64_t pend0:1;
 151		uint64_t pend1:1;
 152		uint64_t nbr0:1;
 153		uint64_t nbr1:1;
 154		uint64_t fidx:1;
 155		uint64_t index:1;
 156		uint64_t nbt:1;
 157		uint64_t cam:1;
 158		uint64_t reserved_10_15:6;
 159		uint64_t pp:16;
 160		uint64_t reserved_32_63:32;
 161#endif
 162	} cn38xx;
 163	struct cvmx_pow_bist_stat_cn52xx {
 164#ifdef __BIG_ENDIAN_BITFIELD
 165		uint64_t reserved_20_63:44;
 166		uint64_t pp:4;
 167		uint64_t reserved_9_15:7;
 168		uint64_t cam:1;
 169		uint64_t nbt1:1;
 170		uint64_t nbt0:1;
 171		uint64_t index:1;
 172		uint64_t fidx:1;
 173		uint64_t nbr1:1;
 174		uint64_t nbr0:1;
 175		uint64_t pend:1;
 176		uint64_t adr:1;
 177#else
 178		uint64_t adr:1;
 179		uint64_t pend:1;
 180		uint64_t nbr0:1;
 181		uint64_t nbr1:1;
 182		uint64_t fidx:1;
 183		uint64_t index:1;
 184		uint64_t nbt0:1;
 185		uint64_t nbt1:1;
 186		uint64_t cam:1;
 187		uint64_t reserved_9_15:7;
 188		uint64_t pp:4;
 189		uint64_t reserved_20_63:44;
 190#endif
 191	} cn52xx;
 192	struct cvmx_pow_bist_stat_cn56xx {
 193#ifdef __BIG_ENDIAN_BITFIELD
 194		uint64_t reserved_28_63:36;
 195		uint64_t pp:12;
 196		uint64_t reserved_10_15:6;
 197		uint64_t cam:1;
 198		uint64_t nbt:1;
 199		uint64_t index:1;
 200		uint64_t fidx:1;
 201		uint64_t nbr1:1;
 202		uint64_t nbr0:1;
 203		uint64_t pend1:1;
 204		uint64_t pend0:1;
 205		uint64_t adr1:1;
 206		uint64_t adr0:1;
 207#else
 208		uint64_t adr0:1;
 209		uint64_t adr1:1;
 210		uint64_t pend0:1;
 211		uint64_t pend1:1;
 212		uint64_t nbr0:1;
 213		uint64_t nbr1:1;
 214		uint64_t fidx:1;
 215		uint64_t index:1;
 216		uint64_t nbt:1;
 217		uint64_t cam:1;
 218		uint64_t reserved_10_15:6;
 219		uint64_t pp:12;
 220		uint64_t reserved_28_63:36;
 221#endif
 222	} cn56xx;
 223	struct cvmx_pow_bist_stat_cn61xx {
 224#ifdef __BIG_ENDIAN_BITFIELD
 225		uint64_t reserved_20_63:44;
 226		uint64_t pp:4;
 227		uint64_t reserved_12_15:4;
 228		uint64_t cam:1;
 229		uint64_t nbr:3;
 230		uint64_t nbt:4;
 231		uint64_t index:1;
 232		uint64_t fidx:1;
 233		uint64_t pend:1;
 234		uint64_t adr:1;
 235#else
 236		uint64_t adr:1;
 237		uint64_t pend:1;
 238		uint64_t fidx:1;
 239		uint64_t index:1;
 240		uint64_t nbt:4;
 241		uint64_t nbr:3;
 242		uint64_t cam:1;
 243		uint64_t reserved_12_15:4;
 244		uint64_t pp:4;
 245		uint64_t reserved_20_63:44;
 246#endif
 247	} cn61xx;
 248	struct cvmx_pow_bist_stat_cn63xx {
 249#ifdef __BIG_ENDIAN_BITFIELD
 250		uint64_t reserved_22_63:42;
 251		uint64_t pp:6;
 252		uint64_t reserved_12_15:4;
 253		uint64_t cam:1;
 254		uint64_t nbr:3;
 255		uint64_t nbt:4;
 256		uint64_t index:1;
 257		uint64_t fidx:1;
 258		uint64_t pend:1;
 259		uint64_t adr:1;
 260#else
 261		uint64_t adr:1;
 262		uint64_t pend:1;
 263		uint64_t fidx:1;
 264		uint64_t index:1;
 265		uint64_t nbt:4;
 266		uint64_t nbr:3;
 267		uint64_t cam:1;
 268		uint64_t reserved_12_15:4;
 269		uint64_t pp:6;
 270		uint64_t reserved_22_63:42;
 271#endif
 272	} cn63xx;
 273	struct cvmx_pow_bist_stat_cn66xx {
 274#ifdef __BIG_ENDIAN_BITFIELD
 275		uint64_t reserved_26_63:38;
 276		uint64_t pp:10;
 277		uint64_t reserved_12_15:4;
 278		uint64_t cam:1;
 279		uint64_t nbr:3;
 280		uint64_t nbt:4;
 281		uint64_t index:1;
 282		uint64_t fidx:1;
 283		uint64_t pend:1;
 284		uint64_t adr:1;
 285#else
 286		uint64_t adr:1;
 287		uint64_t pend:1;
 288		uint64_t fidx:1;
 289		uint64_t index:1;
 290		uint64_t nbt:4;
 291		uint64_t nbr:3;
 292		uint64_t cam:1;
 293		uint64_t reserved_12_15:4;
 294		uint64_t pp:10;
 295		uint64_t reserved_26_63:38;
 296#endif
 297	} cn66xx;
 298};
 299
 300union cvmx_pow_ds_pc {
 301	uint64_t u64;
 302	struct cvmx_pow_ds_pc_s {
 303#ifdef __BIG_ENDIAN_BITFIELD
 304		uint64_t reserved_32_63:32;
 305		uint64_t ds_pc:32;
 306#else
 307		uint64_t ds_pc:32;
 308		uint64_t reserved_32_63:32;
 309#endif
 310	} s;
 311};
 312
 313union cvmx_pow_ecc_err {
 314	uint64_t u64;
 315	struct cvmx_pow_ecc_err_s {
 316#ifdef __BIG_ENDIAN_BITFIELD
 317		uint64_t reserved_45_63:19;
 318		uint64_t iop_ie:13;
 319		uint64_t reserved_29_31:3;
 320		uint64_t iop:13;
 321		uint64_t reserved_14_15:2;
 322		uint64_t rpe_ie:1;
 323		uint64_t rpe:1;
 324		uint64_t reserved_9_11:3;
 325		uint64_t syn:5;
 326		uint64_t dbe_ie:1;
 327		uint64_t sbe_ie:1;
 328		uint64_t dbe:1;
 329		uint64_t sbe:1;
 330#else
 331		uint64_t sbe:1;
 332		uint64_t dbe:1;
 333		uint64_t sbe_ie:1;
 334		uint64_t dbe_ie:1;
 335		uint64_t syn:5;
 336		uint64_t reserved_9_11:3;
 337		uint64_t rpe:1;
 338		uint64_t rpe_ie:1;
 339		uint64_t reserved_14_15:2;
 340		uint64_t iop:13;
 341		uint64_t reserved_29_31:3;
 342		uint64_t iop_ie:13;
 343		uint64_t reserved_45_63:19;
 344#endif
 345	} s;
 346	struct cvmx_pow_ecc_err_cn31xx {
 347#ifdef __BIG_ENDIAN_BITFIELD
 348		uint64_t reserved_14_63:50;
 349		uint64_t rpe_ie:1;
 350		uint64_t rpe:1;
 351		uint64_t reserved_9_11:3;
 352		uint64_t syn:5;
 353		uint64_t dbe_ie:1;
 354		uint64_t sbe_ie:1;
 355		uint64_t dbe:1;
 356		uint64_t sbe:1;
 357#else
 358		uint64_t sbe:1;
 359		uint64_t dbe:1;
 360		uint64_t sbe_ie:1;
 361		uint64_t dbe_ie:1;
 362		uint64_t syn:5;
 363		uint64_t reserved_9_11:3;
 364		uint64_t rpe:1;
 365		uint64_t rpe_ie:1;
 366		uint64_t reserved_14_63:50;
 367#endif
 368	} cn31xx;
 369};
 370
 371union cvmx_pow_int_ctl {
 372	uint64_t u64;
 373	struct cvmx_pow_int_ctl_s {
 374#ifdef __BIG_ENDIAN_BITFIELD
 375		uint64_t reserved_6_63:58;
 376		uint64_t pfr_dis:1;
 377		uint64_t nbr_thr:5;
 378#else
 379		uint64_t nbr_thr:5;
 380		uint64_t pfr_dis:1;
 381		uint64_t reserved_6_63:58;
 382#endif
 383	} s;
 384};
 385
 386union cvmx_pow_iq_cntx {
 387	uint64_t u64;
 388	struct cvmx_pow_iq_cntx_s {
 389#ifdef __BIG_ENDIAN_BITFIELD
 390		uint64_t reserved_32_63:32;
 391		uint64_t iq_cnt:32;
 392#else
 393		uint64_t iq_cnt:32;
 394		uint64_t reserved_32_63:32;
 395#endif
 396	} s;
 397};
 398
 399union cvmx_pow_iq_com_cnt {
 400	uint64_t u64;
 401	struct cvmx_pow_iq_com_cnt_s {
 402#ifdef __BIG_ENDIAN_BITFIELD
 403		uint64_t reserved_32_63:32;
 404		uint64_t iq_cnt:32;
 405#else
 406		uint64_t iq_cnt:32;
 407		uint64_t reserved_32_63:32;
 408#endif
 409	} s;
 410};
 411
 412union cvmx_pow_iq_int {
 413	uint64_t u64;
 414	struct cvmx_pow_iq_int_s {
 415#ifdef __BIG_ENDIAN_BITFIELD
 416		uint64_t reserved_8_63:56;
 417		uint64_t iq_int:8;
 418#else
 419		uint64_t iq_int:8;
 420		uint64_t reserved_8_63:56;
 421#endif
 422	} s;
 423};
 424
 425union cvmx_pow_iq_int_en {
 426	uint64_t u64;
 427	struct cvmx_pow_iq_int_en_s {
 428#ifdef __BIG_ENDIAN_BITFIELD
 429		uint64_t reserved_8_63:56;
 430		uint64_t int_en:8;
 431#else
 432		uint64_t int_en:8;
 433		uint64_t reserved_8_63:56;
 434#endif
 435	} s;
 436};
 437
 438union cvmx_pow_iq_thrx {
 439	uint64_t u64;
 440	struct cvmx_pow_iq_thrx_s {
 441#ifdef __BIG_ENDIAN_BITFIELD
 442		uint64_t reserved_32_63:32;
 443		uint64_t iq_thr:32;
 444#else
 445		uint64_t iq_thr:32;
 446		uint64_t reserved_32_63:32;
 447#endif
 448	} s;
 449};
 450
 451union cvmx_pow_nos_cnt {
 452	uint64_t u64;
 453	struct cvmx_pow_nos_cnt_s {
 454#ifdef __BIG_ENDIAN_BITFIELD
 455		uint64_t reserved_12_63:52;
 456		uint64_t nos_cnt:12;
 457#else
 458		uint64_t nos_cnt:12;
 459		uint64_t reserved_12_63:52;
 460#endif
 461	} s;
 462	struct cvmx_pow_nos_cnt_cn30xx {
 463#ifdef __BIG_ENDIAN_BITFIELD
 464		uint64_t reserved_7_63:57;
 465		uint64_t nos_cnt:7;
 466#else
 467		uint64_t nos_cnt:7;
 468		uint64_t reserved_7_63:57;
 469#endif
 470	} cn30xx;
 471	struct cvmx_pow_nos_cnt_cn31xx {
 472#ifdef __BIG_ENDIAN_BITFIELD
 473		uint64_t reserved_9_63:55;
 474		uint64_t nos_cnt:9;
 475#else
 476		uint64_t nos_cnt:9;
 477		uint64_t reserved_9_63:55;
 478#endif
 479	} cn31xx;
 480	struct cvmx_pow_nos_cnt_cn52xx {
 481#ifdef __BIG_ENDIAN_BITFIELD
 482		uint64_t reserved_10_63:54;
 483		uint64_t nos_cnt:10;
 484#else
 485		uint64_t nos_cnt:10;
 486		uint64_t reserved_10_63:54;
 487#endif
 488	} cn52xx;
 489	struct cvmx_pow_nos_cnt_cn63xx {
 490#ifdef __BIG_ENDIAN_BITFIELD
 491		uint64_t reserved_11_63:53;
 492		uint64_t nos_cnt:11;
 493#else
 494		uint64_t nos_cnt:11;
 495		uint64_t reserved_11_63:53;
 496#endif
 497	} cn63xx;
 498};
 499
 500union cvmx_pow_nw_tim {
 501	uint64_t u64;
 502	struct cvmx_pow_nw_tim_s {
 503#ifdef __BIG_ENDIAN_BITFIELD
 504		uint64_t reserved_10_63:54;
 505		uint64_t nw_tim:10;
 506#else
 507		uint64_t nw_tim:10;
 508		uint64_t reserved_10_63:54;
 509#endif
 510	} s;
 511};
 512
 513union cvmx_pow_pf_rst_msk {
 514	uint64_t u64;
 515	struct cvmx_pow_pf_rst_msk_s {
 516#ifdef __BIG_ENDIAN_BITFIELD
 517		uint64_t reserved_8_63:56;
 518		uint64_t rst_msk:8;
 519#else
 520		uint64_t rst_msk:8;
 521		uint64_t reserved_8_63:56;
 522#endif
 523	} s;
 524};
 525
 526union cvmx_pow_pp_grp_mskx {
 527	uint64_t u64;
 528	struct cvmx_pow_pp_grp_mskx_s {
 529#ifdef __BIG_ENDIAN_BITFIELD
 530		uint64_t reserved_48_63:16;
 531		uint64_t qos7_pri:4;
 532		uint64_t qos6_pri:4;
 533		uint64_t qos5_pri:4;
 534		uint64_t qos4_pri:4;
 535		uint64_t qos3_pri:4;
 536		uint64_t qos2_pri:4;
 537		uint64_t qos1_pri:4;
 538		uint64_t qos0_pri:4;
 539		uint64_t grp_msk:16;
 540#else
 541		uint64_t grp_msk:16;
 542		uint64_t qos0_pri:4;
 543		uint64_t qos1_pri:4;
 544		uint64_t qos2_pri:4;
 545		uint64_t qos3_pri:4;
 546		uint64_t qos4_pri:4;
 547		uint64_t qos5_pri:4;
 548		uint64_t qos6_pri:4;
 549		uint64_t qos7_pri:4;
 550		uint64_t reserved_48_63:16;
 551#endif
 552	} s;
 553	struct cvmx_pow_pp_grp_mskx_cn30xx {
 554#ifdef __BIG_ENDIAN_BITFIELD
 555		uint64_t reserved_16_63:48;
 556		uint64_t grp_msk:16;
 557#else
 558		uint64_t grp_msk:16;
 559		uint64_t reserved_16_63:48;
 560#endif
 561	} cn30xx;
 562};
 563
 564union cvmx_pow_qos_rndx {
 565	uint64_t u64;
 566	struct cvmx_pow_qos_rndx_s {
 567#ifdef __BIG_ENDIAN_BITFIELD
 568		uint64_t reserved_32_63:32;
 569		uint64_t rnd_p3:8;
 570		uint64_t rnd_p2:8;
 571		uint64_t rnd_p1:8;
 572		uint64_t rnd:8;
 573#else
 574		uint64_t rnd:8;
 575		uint64_t rnd_p1:8;
 576		uint64_t rnd_p2:8;
 577		uint64_t rnd_p3:8;
 578		uint64_t reserved_32_63:32;
 579#endif
 580	} s;
 581};
 582
 583union cvmx_pow_qos_thrx {
 584	uint64_t u64;
 585	struct cvmx_pow_qos_thrx_s {
 586#ifdef __BIG_ENDIAN_BITFIELD
 587		uint64_t reserved_60_63:4;
 588		uint64_t des_cnt:12;
 589		uint64_t buf_cnt:12;
 590		uint64_t free_cnt:12;
 591		uint64_t reserved_23_23:1;
 592		uint64_t max_thr:11;
 593		uint64_t reserved_11_11:1;
 594		uint64_t min_thr:11;
 595#else
 596		uint64_t min_thr:11;
 597		uint64_t reserved_11_11:1;
 598		uint64_t max_thr:11;
 599		uint64_t reserved_23_23:1;
 600		uint64_t free_cnt:12;
 601		uint64_t buf_cnt:12;
 602		uint64_t des_cnt:12;
 603		uint64_t reserved_60_63:4;
 604#endif
 605	} s;
 606	struct cvmx_pow_qos_thrx_cn30xx {
 607#ifdef __BIG_ENDIAN_BITFIELD
 608		uint64_t reserved_55_63:9;
 609		uint64_t des_cnt:7;
 610		uint64_t reserved_43_47:5;
 611		uint64_t buf_cnt:7;
 612		uint64_t reserved_31_35:5;
 613		uint64_t free_cnt:7;
 614		uint64_t reserved_18_23:6;
 615		uint64_t max_thr:6;
 616		uint64_t reserved_6_11:6;
 617		uint64_t min_thr:6;
 618#else
 619		uint64_t min_thr:6;
 620		uint64_t reserved_6_11:6;
 621		uint64_t max_thr:6;
 622		uint64_t reserved_18_23:6;
 623		uint64_t free_cnt:7;
 624		uint64_t reserved_31_35:5;
 625		uint64_t buf_cnt:7;
 626		uint64_t reserved_43_47:5;
 627		uint64_t des_cnt:7;
 628		uint64_t reserved_55_63:9;
 629#endif
 630	} cn30xx;
 631	struct cvmx_pow_qos_thrx_cn31xx {
 632#ifdef __BIG_ENDIAN_BITFIELD
 633		uint64_t reserved_57_63:7;
 634		uint64_t des_cnt:9;
 635		uint64_t reserved_45_47:3;
 636		uint64_t buf_cnt:9;
 637		uint64_t reserved_33_35:3;
 638		uint64_t free_cnt:9;
 639		uint64_t reserved_20_23:4;
 640		uint64_t max_thr:8;
 641		uint64_t reserved_8_11:4;
 642		uint64_t min_thr:8;
 643#else
 644		uint64_t min_thr:8;
 645		uint64_t reserved_8_11:4;
 646		uint64_t max_thr:8;
 647		uint64_t reserved_20_23:4;
 648		uint64_t free_cnt:9;
 649		uint64_t reserved_33_35:3;
 650		uint64_t buf_cnt:9;
 651		uint64_t reserved_45_47:3;
 652		uint64_t des_cnt:9;
 653		uint64_t reserved_57_63:7;
 654#endif
 655	} cn31xx;
 656	struct cvmx_pow_qos_thrx_cn52xx {
 657#ifdef __BIG_ENDIAN_BITFIELD
 658		uint64_t reserved_58_63:6;
 659		uint64_t des_cnt:10;
 660		uint64_t reserved_46_47:2;
 661		uint64_t buf_cnt:10;
 662		uint64_t reserved_34_35:2;
 663		uint64_t free_cnt:10;
 664		uint64_t reserved_21_23:3;
 665		uint64_t max_thr:9;
 666		uint64_t reserved_9_11:3;
 667		uint64_t min_thr:9;
 668#else
 669		uint64_t min_thr:9;
 670		uint64_t reserved_9_11:3;
 671		uint64_t max_thr:9;
 672		uint64_t reserved_21_23:3;
 673		uint64_t free_cnt:10;
 674		uint64_t reserved_34_35:2;
 675		uint64_t buf_cnt:10;
 676		uint64_t reserved_46_47:2;
 677		uint64_t des_cnt:10;
 678		uint64_t reserved_58_63:6;
 679#endif
 680	} cn52xx;
 681	struct cvmx_pow_qos_thrx_cn63xx {
 682#ifdef __BIG_ENDIAN_BITFIELD
 683		uint64_t reserved_59_63:5;
 684		uint64_t des_cnt:11;
 685		uint64_t reserved_47_47:1;
 686		uint64_t buf_cnt:11;
 687		uint64_t reserved_35_35:1;
 688		uint64_t free_cnt:11;
 689		uint64_t reserved_22_23:2;
 690		uint64_t max_thr:10;
 691		uint64_t reserved_10_11:2;
 692		uint64_t min_thr:10;
 693#else
 694		uint64_t min_thr:10;
 695		uint64_t reserved_10_11:2;
 696		uint64_t max_thr:10;
 697		uint64_t reserved_22_23:2;
 698		uint64_t free_cnt:11;
 699		uint64_t reserved_35_35:1;
 700		uint64_t buf_cnt:11;
 701		uint64_t reserved_47_47:1;
 702		uint64_t des_cnt:11;
 703		uint64_t reserved_59_63:5;
 704#endif
 705	} cn63xx;
 706};
 707
 708union cvmx_pow_ts_pc {
 709	uint64_t u64;
 710	struct cvmx_pow_ts_pc_s {
 711#ifdef __BIG_ENDIAN_BITFIELD
 712		uint64_t reserved_32_63:32;
 713		uint64_t ts_pc:32;
 714#else
 715		uint64_t ts_pc:32;
 716		uint64_t reserved_32_63:32;
 717#endif
 718	} s;
 719};
 720
 721union cvmx_pow_wa_com_pc {
 722	uint64_t u64;
 723	struct cvmx_pow_wa_com_pc_s {
 724#ifdef __BIG_ENDIAN_BITFIELD
 725		uint64_t reserved_32_63:32;
 726		uint64_t wa_pc:32;
 727#else
 728		uint64_t wa_pc:32;
 729		uint64_t reserved_32_63:32;
 730#endif
 731	} s;
 732};
 733
 734union cvmx_pow_wa_pcx {
 735	uint64_t u64;
 736	struct cvmx_pow_wa_pcx_s {
 737#ifdef __BIG_ENDIAN_BITFIELD
 738		uint64_t reserved_32_63:32;
 739		uint64_t wa_pc:32;
 740#else
 741		uint64_t wa_pc:32;
 742		uint64_t reserved_32_63:32;
 743#endif
 744	} s;
 745};
 746
 747union cvmx_pow_wq_int {
 748	uint64_t u64;
 749	struct cvmx_pow_wq_int_s {
 750#ifdef __BIG_ENDIAN_BITFIELD
 751		uint64_t reserved_32_63:32;
 752		uint64_t iq_dis:16;
 753		uint64_t wq_int:16;
 754#else
 755		uint64_t wq_int:16;
 756		uint64_t iq_dis:16;
 757		uint64_t reserved_32_63:32;
 758#endif
 759	} s;
 760};
 761
 762union cvmx_pow_wq_int_cntx {
 763	uint64_t u64;
 764	struct cvmx_pow_wq_int_cntx_s {
 765#ifdef __BIG_ENDIAN_BITFIELD
 766		uint64_t reserved_28_63:36;
 767		uint64_t tc_cnt:4;
 768		uint64_t ds_cnt:12;
 769		uint64_t iq_cnt:12;
 770#else
 771		uint64_t iq_cnt:12;
 772		uint64_t ds_cnt:12;
 773		uint64_t tc_cnt:4;
 774		uint64_t reserved_28_63:36;
 775#endif
 776	} s;
 777	struct cvmx_pow_wq_int_cntx_cn30xx {
 778#ifdef __BIG_ENDIAN_BITFIELD
 779		uint64_t reserved_28_63:36;
 780		uint64_t tc_cnt:4;
 781		uint64_t reserved_19_23:5;
 782		uint64_t ds_cnt:7;
 783		uint64_t reserved_7_11:5;
 784		uint64_t iq_cnt:7;
 785#else
 786		uint64_t iq_cnt:7;
 787		uint64_t reserved_7_11:5;
 788		uint64_t ds_cnt:7;
 789		uint64_t reserved_19_23:5;
 790		uint64_t tc_cnt:4;
 791		uint64_t reserved_28_63:36;
 792#endif
 793	} cn30xx;
 794	struct cvmx_pow_wq_int_cntx_cn31xx {
 795#ifdef __BIG_ENDIAN_BITFIELD
 796		uint64_t reserved_28_63:36;
 797		uint64_t tc_cnt:4;
 798		uint64_t reserved_21_23:3;
 799		uint64_t ds_cnt:9;
 800		uint64_t reserved_9_11:3;
 801		uint64_t iq_cnt:9;
 802#else
 803		uint64_t iq_cnt:9;
 804		uint64_t reserved_9_11:3;
 805		uint64_t ds_cnt:9;
 806		uint64_t reserved_21_23:3;
 807		uint64_t tc_cnt:4;
 808		uint64_t reserved_28_63:36;
 809#endif
 810	} cn31xx;
 811	struct cvmx_pow_wq_int_cntx_cn52xx {
 812#ifdef __BIG_ENDIAN_BITFIELD
 813		uint64_t reserved_28_63:36;
 814		uint64_t tc_cnt:4;
 815		uint64_t reserved_22_23:2;
 816		uint64_t ds_cnt:10;
 817		uint64_t reserved_10_11:2;
 818		uint64_t iq_cnt:10;
 819#else
 820		uint64_t iq_cnt:10;
 821		uint64_t reserved_10_11:2;
 822		uint64_t ds_cnt:10;
 823		uint64_t reserved_22_23:2;
 824		uint64_t tc_cnt:4;
 825		uint64_t reserved_28_63:36;
 826#endif
 827	} cn52xx;
 828	struct cvmx_pow_wq_int_cntx_cn63xx {
 829#ifdef __BIG_ENDIAN_BITFIELD
 830		uint64_t reserved_28_63:36;
 831		uint64_t tc_cnt:4;
 832		uint64_t reserved_23_23:1;
 833		uint64_t ds_cnt:11;
 834		uint64_t reserved_11_11:1;
 835		uint64_t iq_cnt:11;
 836#else
 837		uint64_t iq_cnt:11;
 838		uint64_t reserved_11_11:1;
 839		uint64_t ds_cnt:11;
 840		uint64_t reserved_23_23:1;
 841		uint64_t tc_cnt:4;
 842		uint64_t reserved_28_63:36;
 843#endif
 844	} cn63xx;
 845};
 846
 847union cvmx_pow_wq_int_pc {
 848	uint64_t u64;
 849	struct cvmx_pow_wq_int_pc_s {
 850#ifdef __BIG_ENDIAN_BITFIELD
 851		uint64_t reserved_60_63:4;
 852		uint64_t pc:28;
 853		uint64_t reserved_28_31:4;
 854		uint64_t pc_thr:20;
 855		uint64_t reserved_0_7:8;
 856#else
 857		uint64_t reserved_0_7:8;
 858		uint64_t pc_thr:20;
 859		uint64_t reserved_28_31:4;
 860		uint64_t pc:28;
 861		uint64_t reserved_60_63:4;
 862#endif
 863	} s;
 864};
 865
 866union cvmx_pow_wq_int_thrx {
 867	uint64_t u64;
 868	struct cvmx_pow_wq_int_thrx_s {
 869#ifdef __BIG_ENDIAN_BITFIELD
 870		uint64_t reserved_29_63:35;
 871		uint64_t tc_en:1;
 872		uint64_t tc_thr:4;
 873		uint64_t reserved_23_23:1;
 874		uint64_t ds_thr:11;
 875		uint64_t reserved_11_11:1;
 876		uint64_t iq_thr:11;
 877#else
 878		uint64_t iq_thr:11;
 879		uint64_t reserved_11_11:1;
 880		uint64_t ds_thr:11;
 881		uint64_t reserved_23_23:1;
 882		uint64_t tc_thr:4;
 883		uint64_t tc_en:1;
 884		uint64_t reserved_29_63:35;
 885#endif
 886	} s;
 887	struct cvmx_pow_wq_int_thrx_cn30xx {
 888#ifdef __BIG_ENDIAN_BITFIELD
 889		uint64_t reserved_29_63:35;
 890		uint64_t tc_en:1;
 891		uint64_t tc_thr:4;
 892		uint64_t reserved_18_23:6;
 893		uint64_t ds_thr:6;
 894		uint64_t reserved_6_11:6;
 895		uint64_t iq_thr:6;
 896#else
 897		uint64_t iq_thr:6;
 898		uint64_t reserved_6_11:6;
 899		uint64_t ds_thr:6;
 900		uint64_t reserved_18_23:6;
 901		uint64_t tc_thr:4;
 902		uint64_t tc_en:1;
 903		uint64_t reserved_29_63:35;
 904#endif
 905	} cn30xx;
 906	struct cvmx_pow_wq_int_thrx_cn31xx {
 907#ifdef __BIG_ENDIAN_BITFIELD
 908		uint64_t reserved_29_63:35;
 909		uint64_t tc_en:1;
 910		uint64_t tc_thr:4;
 911		uint64_t reserved_20_23:4;
 912		uint64_t ds_thr:8;
 913		uint64_t reserved_8_11:4;
 914		uint64_t iq_thr:8;
 915#else
 916		uint64_t iq_thr:8;
 917		uint64_t reserved_8_11:4;
 918		uint64_t ds_thr:8;
 919		uint64_t reserved_20_23:4;
 920		uint64_t tc_thr:4;
 921		uint64_t tc_en:1;
 922		uint64_t reserved_29_63:35;
 923#endif
 924	} cn31xx;
 925	struct cvmx_pow_wq_int_thrx_cn52xx {
 926#ifdef __BIG_ENDIAN_BITFIELD
 927		uint64_t reserved_29_63:35;
 928		uint64_t tc_en:1;
 929		uint64_t tc_thr:4;
 930		uint64_t reserved_21_23:3;
 931		uint64_t ds_thr:9;
 932		uint64_t reserved_9_11:3;
 933		uint64_t iq_thr:9;
 934#else
 935		uint64_t iq_thr:9;
 936		uint64_t reserved_9_11:3;
 937		uint64_t ds_thr:9;
 938		uint64_t reserved_21_23:3;
 939		uint64_t tc_thr:4;
 940		uint64_t tc_en:1;
 941		uint64_t reserved_29_63:35;
 942#endif
 943	} cn52xx;
 944	struct cvmx_pow_wq_int_thrx_cn63xx {
 945#ifdef __BIG_ENDIAN_BITFIELD
 946		uint64_t reserved_29_63:35;
 947		uint64_t tc_en:1;
 948		uint64_t tc_thr:4;
 949		uint64_t reserved_22_23:2;
 950		uint64_t ds_thr:10;
 951		uint64_t reserved_10_11:2;
 952		uint64_t iq_thr:10;
 953#else
 954		uint64_t iq_thr:10;
 955		uint64_t reserved_10_11:2;
 956		uint64_t ds_thr:10;
 957		uint64_t reserved_22_23:2;
 958		uint64_t tc_thr:4;
 959		uint64_t tc_en:1;
 960		uint64_t reserved_29_63:35;
 961#endif
 962	} cn63xx;
 963};
 964
 965union cvmx_pow_ws_pcx {
 966	uint64_t u64;
 967	struct cvmx_pow_ws_pcx_s {
 968#ifdef __BIG_ENDIAN_BITFIELD
 969		uint64_t reserved_32_63:32;
 970		uint64_t ws_pc:32;
 971#else
 972		uint64_t ws_pc:32;
 973		uint64_t reserved_32_63:32;
 974#endif
 975	} s;
 976};
 977
 978union cvmx_sso_wq_int_thrx {
 979	uint64_t u64;
 980	struct {
 981#ifdef __BIG_ENDIAN_BITFIELD
 982		uint64_t reserved_33_63:31;
 983		uint64_t tc_en:1;
 984		uint64_t tc_thr:4;
 985		uint64_t reserved_26_27:2;
 986		uint64_t ds_thr:12;
 987		uint64_t reserved_12_13:2;
 988		uint64_t iq_thr:12;
 989#else
 990		uint64_t iq_thr:12;
 991		uint64_t reserved_12_13:2;
 992		uint64_t ds_thr:12;
 993		uint64_t reserved_26_27:2;
 994		uint64_t tc_thr:4;
 995		uint64_t tc_en:1;
 996		uint64_t reserved_33_63:31;
 997#endif
 998	} s;
 999};
1000
1001#endif