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/arch/mips/include/asm/octeon/cvmx.h

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  1/***********************license start***************
  2 * Author: Cavium Networks
  3 *
  4 * Contact: support@caviumnetworks.com
  5 * This file is part of the OCTEON SDK
  6 *
  7 * Copyright (c) 2003-2017 Cavium, Inc.
  8 *
  9 * This file is free software; you can redistribute it and/or modify
 10 * it under the terms of the GNU General Public License, Version 2, as
 11 * published by the Free Software Foundation.
 12 *
 13 * This file is distributed in the hope that it will be useful, but
 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
 16 * NONINFRINGEMENT.  See the GNU General Public License for more
 17 * details.
 18 *
 19 * You should have received a copy of the GNU General Public License
 20 * along with this file; if not, write to the Free Software
 21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 22 * or visit http://www.gnu.org/licenses/.
 23 *
 24 * This file may also be available under a different license from Cavium.
 25 * Contact Cavium Networks for more information
 26 ***********************license end**************************************/
 27
 28#ifndef __CVMX_H__
 29#define __CVMX_H__
 30
 31#include <linux/kernel.h>
 32#include <linux/string.h>
 33#include <linux/delay.h>
 34
 35enum cvmx_mips_space {
 36	CVMX_MIPS_SPACE_XKSEG = 3LL,
 37	CVMX_MIPS_SPACE_XKPHYS = 2LL,
 38	CVMX_MIPS_SPACE_XSSEG = 1LL,
 39	CVMX_MIPS_SPACE_XUSEG = 0LL
 40};
 41
 42/* These macros for use when using 32 bit pointers. */
 43#define CVMX_MIPS32_SPACE_KSEG0 1l
 44#define CVMX_ADD_SEG32(segment, add) \
 45	(((int32_t)segment << 31) | (int32_t)(add))
 46
 47#define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS
 48
 49/* These macros simplify the process of creating common IO addresses */
 50#define CVMX_ADD_SEG(segment, add) \
 51	((((uint64_t)segment) << 62) | (add))
 52#ifndef CVMX_ADD_IO_SEG
 53#define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add))
 54#endif
 55
 56#include <asm/octeon/cvmx-asm.h>
 57#include <asm/octeon/cvmx-packet.h>
 58#include <asm/octeon/cvmx-sysinfo.h>
 59
 60#include <asm/octeon/cvmx-ciu-defs.h>
 61#include <asm/octeon/cvmx-ciu3-defs.h>
 62#include <asm/octeon/cvmx-gpio-defs.h>
 63#include <asm/octeon/cvmx-iob-defs.h>
 64#include <asm/octeon/cvmx-ipd-defs.h>
 65#include <asm/octeon/cvmx-l2c-defs.h>
 66#include <asm/octeon/cvmx-l2d-defs.h>
 67#include <asm/octeon/cvmx-l2t-defs.h>
 68#include <asm/octeon/cvmx-led-defs.h>
 69#include <asm/octeon/cvmx-mio-defs.h>
 70#include <asm/octeon/cvmx-pow-defs.h>
 71
 72#include <asm/octeon/cvmx-bootinfo.h>
 73#include <asm/octeon/cvmx-bootmem.h>
 74#include <asm/octeon/cvmx-l2c.h>
 75
 76#ifndef CVMX_ENABLE_DEBUG_PRINTS
 77#define CVMX_ENABLE_DEBUG_PRINTS 1
 78#endif
 79
 80#if CVMX_ENABLE_DEBUG_PRINTS
 81#define cvmx_dprintf	    printk
 82#else
 83#define cvmx_dprintf(...)   {}
 84#endif
 85
 86#define CVMX_MAX_CORES		(16)
 87#define CVMX_CACHE_LINE_SIZE	(128)	/* In bytes */
 88#define CVMX_CACHE_LINE_MASK	(CVMX_CACHE_LINE_SIZE - 1)	/* In bytes */
 89#define CVMX_CACHE_LINE_ALIGNED __attribute__ ((aligned(CVMX_CACHE_LINE_SIZE)))
 90#define CAST64(v) ((long long)(long)(v))
 91#define CASTPTR(type, v) ((type *)(long)(v))
 92
 93/*
 94 * Returns processor ID, different Linux and simple exec versions
 95 * provided in the cvmx-app-init*.c files.
 96 */
 97static inline uint32_t cvmx_get_proc_id(void) __attribute__ ((pure));
 98static inline uint32_t cvmx_get_proc_id(void)
 99{
100	uint32_t id;
101	asm("mfc0 %0, $15,0" : "=r"(id));
102	return id;
103}
104
105/* turn the variable name into a string */
106#define CVMX_TMP_STR(x) CVMX_TMP_STR2(x)
107#define CVMX_TMP_STR2(x) #x
108
109/**
110 * Builds a bit mask given the required size in bits.
111 *
112 * @bits:   Number of bits in the mask
113 * Returns The mask
114 */ static inline uint64_t cvmx_build_mask(uint64_t bits)
115{
116	return ~((~0x0ull) << bits);
117}
118
119/**
120 * Builds a memory address for I/O based on the Major and Sub DID.
121 *
122 * @major_did: 5 bit major did
123 * @sub_did:   3 bit sub did
124 * Returns I/O base address
125 */
126static inline uint64_t cvmx_build_io_address(uint64_t major_did,
127					     uint64_t sub_did)
128{
129	return (0x1ull << 48) | (major_did << 43) | (sub_did << 40);
130}
131
132/**
133 * Perform mask and shift to place the supplied value into
134 * the supplied bit rage.
135 *
136 * Example: cvmx_build_bits(39,24,value)
137 * <pre>
138 * 6	   5	   4	   3	   3	   2	   1
139 * 3	   5	   7	   9	   1	   3	   5	   7	  0
140 * +-------+-------+-------+-------+-------+-------+-------+------+
141 * 000000000000000000000000___________value000000000000000000000000
142 * </pre>
143 *
144 * @high_bit: Highest bit value can occupy (inclusive) 0-63
145 * @low_bit:  Lowest bit value can occupy inclusive 0-high_bit
146 * @value:    Value to use
147 * Returns Value masked and shifted
148 */
149static inline uint64_t cvmx_build_bits(uint64_t high_bit,
150				       uint64_t low_bit, uint64_t value)
151{
152	return (value & cvmx_build_mask(high_bit - low_bit + 1)) << low_bit;
153}
154
155/**
156 * Convert a memory pointer (void*) into a hardware compatible
157 * memory address (uint64_t). Octeon hardware widgets don't
158 * understand logical addresses.
159 *
160 * @ptr:    C style memory pointer
161 * Returns Hardware physical address
162 */
163static inline uint64_t cvmx_ptr_to_phys(void *ptr)
164{
165	if (sizeof(void *) == 8) {
166		/*
167		 * We're running in 64 bit mode. Normally this means
168		 * that we can use 40 bits of address space (the
169		 * hardware limit). Unfortunately there is one case
170		 * were we need to limit this to 30 bits, sign
171		 * extended 32 bit. Although these are 64 bits wide,
172		 * only 30 bits can be used.
173		 */
174		if ((CAST64(ptr) >> 62) == 3)
175			return CAST64(ptr) & cvmx_build_mask(30);
176		else
177			return CAST64(ptr) & cvmx_build_mask(40);
178	} else {
179		return (long)(ptr) & 0x1fffffff;
180	}
181}
182
183/**
184 * Convert a hardware physical address (uint64_t) into a
185 * memory pointer (void *).
186 *
187 * @physical_address:
188 *		 Hardware physical address to memory
189 * Returns Pointer to memory
190 */
191static inline void *cvmx_phys_to_ptr(uint64_t physical_address)
192{
193	if (sizeof(void *) == 8) {
194		/* Just set the top bit, avoiding any TLB ugliness */
195		return CASTPTR(void,
196			       CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
197					    physical_address));
198	} else {
199		return CASTPTR(void,
200			       CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0,
201					      physical_address));
202	}
203}
204
205/* The following #if controls the definition of the macro
206    CVMX_BUILD_WRITE64. This macro is used to build a store operation to
207    a full 64bit address. With a 64bit ABI, this can be done with a simple
208    pointer access. 32bit ABIs require more complicated assembly */
209
210/* We have a full 64bit ABI. Writing to a 64bit address can be done with
211    a simple volatile pointer */
212#define CVMX_BUILD_WRITE64(TYPE, ST)					\
213static inline void cvmx_write64_##TYPE(uint64_t addr, TYPE##_t val)	\
214{									\
215    *CASTPTR(volatile TYPE##_t, addr) = val;				\
216}
217
218
219/* The following #if controls the definition of the macro
220    CVMX_BUILD_READ64. This macro is used to build a load operation from
221    a full 64bit address. With a 64bit ABI, this can be done with a simple
222    pointer access. 32bit ABIs require more complicated assembly */
223
224/* We have a full 64bit ABI. Writing to a 64bit address can be done with
225    a simple volatile pointer */
226#define CVMX_BUILD_READ64(TYPE, LT)					\
227static inline TYPE##_t cvmx_read64_##TYPE(uint64_t addr)		\
228{									\
229	return *CASTPTR(volatile TYPE##_t, addr);			\
230}
231
232
233/* The following defines 8 functions for writing to a 64bit address. Each
234    takes two arguments, the address and the value to write.
235    cvmx_write64_int64	    cvmx_write64_uint64
236    cvmx_write64_int32	    cvmx_write64_uint32
237    cvmx_write64_int16	    cvmx_write64_uint16
238    cvmx_write64_int8	    cvmx_write64_uint8 */
239CVMX_BUILD_WRITE64(int64, "sd");
240CVMX_BUILD_WRITE64(int32, "sw");
241CVMX_BUILD_WRITE64(int16, "sh");
242CVMX_BUILD_WRITE64(int8, "sb");
243CVMX_BUILD_WRITE64(uint64, "sd");
244CVMX_BUILD_WRITE64(uint32, "sw");
245CVMX_BUILD_WRITE64(uint16, "sh");
246CVMX_BUILD_WRITE64(uint8, "sb");
247#define cvmx_write64 cvmx_write64_uint64
248
249/* The following defines 8 functions for reading from a 64bit address. Each
250    takes the address as the only argument
251    cvmx_read64_int64	    cvmx_read64_uint64
252    cvmx_read64_int32	    cvmx_read64_uint32
253    cvmx_read64_int16	    cvmx_read64_uint16
254    cvmx_read64_int8	    cvmx_read64_uint8 */
255CVMX_BUILD_READ64(int64, "ld");
256CVMX_BUILD_READ64(int32, "lw");
257CVMX_BUILD_READ64(int16, "lh");
258CVMX_BUILD_READ64(int8, "lb");
259CVMX_BUILD_READ64(uint64, "ld");
260CVMX_BUILD_READ64(uint32, "lw");
261CVMX_BUILD_READ64(uint16, "lhu");
262CVMX_BUILD_READ64(uint8, "lbu");
263#define cvmx_read64 cvmx_read64_uint64
264
265
266static inline void cvmx_write_csr(uint64_t csr_addr, uint64_t val)
267{
268	cvmx_write64(csr_addr, val);
269
270	/*
271	 * Perform an immediate read after every write to an RSL
272	 * register to force the write to complete. It doesn't matter
273	 * what RSL read we do, so we choose CVMX_MIO_BOOT_BIST_STAT
274	 * because it is fast and harmless.
275	 */
276	if (((csr_addr >> 40) & 0x7ffff) == (0x118))
277		cvmx_read64(CVMX_MIO_BOOT_BIST_STAT);
278}
279
280static inline void cvmx_writeq_csr(void __iomem *csr_addr, uint64_t val)
281{
282	cvmx_write_csr((__force uint64_t)csr_addr, val);
283}
284
285static inline void cvmx_write_io(uint64_t io_addr, uint64_t val)
286{
287	cvmx_write64(io_addr, val);
288
289}
290
291static inline uint64_t cvmx_read_csr(uint64_t csr_addr)
292{
293	uint64_t val = cvmx_read64(csr_addr);
294	return val;
295}
296
297static inline uint64_t cvmx_readq_csr(void __iomem *csr_addr)
298{
299	return cvmx_read_csr((__force uint64_t) csr_addr);
300}
301
302static inline void cvmx_send_single(uint64_t data)
303{
304	const uint64_t CVMX_IOBDMA_SENDSINGLE = 0xffffffffffffa200ull;
305	cvmx_write64(CVMX_IOBDMA_SENDSINGLE, data);
306}
307
308static inline void cvmx_read_csr_async(uint64_t scraddr, uint64_t csr_addr)
309{
310	union {
311		uint64_t u64;
312		struct {
313			uint64_t scraddr:8;
314			uint64_t len:8;
315			uint64_t addr:48;
316		} s;
317	} addr;
318	addr.u64 = csr_addr;
319	addr.s.scraddr = scraddr >> 3;
320	addr.s.len = 1;
321	cvmx_send_single(addr.u64);
322}
323
324/* Return true if Octeon is CN38XX pass 1 */
325static inline int cvmx_octeon_is_pass1(void)
326{
327#if OCTEON_IS_COMMON_BINARY()
328	return 0;	/* Pass 1 isn't supported for common binaries */
329#else
330/* Now that we know we're built for a specific model, only check CN38XX */
331#if OCTEON_IS_MODEL(OCTEON_CN38XX)
332	return cvmx_get_proc_id() == OCTEON_CN38XX_PASS1;
333#else
334	return 0;	/* Built for non CN38XX chip, we're not CN38XX pass1 */
335#endif
336#endif
337}
338
339static inline unsigned int cvmx_get_core_num(void)
340{
341	unsigned int core_num;
342	CVMX_RDHWRNV(core_num, 0);
343	return core_num;
344}
345
346/* Maximum # of bits to define core in node */
347#define CVMX_NODE_NO_SHIFT	7
348#define CVMX_NODE_MASK		0x3
349static inline unsigned int cvmx_get_node_num(void)
350{
351	unsigned int core_num = cvmx_get_core_num();
352
353	return (core_num >> CVMX_NODE_NO_SHIFT) & CVMX_NODE_MASK;
354}
355
356static inline unsigned int cvmx_get_local_core_num(void)
357{
358	return cvmx_get_core_num() & ((1 << CVMX_NODE_NO_SHIFT) - 1);
359}
360
361#define CVMX_NODE_BITS         (2)     /* Number of bits to define a node */
362#define CVMX_MAX_NODES         (1 << CVMX_NODE_BITS)
363#define CVMX_NODE_IO_SHIFT     (36)
364#define CVMX_NODE_MEM_SHIFT    (40)
365#define CVMX_NODE_IO_MASK      ((uint64_t)CVMX_NODE_MASK << CVMX_NODE_IO_SHIFT)
366
367static inline void cvmx_write_csr_node(uint64_t node, uint64_t csr_addr,
368				       uint64_t val)
369{
370	uint64_t composite_csr_addr, node_addr;
371
372	node_addr = (node & CVMX_NODE_MASK) << CVMX_NODE_IO_SHIFT;
373	composite_csr_addr = (csr_addr & ~CVMX_NODE_IO_MASK) | node_addr;
374
375	cvmx_write64_uint64(composite_csr_addr, val);
376	if (((csr_addr >> 40) & 0x7ffff) == (0x118))
377		cvmx_read64_uint64(CVMX_MIO_BOOT_BIST_STAT | node_addr);
378}
379
380static inline uint64_t cvmx_read_csr_node(uint64_t node, uint64_t csr_addr)
381{
382	uint64_t node_addr;
383
384	node_addr = (csr_addr & ~CVMX_NODE_IO_MASK) |
385		    (node & CVMX_NODE_MASK) << CVMX_NODE_IO_SHIFT;
386	return cvmx_read_csr(node_addr);
387}
388
389/**
390 * Returns the number of bits set in the provided value.
391 * Simple wrapper for POP instruction.
392 *
393 * @val:    32 bit value to count set bits in
394 *
395 * Returns Number of bits set
396 */
397static inline uint32_t cvmx_pop(uint32_t val)
398{
399	uint32_t pop;
400	CVMX_POP(pop, val);
401	return pop;
402}
403
404/**
405 * Returns the number of bits set in the provided value.
406 * Simple wrapper for DPOP instruction.
407 *
408 * @val:    64 bit value to count set bits in
409 *
410 * Returns Number of bits set
411 */
412static inline int cvmx_dpop(uint64_t val)
413{
414	int pop;
415	CVMX_DPOP(pop, val);
416	return pop;
417}
418
419/**
420 * Provide current cycle counter as a return value
421 *
422 * Returns current cycle counter
423 */
424
425static inline uint64_t cvmx_get_cycle(void)
426{
427	uint64_t cycle;
428	CVMX_RDHWR(cycle, 31);
429	return cycle;
430}
431
432/**
433 * Reads a chip global cycle counter.  This counts CPU cycles since
434 * chip reset.	The counter is 64 bit.
435 * This register does not exist on CN38XX pass 1 silicion
436 *
437 * Returns Global chip cycle count since chip reset.
438 */
439static inline uint64_t cvmx_get_cycle_global(void)
440{
441	if (cvmx_octeon_is_pass1())
442		return 0;
443	else
444		return cvmx_read64(CVMX_IPD_CLK_COUNT);
445}
446
447/**
448 * This macro spins on a field waiting for it to reach a value. It
449 * is common in code to need to wait for a specific field in a CSR
450 * to match a specific value. Conceptually this macro expands to:
451 *
452 * 1) read csr at "address" with a csr typedef of "type"
453 * 2) Check if ("type".s."field" "op" "value")
454 * 3) If #2 isn't true loop to #1 unless too much time has passed.
455 */
456#define CVMX_WAIT_FOR_FIELD64(address, type, field, op, value, timeout_usec)\
457    (									\
458{									\
459	int result;							\
460	do {								\
461		uint64_t done = cvmx_get_cycle() + (uint64_t)timeout_usec * \
462			cvmx_sysinfo_get()->cpu_clock_hz / 1000000;	\
463		type c;							\
464		while (1) {						\
465			c.u64 = cvmx_read_csr(address);			\
466			if ((c.s.field) op(value)) {			\
467				result = 0;				\
468				break;					\
469			} else if (cvmx_get_cycle() > done) {		\
470				result = -1;				\
471				break;					\
472			} else						\
473				__delay(100);				\
474		}							\
475	} while (0);							\
476	result;								\
477})
478
479/***************************************************************************/
480
481/* Return the number of cores available in the chip */
482static inline uint32_t cvmx_octeon_num_cores(void)
483{
484	u64 ciu_fuse_reg;
485	u64 ciu_fuse;
486
487	if (OCTEON_IS_OCTEON3() && !OCTEON_IS_MODEL(OCTEON_CN70XX))
488		ciu_fuse_reg = CVMX_CIU3_FUSE;
489	else
490		ciu_fuse_reg = CVMX_CIU_FUSE;
491	ciu_fuse = cvmx_read_csr(ciu_fuse_reg);
492	return cvmx_dpop(ciu_fuse);
493}
494
495#endif /*  __CVMX_H__  */