/arch/mips/include/asm/mach-pnx833x/gpio.h

http://github.com/mirrors/linux · C Header · 159 lines · 122 code · 13 blank · 24 comment · 12 complexity · b67cbc6516a36102955d936e8cd0db82 MD5 · raw file

  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * gpio.h: GPIO Support for PNX833X.
  4. *
  5. * Copyright 2008 NXP Semiconductors
  6. * Chris Steel <chris.steel@nxp.com>
  7. * Daniel Laird <daniel.j.laird@nxp.com>
  8. */
  9. #ifndef __ASM_MIPS_MACH_PNX833X_GPIO_H
  10. #define __ASM_MIPS_MACH_PNX833X_GPIO_H
  11. /* BIG FAT WARNING: races danger!
  12. No protections exist here. Current users are only early init code,
  13. when locking is not needed because no concurrency yet exists there,
  14. and GPIO IRQ dispatcher, which does locking.
  15. However, if many uses will ever happen, proper locking will be needed
  16. - including locking between different uses
  17. */
  18. #include <asm/mach-pnx833x/pnx833x.h>
  19. #define SET_REG_BIT(reg, bit) do { (reg |= (1 << (bit))); } while (0)
  20. #define CLEAR_REG_BIT(reg, bit) do { (reg &= ~(1 << (bit))); } while (0)
  21. /* Initialize GPIO to a known state */
  22. static inline void pnx833x_gpio_init(void)
  23. {
  24. PNX833X_PIO_DIR = 0;
  25. PNX833X_PIO_DIR2 = 0;
  26. PNX833X_PIO_SEL = 0;
  27. PNX833X_PIO_SEL2 = 0;
  28. PNX833X_PIO_INT_EDGE = 0;
  29. PNX833X_PIO_INT_HI = 0;
  30. PNX833X_PIO_INT_LO = 0;
  31. /* clear any GPIO interrupt requests */
  32. PNX833X_PIO_INT_CLEAR = 0xffff;
  33. PNX833X_PIO_INT_CLEAR = 0;
  34. PNX833X_PIO_INT_ENABLE = 0;
  35. }
  36. /* Select GPIO direction for a pin */
  37. static inline void pnx833x_gpio_select_input(unsigned int pin)
  38. {
  39. if (pin < 32)
  40. CLEAR_REG_BIT(PNX833X_PIO_DIR, pin);
  41. else
  42. CLEAR_REG_BIT(PNX833X_PIO_DIR2, pin & 31);
  43. }
  44. static inline void pnx833x_gpio_select_output(unsigned int pin)
  45. {
  46. if (pin < 32)
  47. SET_REG_BIT(PNX833X_PIO_DIR, pin);
  48. else
  49. SET_REG_BIT(PNX833X_PIO_DIR2, pin & 31);
  50. }
  51. /* Select GPIO or alternate function for a pin */
  52. static inline void pnx833x_gpio_select_function_io(unsigned int pin)
  53. {
  54. if (pin < 32)
  55. CLEAR_REG_BIT(PNX833X_PIO_SEL, pin);
  56. else
  57. CLEAR_REG_BIT(PNX833X_PIO_SEL2, pin & 31);
  58. }
  59. static inline void pnx833x_gpio_select_function_alt(unsigned int pin)
  60. {
  61. if (pin < 32)
  62. SET_REG_BIT(PNX833X_PIO_SEL, pin);
  63. else
  64. SET_REG_BIT(PNX833X_PIO_SEL2, pin & 31);
  65. }
  66. /* Read GPIO pin */
  67. static inline int pnx833x_gpio_read(unsigned int pin)
  68. {
  69. if (pin < 32)
  70. return (PNX833X_PIO_IN >> pin) & 1;
  71. else
  72. return (PNX833X_PIO_IN2 >> (pin & 31)) & 1;
  73. }
  74. /* Write GPIO pin */
  75. static inline void pnx833x_gpio_write(unsigned int val, unsigned int pin)
  76. {
  77. if (pin < 32) {
  78. if (val)
  79. SET_REG_BIT(PNX833X_PIO_OUT, pin);
  80. else
  81. CLEAR_REG_BIT(PNX833X_PIO_OUT, pin);
  82. } else {
  83. if (val)
  84. SET_REG_BIT(PNX833X_PIO_OUT2, pin & 31);
  85. else
  86. CLEAR_REG_BIT(PNX833X_PIO_OUT2, pin & 31);
  87. }
  88. }
  89. /* Configure GPIO interrupt */
  90. #define GPIO_INT_NONE 0
  91. #define GPIO_INT_LEVEL_LOW 1
  92. #define GPIO_INT_LEVEL_HIGH 2
  93. #define GPIO_INT_EDGE_RISING 3
  94. #define GPIO_INT_EDGE_FALLING 4
  95. #define GPIO_INT_EDGE_BOTH 5
  96. static inline void pnx833x_gpio_setup_irq(int when, unsigned int pin)
  97. {
  98. switch (when) {
  99. case GPIO_INT_LEVEL_LOW:
  100. CLEAR_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
  101. CLEAR_REG_BIT(PNX833X_PIO_INT_HI, pin);
  102. SET_REG_BIT(PNX833X_PIO_INT_LO, pin);
  103. break;
  104. case GPIO_INT_LEVEL_HIGH:
  105. CLEAR_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
  106. SET_REG_BIT(PNX833X_PIO_INT_HI, pin);
  107. CLEAR_REG_BIT(PNX833X_PIO_INT_LO, pin);
  108. break;
  109. case GPIO_INT_EDGE_RISING:
  110. SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
  111. SET_REG_BIT(PNX833X_PIO_INT_HI, pin);
  112. CLEAR_REG_BIT(PNX833X_PIO_INT_LO, pin);
  113. break;
  114. case GPIO_INT_EDGE_FALLING:
  115. SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
  116. CLEAR_REG_BIT(PNX833X_PIO_INT_HI, pin);
  117. SET_REG_BIT(PNX833X_PIO_INT_LO, pin);
  118. break;
  119. case GPIO_INT_EDGE_BOTH:
  120. SET_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
  121. SET_REG_BIT(PNX833X_PIO_INT_HI, pin);
  122. SET_REG_BIT(PNX833X_PIO_INT_LO, pin);
  123. break;
  124. default:
  125. CLEAR_REG_BIT(PNX833X_PIO_INT_EDGE, pin);
  126. CLEAR_REG_BIT(PNX833X_PIO_INT_HI, pin);
  127. CLEAR_REG_BIT(PNX833X_PIO_INT_LO, pin);
  128. break;
  129. }
  130. }
  131. /* Enable/disable GPIO interrupt */
  132. static inline void pnx833x_gpio_enable_irq(unsigned int pin)
  133. {
  134. SET_REG_BIT(PNX833X_PIO_INT_ENABLE, pin);
  135. }
  136. static inline void pnx833x_gpio_disable_irq(unsigned int pin)
  137. {
  138. CLEAR_REG_BIT(PNX833X_PIO_INT_ENABLE, pin);
  139. }
  140. /* Clear GPIO interrupt request */
  141. static inline void pnx833x_gpio_clear_irq(unsigned int pin)
  142. {
  143. SET_REG_BIT(PNX833X_PIO_INT_CLEAR, pin);
  144. CLEAR_REG_BIT(PNX833X_PIO_INT_CLEAR, pin);
  145. }
  146. #endif