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/arch/mips/include/asm/sibyte/sb1250_scd.h

http://github.com/mirrors/linux
C Header | 641 lines | 433 code | 126 blank | 82 comment | 6 complexity | d6d3c92e77b3da60174c940210373614 MD5 | raw file
  1/* SPDX-License-Identifier: GPL-2.0-or-later */
  2/*  *********************************************************************
  3    *  SB1250 Board Support Package
  4    *
  5    *  SCD Constants and Macros			File: sb1250_scd.h
  6    *
  7    *  This module contains constants and macros useful for
  8    *  manipulating the System Control and Debug module on the 1250.
  9    *
 10    *  SB1250 specification level:  User's manual 1/02/02
 11    *
 12    *********************************************************************
 13    *
 14    *  Copyright 2000,2001,2002,2003,2004,2005
 15    *  Broadcom Corporation. All rights reserved.
 16    *
 17    ********************************************************************* */
 18
 19#ifndef _SB1250_SCD_H
 20#define _SB1250_SCD_H
 21
 22#include <asm/sibyte/sb1250_defs.h>
 23
 24/*  *********************************************************************
 25    *  System control/debug registers
 26    ********************************************************************* */
 27
 28/*
 29 * System Revision Register (Table 4-1)
 30 */
 31
 32#define M_SYS_RESERVED		    _SB_MAKEMASK(8, 0)
 33
 34#define S_SYS_REVISION		    _SB_MAKE64(8)
 35#define M_SYS_REVISION		    _SB_MAKEMASK(8, S_SYS_REVISION)
 36#define V_SYS_REVISION(x)	    _SB_MAKEVALUE(x, S_SYS_REVISION)
 37#define G_SYS_REVISION(x)	    _SB_GETVALUE(x, S_SYS_REVISION, M_SYS_REVISION)
 38
 39#define K_SYS_REVISION_BCM1250_PASS1	0x01
 40
 41#define K_SYS_REVISION_BCM1250_PASS2	0x03
 42#define K_SYS_REVISION_BCM1250_A1	0x03	/* Pass 2.0 WB */
 43#define K_SYS_REVISION_BCM1250_A2	0x04	/* Pass 2.0 FC */
 44#define K_SYS_REVISION_BCM1250_A3	0x05	/* Pass 2.1 FC */
 45#define K_SYS_REVISION_BCM1250_A4	0x06	/* Pass 2.1 WB */
 46#define K_SYS_REVISION_BCM1250_A6	0x07	/* OR 0x04 (A2) w/WID != 0 */
 47#define K_SYS_REVISION_BCM1250_A8	0x0b	/* A8/A10 */
 48#define K_SYS_REVISION_BCM1250_A9	0x08
 49#define K_SYS_REVISION_BCM1250_A10	K_SYS_REVISION_BCM1250_A8
 50
 51#define K_SYS_REVISION_BCM1250_PASS2_2	0x10
 52#define K_SYS_REVISION_BCM1250_B0	K_SYS_REVISION_BCM1250_B1
 53#define K_SYS_REVISION_BCM1250_B1	0x10
 54#define K_SYS_REVISION_BCM1250_B2	0x11
 55
 56#define K_SYS_REVISION_BCM1250_C0	0x20
 57#define K_SYS_REVISION_BCM1250_C1	0x21
 58#define K_SYS_REVISION_BCM1250_C2	0x22
 59#define K_SYS_REVISION_BCM1250_C3	0x23
 60
 61#if SIBYTE_HDR_FEATURE_CHIP(1250)
 62/* XXX: discourage people from using these constants.  */
 63#define K_SYS_REVISION_PASS1	    K_SYS_REVISION_BCM1250_PASS1
 64#define K_SYS_REVISION_PASS2	    K_SYS_REVISION_BCM1250_PASS2
 65#define K_SYS_REVISION_PASS2_2	    K_SYS_REVISION_BCM1250_PASS2_2
 66#define K_SYS_REVISION_PASS3	    K_SYS_REVISION_BCM1250_PASS3
 67#define K_SYS_REVISION_BCM1250_PASS3	K_SYS_REVISION_BCM1250_C0
 68#endif /* 1250 */
 69
 70#define K_SYS_REVISION_BCM112x_A1	0x20
 71#define K_SYS_REVISION_BCM112x_A2	0x21
 72#define K_SYS_REVISION_BCM112x_A3	0x22
 73#define K_SYS_REVISION_BCM112x_A4	0x23
 74#define K_SYS_REVISION_BCM112x_B0	0x30
 75
 76#define K_SYS_REVISION_BCM1480_S0	0x01
 77#define K_SYS_REVISION_BCM1480_A1	0x02
 78#define K_SYS_REVISION_BCM1480_A2	0x03
 79#define K_SYS_REVISION_BCM1480_A3	0x04
 80#define K_SYS_REVISION_BCM1480_B0	0x11
 81
 82/*Cache size - 23:20  of revision register*/
 83#define S_SYS_L2C_SIZE		  _SB_MAKE64(20)
 84#define M_SYS_L2C_SIZE		  _SB_MAKEMASK(4, S_SYS_L2C_SIZE)
 85#define V_SYS_L2C_SIZE(x)	  _SB_MAKEVALUE(x, S_SYS_L2C_SIZE)
 86#define G_SYS_L2C_SIZE(x)	  _SB_GETVALUE(x, S_SYS_L2C_SIZE, M_SYS_L2C_SIZE)
 87
 88#define K_SYS_L2C_SIZE_1MB	0
 89#define K_SYS_L2C_SIZE_512KB	5
 90#define K_SYS_L2C_SIZE_256KB	2
 91#define K_SYS_L2C_SIZE_128KB	1
 92
 93#define K_SYS_L2C_SIZE_BCM1250	K_SYS_L2C_SIZE_512KB
 94#define K_SYS_L2C_SIZE_BCM1125	K_SYS_L2C_SIZE_256KB
 95#define K_SYS_L2C_SIZE_BCM1122	K_SYS_L2C_SIZE_128KB
 96
 97
 98/* Number of CPU cores, bits 27:24  of revision register*/
 99#define S_SYS_NUM_CPUS		  _SB_MAKE64(24)
100#define M_SYS_NUM_CPUS		  _SB_MAKEMASK(4, S_SYS_NUM_CPUS)
101#define V_SYS_NUM_CPUS(x)	  _SB_MAKEVALUE(x, S_SYS_NUM_CPUS)
102#define G_SYS_NUM_CPUS(x)	  _SB_GETVALUE(x, S_SYS_NUM_CPUS, M_SYS_NUM_CPUS)
103
104
105/* XXX: discourage people from using these constants.  */
106#define S_SYS_PART		    _SB_MAKE64(16)
107#define M_SYS_PART		    _SB_MAKEMASK(16, S_SYS_PART)
108#define V_SYS_PART(x)		    _SB_MAKEVALUE(x, S_SYS_PART)
109#define G_SYS_PART(x)		    _SB_GETVALUE(x, S_SYS_PART, M_SYS_PART)
110
111/* XXX: discourage people from using these constants.  */
112#define K_SYS_PART_SB1250	    0x1250
113#define K_SYS_PART_BCM1120	    0x1121
114#define K_SYS_PART_BCM1125	    0x1123
115#define K_SYS_PART_BCM1125H	    0x1124
116#define K_SYS_PART_BCM1122	    0x1113
117
118
119/* The "peripheral set" (SOC type) is the low 4 bits of the "part" field.  */
120#define S_SYS_SOC_TYPE		    _SB_MAKE64(16)
121#define M_SYS_SOC_TYPE		    _SB_MAKEMASK(4, S_SYS_SOC_TYPE)
122#define V_SYS_SOC_TYPE(x)	    _SB_MAKEVALUE(x, S_SYS_SOC_TYPE)
123#define G_SYS_SOC_TYPE(x)	    _SB_GETVALUE(x, S_SYS_SOC_TYPE, M_SYS_SOC_TYPE)
124
125#define K_SYS_SOC_TYPE_BCM1250	    0x0
126#define K_SYS_SOC_TYPE_BCM1120	    0x1
127#define K_SYS_SOC_TYPE_BCM1250_ALT  0x2		/* 1250pass2 w/ 1/4 L2.	 */
128#define K_SYS_SOC_TYPE_BCM1125	    0x3
129#define K_SYS_SOC_TYPE_BCM1125H	    0x4
130#define K_SYS_SOC_TYPE_BCM1250_ALT2 0x5		/* 1250pass2 w/ 1/2 L2.	 */
131#define K_SYS_SOC_TYPE_BCM1x80	    0x6
132#define K_SYS_SOC_TYPE_BCM1x55	    0x7
133
134/*
135 * Calculate correct SOC type given a copy of system revision register.
136 *
137 * (For the assembler version, sysrev and dest may be the same register.
138 * Also, it clobbers AT.)
139 */
140#ifdef __ASSEMBLER__
141#define SYS_SOC_TYPE(dest, sysrev)					\
142	.set push ;							\
143	.set reorder ;							\
144	dsrl	dest, sysrev, S_SYS_SOC_TYPE ;				\
145	andi	dest, dest, (M_SYS_SOC_TYPE >> S_SYS_SOC_TYPE);		\
146	beq	dest, K_SYS_SOC_TYPE_BCM1250_ALT, 991f ;		\
147	beq	dest, K_SYS_SOC_TYPE_BCM1250_ALT2, 991f	 ;		\
148	b	992f ;							\
149991:	li	dest, K_SYS_SOC_TYPE_BCM1250 ;				\
150992:									\
151	.set pop
152#else
153#define SYS_SOC_TYPE(sysrev)						\
154	((G_SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1250_ALT		\
155	  || G_SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1250_ALT2)	\
156	 ? K_SYS_SOC_TYPE_BCM1250 : G_SYS_SOC_TYPE(sysrev))
157#endif
158
159#define S_SYS_WID		    _SB_MAKE64(32)
160#define M_SYS_WID		    _SB_MAKEMASK(32, S_SYS_WID)
161#define V_SYS_WID(x)		    _SB_MAKEVALUE(x, S_SYS_WID)
162#define G_SYS_WID(x)		    _SB_GETVALUE(x, S_SYS_WID, M_SYS_WID)
163
164/*
165 * System Manufacturing Register
166 * Register: SCD_SYSTEM_MANUF
167 */
168
169#if SIBYTE_HDR_FEATURE_1250_112x
170/* Wafer ID: bits 31:0 */
171#define S_SYS_WAFERID1_200	  _SB_MAKE64(0)
172#define M_SYS_WAFERID1_200	  _SB_MAKEMASK(32, S_SYS_WAFERID1_200)
173#define V_SYS_WAFERID1_200(x)	  _SB_MAKEVALUE(x, S_SYS_WAFERID1_200)
174#define G_SYS_WAFERID1_200(x)	  _SB_GETVALUE(x, S_SYS_WAFERID1_200, M_SYS_WAFERID1_200)
175
176#define S_SYS_BIN		  _SB_MAKE64(32)
177#define M_SYS_BIN		  _SB_MAKEMASK(4, S_SYS_BIN)
178#define V_SYS_BIN(x)		  _SB_MAKEVALUE(x, S_SYS_BIN)
179#define G_SYS_BIN(x)		  _SB_GETVALUE(x, S_SYS_BIN, M_SYS_BIN)
180
181/* Wafer ID: bits 39:36 */
182#define S_SYS_WAFERID2_200	  _SB_MAKE64(36)
183#define M_SYS_WAFERID2_200	  _SB_MAKEMASK(4, S_SYS_WAFERID2_200)
184#define V_SYS_WAFERID2_200(x)	  _SB_MAKEVALUE(x, S_SYS_WAFERID2_200)
185#define G_SYS_WAFERID2_200(x)	  _SB_GETVALUE(x, S_SYS_WAFERID2_200, M_SYS_WAFERID2_200)
186
187/* Wafer ID: bits 39:0 */
188#define S_SYS_WAFERID_300	  _SB_MAKE64(0)
189#define M_SYS_WAFERID_300	  _SB_MAKEMASK(40, S_SYS_WAFERID_300)
190#define V_SYS_WAFERID_300(x)	  _SB_MAKEVALUE(x, S_SYS_WAFERID_300)
191#define G_SYS_WAFERID_300(x)	  _SB_GETVALUE(x, S_SYS_WAFERID_300, M_SYS_WAFERID_300)
192
193#define S_SYS_XPOS		  _SB_MAKE64(40)
194#define M_SYS_XPOS		  _SB_MAKEMASK(6, S_SYS_XPOS)
195#define V_SYS_XPOS(x)		  _SB_MAKEVALUE(x, S_SYS_XPOS)
196#define G_SYS_XPOS(x)		  _SB_GETVALUE(x, S_SYS_XPOS, M_SYS_XPOS)
197
198#define S_SYS_YPOS		  _SB_MAKE64(46)
199#define M_SYS_YPOS		  _SB_MAKEMASK(6, S_SYS_YPOS)
200#define V_SYS_YPOS(x)		  _SB_MAKEVALUE(x, S_SYS_YPOS)
201#define G_SYS_YPOS(x)		  _SB_GETVALUE(x, S_SYS_YPOS, M_SYS_YPOS)
202#endif
203
204
205/*
206 * System Config Register (Table 4-2)
207 * Register: SCD_SYSTEM_CFG
208 */
209
210#if SIBYTE_HDR_FEATURE_1250_112x
211#define M_SYS_LDT_PLL_BYP	    _SB_MAKEMASK1(3)
212#define M_SYS_PCI_SYNC_TEST_MODE    _SB_MAKEMASK1(4)
213#define M_SYS_IOB0_DIV		    _SB_MAKEMASK1(5)
214#define M_SYS_IOB1_DIV		    _SB_MAKEMASK1(6)
215
216#define S_SYS_PLL_DIV		    _SB_MAKE64(7)
217#define M_SYS_PLL_DIV		    _SB_MAKEMASK(5, S_SYS_PLL_DIV)
218#define V_SYS_PLL_DIV(x)	    _SB_MAKEVALUE(x, S_SYS_PLL_DIV)
219#define G_SYS_PLL_DIV(x)	    _SB_GETVALUE(x, S_SYS_PLL_DIV, M_SYS_PLL_DIV)
220
221#define M_SYS_SER0_ENABLE	    _SB_MAKEMASK1(12)
222#define M_SYS_SER0_RSTB_EN	    _SB_MAKEMASK1(13)
223#define M_SYS_SER1_ENABLE	    _SB_MAKEMASK1(14)
224#define M_SYS_SER1_RSTB_EN	    _SB_MAKEMASK1(15)
225#define M_SYS_PCMCIA_ENABLE	    _SB_MAKEMASK1(16)
226
227#define S_SYS_BOOT_MODE		    _SB_MAKE64(17)
228#define M_SYS_BOOT_MODE		    _SB_MAKEMASK(2, S_SYS_BOOT_MODE)
229#define V_SYS_BOOT_MODE(x)	    _SB_MAKEVALUE(x, S_SYS_BOOT_MODE)
230#define G_SYS_BOOT_MODE(x)	    _SB_GETVALUE(x, S_SYS_BOOT_MODE, M_SYS_BOOT_MODE)
231#define K_SYS_BOOT_MODE_ROM32	    0
232#define K_SYS_BOOT_MODE_ROM8	    1
233#define K_SYS_BOOT_MODE_SMBUS_SMALL 2
234#define K_SYS_BOOT_MODE_SMBUS_BIG   3
235
236#define M_SYS_PCI_HOST		    _SB_MAKEMASK1(19)
237#define M_SYS_PCI_ARBITER	    _SB_MAKEMASK1(20)
238#define M_SYS_SOUTH_ON_LDT	    _SB_MAKEMASK1(21)
239#define M_SYS_BIG_ENDIAN	    _SB_MAKEMASK1(22)
240#define M_SYS_GENCLK_EN		    _SB_MAKEMASK1(23)
241#define M_SYS_LDT_TEST_EN	    _SB_MAKEMASK1(24)
242#define M_SYS_GEN_PARITY_EN	    _SB_MAKEMASK1(25)
243
244#define S_SYS_CONFIG		    26
245#define M_SYS_CONFIG		    _SB_MAKEMASK(6, S_SYS_CONFIG)
246#define V_SYS_CONFIG(x)		    _SB_MAKEVALUE(x, S_SYS_CONFIG)
247#define G_SYS_CONFIG(x)		    _SB_GETVALUE(x, S_SYS_CONFIG, M_SYS_CONFIG)
248
249/* The following bits are writeable by JTAG only. */
250
251#define M_SYS_CLKSTOP		    _SB_MAKEMASK1(32)
252#define M_SYS_CLKSTEP		    _SB_MAKEMASK1(33)
253
254#define S_SYS_CLKCOUNT		    34
255#define M_SYS_CLKCOUNT		    _SB_MAKEMASK(8, S_SYS_CLKCOUNT)
256#define V_SYS_CLKCOUNT(x)	    _SB_MAKEVALUE(x, S_SYS_CLKCOUNT)
257#define G_SYS_CLKCOUNT(x)	    _SB_GETVALUE(x, S_SYS_CLKCOUNT, M_SYS_CLKCOUNT)
258
259#define M_SYS_PLL_BYPASS	    _SB_MAKEMASK1(42)
260
261#define S_SYS_PLL_IREF		    43
262#define M_SYS_PLL_IREF		    _SB_MAKEMASK(2, S_SYS_PLL_IREF)
263
264#define S_SYS_PLL_VCO		    45
265#define M_SYS_PLL_VCO		    _SB_MAKEMASK(2, S_SYS_PLL_VCO)
266
267#define S_SYS_PLL_VREG		    47
268#define M_SYS_PLL_VREG		    _SB_MAKEMASK(2, S_SYS_PLL_VREG)
269
270#define M_SYS_MEM_RESET		    _SB_MAKEMASK1(49)
271#define M_SYS_L2C_RESET		    _SB_MAKEMASK1(50)
272#define M_SYS_IO_RESET_0	    _SB_MAKEMASK1(51)
273#define M_SYS_IO_RESET_1	    _SB_MAKEMASK1(52)
274#define M_SYS_SCD_RESET		    _SB_MAKEMASK1(53)
275
276/* End of bits writable by JTAG only. */
277
278#define M_SYS_CPU_RESET_0	    _SB_MAKEMASK1(54)
279#define M_SYS_CPU_RESET_1	    _SB_MAKEMASK1(55)
280
281#define M_SYS_UNICPU0		    _SB_MAKEMASK1(56)
282#define M_SYS_UNICPU1		    _SB_MAKEMASK1(57)
283
284#define M_SYS_SB_SOFTRES	    _SB_MAKEMASK1(58)
285#define M_SYS_EXT_RESET		    _SB_MAKEMASK1(59)
286#define M_SYS_SYSTEM_RESET	    _SB_MAKEMASK1(60)
287
288#define M_SYS_MISR_MODE		    _SB_MAKEMASK1(61)
289#define M_SYS_MISR_RESET	    _SB_MAKEMASK1(62)
290
291#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
292#define M_SYS_SW_FLAG		    _SB_MAKEMASK1(63)
293#endif /* 1250 PASS2 || 112x PASS1 */
294
295#endif
296
297
298/*
299 * Mailbox Registers (Table 4-3)
300 * Registers: SCD_MBOX_CPU_x
301 */
302
303#define S_MBOX_INT_3		    0
304#define M_MBOX_INT_3		    _SB_MAKEMASK(16, S_MBOX_INT_3)
305#define S_MBOX_INT_2		    16
306#define M_MBOX_INT_2		    _SB_MAKEMASK(16, S_MBOX_INT_2)
307#define S_MBOX_INT_1		    32
308#define M_MBOX_INT_1		    _SB_MAKEMASK(16, S_MBOX_INT_1)
309#define S_MBOX_INT_0		    48
310#define M_MBOX_INT_0		    _SB_MAKEMASK(16, S_MBOX_INT_0)
311
312/*
313 * Watchdog Registers (Table 4-8) (Table 4-9) (Table 4-10)
314 * Registers: SCD_WDOG_INIT_CNT_x
315 */
316
317#define V_SCD_WDOG_FREQ		    1000000
318
319#define S_SCD_WDOG_INIT		    0
320#define M_SCD_WDOG_INIT		    _SB_MAKEMASK(23, S_SCD_WDOG_INIT)
321
322#define S_SCD_WDOG_CNT		    0
323#define M_SCD_WDOG_CNT		    _SB_MAKEMASK(23, S_SCD_WDOG_CNT)
324
325#define S_SCD_WDOG_ENABLE	    0
326#define M_SCD_WDOG_ENABLE	    _SB_MAKEMASK1(S_SCD_WDOG_ENABLE)
327
328#define S_SCD_WDOG_RESET_TYPE	    2
329#define M_SCD_WDOG_RESET_TYPE	    _SB_MAKEMASK(3, S_SCD_WDOG_RESET_TYPE)
330#define V_SCD_WDOG_RESET_TYPE(x)    _SB_MAKEVALUE(x, S_SCD_WDOG_RESET_TYPE)
331#define G_SCD_WDOG_RESET_TYPE(x)    _SB_GETVALUE(x, S_SCD_WDOG_RESET_TYPE, M_SCD_WDOG_RESET_TYPE)
332
333#define K_SCD_WDOG_RESET_FULL	    0	/* actually, (x & 1) == 0  */
334#define K_SCD_WDOG_RESET_SOFT	    1
335#define K_SCD_WDOG_RESET_CPU0	    3
336#define K_SCD_WDOG_RESET_CPU1	    5
337#define K_SCD_WDOG_RESET_BOTH_CPUS  7
338
339/* This feature is present in 1250 C0 and later, but *not* in 112x A revs.  */
340#if SIBYTE_HDR_FEATURE(1250, PASS3)
341#define S_SCD_WDOG_HAS_RESET	    8
342#define M_SCD_WDOG_HAS_RESET	    _SB_MAKEMASK1(S_SCD_WDOG_HAS_RESET)
343#endif
344
345
346/*
347 * Timer Registers (Table 4-11) (Table 4-12) (Table 4-13)
348 */
349
350#define V_SCD_TIMER_FREQ	    1000000
351
352#define S_SCD_TIMER_INIT	    0
353#define M_SCD_TIMER_INIT	    _SB_MAKEMASK(23, S_SCD_TIMER_INIT)
354#define V_SCD_TIMER_INIT(x)	    _SB_MAKEVALUE(x, S_SCD_TIMER_INIT)
355#define G_SCD_TIMER_INIT(x)	    _SB_GETVALUE(x, S_SCD_TIMER_INIT, M_SCD_TIMER_INIT)
356
357#define V_SCD_TIMER_WIDTH	    23
358#define S_SCD_TIMER_CNT		    0
359#define M_SCD_TIMER_CNT		    _SB_MAKEMASK(V_SCD_TIMER_WIDTH, S_SCD_TIMER_CNT)
360#define V_SCD_TIMER_CNT(x)	   _SB_MAKEVALUE(x, S_SCD_TIMER_CNT)
361#define G_SCD_TIMER_CNT(x)	   _SB_GETVALUE(x, S_SCD_TIMER_CNT, M_SCD_TIMER_CNT)
362
363#define M_SCD_TIMER_ENABLE	    _SB_MAKEMASK1(0)
364#define M_SCD_TIMER_MODE	    _SB_MAKEMASK1(1)
365#define M_SCD_TIMER_MODE_CONTINUOUS M_SCD_TIMER_MODE
366
367/*
368 * System Performance Counters
369 */
370
371#define S_SPC_CFG_SRC0		  0
372#define M_SPC_CFG_SRC0		  _SB_MAKEMASK(8, S_SPC_CFG_SRC0)
373#define V_SPC_CFG_SRC0(x)	  _SB_MAKEVALUE(x, S_SPC_CFG_SRC0)
374#define G_SPC_CFG_SRC0(x)	  _SB_GETVALUE(x, S_SPC_CFG_SRC0, M_SPC_CFG_SRC0)
375
376#define S_SPC_CFG_SRC1		  8
377#define M_SPC_CFG_SRC1		  _SB_MAKEMASK(8, S_SPC_CFG_SRC1)
378#define V_SPC_CFG_SRC1(x)	  _SB_MAKEVALUE(x, S_SPC_CFG_SRC1)
379#define G_SPC_CFG_SRC1(x)	  _SB_GETVALUE(x, S_SPC_CFG_SRC1, M_SPC_CFG_SRC1)
380
381#define S_SPC_CFG_SRC2		  16
382#define M_SPC_CFG_SRC2		  _SB_MAKEMASK(8, S_SPC_CFG_SRC2)
383#define V_SPC_CFG_SRC2(x)	  _SB_MAKEVALUE(x, S_SPC_CFG_SRC2)
384#define G_SPC_CFG_SRC2(x)	  _SB_GETVALUE(x, S_SPC_CFG_SRC2, M_SPC_CFG_SRC2)
385
386#define S_SPC_CFG_SRC3		  24
387#define M_SPC_CFG_SRC3		  _SB_MAKEMASK(8, S_SPC_CFG_SRC3)
388#define V_SPC_CFG_SRC3(x)	  _SB_MAKEVALUE(x, S_SPC_CFG_SRC3)
389#define G_SPC_CFG_SRC3(x)	  _SB_GETVALUE(x, S_SPC_CFG_SRC3, M_SPC_CFG_SRC3)
390
391#if SIBYTE_HDR_FEATURE_1250_112x
392#define M_SPC_CFG_CLEAR		_SB_MAKEMASK1(32)
393#define M_SPC_CFG_ENABLE	_SB_MAKEMASK1(33)
394#endif
395
396
397/*
398 * Bus Watcher
399 */
400
401#define S_SCD_BERR_TID		  8
402#define M_SCD_BERR_TID		  _SB_MAKEMASK(10, S_SCD_BERR_TID)
403#define V_SCD_BERR_TID(x)	  _SB_MAKEVALUE(x, S_SCD_BERR_TID)
404#define G_SCD_BERR_TID(x)	  _SB_GETVALUE(x, S_SCD_BERR_TID, M_SCD_BERR_TID)
405
406#define S_SCD_BERR_RID		  18
407#define M_SCD_BERR_RID		  _SB_MAKEMASK(4, S_SCD_BERR_RID)
408#define V_SCD_BERR_RID(x)	  _SB_MAKEVALUE(x, S_SCD_BERR_RID)
409#define G_SCD_BERR_RID(x)	  _SB_GETVALUE(x, S_SCD_BERR_RID, M_SCD_BERR_RID)
410
411#define S_SCD_BERR_DCODE	  22
412#define M_SCD_BERR_DCODE	  _SB_MAKEMASK(3, S_SCD_BERR_DCODE)
413#define V_SCD_BERR_DCODE(x)	  _SB_MAKEVALUE(x, S_SCD_BERR_DCODE)
414#define G_SCD_BERR_DCODE(x)	  _SB_GETVALUE(x, S_SCD_BERR_DCODE, M_SCD_BERR_DCODE)
415
416#define M_SCD_BERR_MULTERRS	  _SB_MAKEMASK1(30)
417
418
419#define S_SCD_L2ECC_CORR_D	  0
420#define M_SCD_L2ECC_CORR_D	  _SB_MAKEMASK(8, S_SCD_L2ECC_CORR_D)
421#define V_SCD_L2ECC_CORR_D(x)	  _SB_MAKEVALUE(x, S_SCD_L2ECC_CORR_D)
422#define G_SCD_L2ECC_CORR_D(x)	  _SB_GETVALUE(x, S_SCD_L2ECC_CORR_D, M_SCD_L2ECC_CORR_D)
423
424#define S_SCD_L2ECC_BAD_D	  8
425#define M_SCD_L2ECC_BAD_D	  _SB_MAKEMASK(8, S_SCD_L2ECC_BAD_D)
426#define V_SCD_L2ECC_BAD_D(x)	  _SB_MAKEVALUE(x, S_SCD_L2ECC_BAD_D)
427#define G_SCD_L2ECC_BAD_D(x)	  _SB_GETVALUE(x, S_SCD_L2ECC_BAD_D, M_SCD_L2ECC_BAD_D)
428
429#define S_SCD_L2ECC_CORR_T	  16
430#define M_SCD_L2ECC_CORR_T	  _SB_MAKEMASK(8, S_SCD_L2ECC_CORR_T)
431#define V_SCD_L2ECC_CORR_T(x)	  _SB_MAKEVALUE(x, S_SCD_L2ECC_CORR_T)
432#define G_SCD_L2ECC_CORR_T(x)	  _SB_GETVALUE(x, S_SCD_L2ECC_CORR_T, M_SCD_L2ECC_CORR_T)
433
434#define S_SCD_L2ECC_BAD_T	  24
435#define M_SCD_L2ECC_BAD_T	  _SB_MAKEMASK(8, S_SCD_L2ECC_BAD_T)
436#define V_SCD_L2ECC_BAD_T(x)	  _SB_MAKEVALUE(x, S_SCD_L2ECC_BAD_T)
437#define G_SCD_L2ECC_BAD_T(x)	  _SB_GETVALUE(x, S_SCD_L2ECC_BAD_T, M_SCD_L2ECC_BAD_T)
438
439#define S_SCD_MEM_ECC_CORR	  0
440#define M_SCD_MEM_ECC_CORR	  _SB_MAKEMASK(8, S_SCD_MEM_ECC_CORR)
441#define V_SCD_MEM_ECC_CORR(x)	  _SB_MAKEVALUE(x, S_SCD_MEM_ECC_CORR)
442#define G_SCD_MEM_ECC_CORR(x)	  _SB_GETVALUE(x, S_SCD_MEM_ECC_CORR, M_SCD_MEM_ECC_CORR)
443
444#define S_SCD_MEM_ECC_BAD	  8
445#define M_SCD_MEM_ECC_BAD	  _SB_MAKEMASK(8, S_SCD_MEM_ECC_BAD)
446#define V_SCD_MEM_ECC_BAD(x)	  _SB_MAKEVALUE(x, S_SCD_MEM_ECC_BAD)
447#define G_SCD_MEM_ECC_BAD(x)	  _SB_GETVALUE(x, S_SCD_MEM_ECC_BAD, M_SCD_MEM_ECC_BAD)
448
449#define S_SCD_MEM_BUSERR	  16
450#define M_SCD_MEM_BUSERR	  _SB_MAKEMASK(8, S_SCD_MEM_BUSERR)
451#define V_SCD_MEM_BUSERR(x)	  _SB_MAKEVALUE(x, S_SCD_MEM_BUSERR)
452#define G_SCD_MEM_BUSERR(x)	  _SB_GETVALUE(x, S_SCD_MEM_BUSERR, M_SCD_MEM_BUSERR)
453
454
455/*
456 * Address Trap Registers
457 */
458
459#if SIBYTE_HDR_FEATURE_1250_112x
460#define M_ATRAP_INDEX		  _SB_MAKEMASK(4, 0)
461#define M_ATRAP_ADDRESS		  _SB_MAKEMASK(40, 0)
462
463#define S_ATRAP_CFG_CNT		   0
464#define M_ATRAP_CFG_CNT		   _SB_MAKEMASK(3, S_ATRAP_CFG_CNT)
465#define V_ATRAP_CFG_CNT(x)	   _SB_MAKEVALUE(x, S_ATRAP_CFG_CNT)
466#define G_ATRAP_CFG_CNT(x)	   _SB_GETVALUE(x, S_ATRAP_CFG_CNT, M_ATRAP_CFG_CNT)
467
468#define M_ATRAP_CFG_WRITE	   _SB_MAKEMASK1(3)
469#define M_ATRAP_CFG_ALL		   _SB_MAKEMASK1(4)
470#define M_ATRAP_CFG_INV		   _SB_MAKEMASK1(5)
471#define M_ATRAP_CFG_USESRC	   _SB_MAKEMASK1(6)
472#define M_ATRAP_CFG_SRCINV	   _SB_MAKEMASK1(7)
473
474#define S_ATRAP_CFG_AGENTID	8
475#define M_ATRAP_CFG_AGENTID	_SB_MAKEMASK(4, S_ATRAP_CFG_AGENTID)
476#define V_ATRAP_CFG_AGENTID(x)	_SB_MAKEVALUE(x, S_ATRAP_CFG_AGENTID)
477#define G_ATRAP_CFG_AGENTID(x)	_SB_GETVALUE(x, S_ATRAP_CFG_AGENTID, M_ATRAP_CFG_AGENTID)
478
479#define K_BUS_AGENT_CPU0	0
480#define K_BUS_AGENT_CPU1	1
481#define K_BUS_AGENT_IOB0	2
482#define K_BUS_AGENT_IOB1	3
483#define K_BUS_AGENT_SCD 4
484#define K_BUS_AGENT_L2C 6
485#define K_BUS_AGENT_MC	7
486
487#define S_ATRAP_CFG_CATTR     12
488#define M_ATRAP_CFG_CATTR     _SB_MAKEMASK(3, S_ATRAP_CFG_CATTR)
489#define V_ATRAP_CFG_CATTR(x)  _SB_MAKEVALUE(x, S_ATRAP_CFG_CATTR)
490#define G_ATRAP_CFG_CATTR(x)  _SB_GETVALUE(x, S_ATRAP_CFG_CATTR, M_ATRAP_CFG_CATTR)
491
492#define K_ATRAP_CFG_CATTR_IGNORE	0
493#define K_ATRAP_CFG_CATTR_UNC		1
494#define K_ATRAP_CFG_CATTR_CACHEABLE	2
495#define K_ATRAP_CFG_CATTR_NONCOH	3
496#define K_ATRAP_CFG_CATTR_COHERENT	4
497#define K_ATRAP_CFG_CATTR_NOTUNC	5
498#define K_ATRAP_CFG_CATTR_NOTNONCOH	6
499#define K_ATRAP_CFG_CATTR_NOTCOHERENT	7
500
501#endif	/* 1250/112x */
502
503/*
504 * Trace Buffer Config register
505 */
506
507#define M_SCD_TRACE_CFG_RESET		_SB_MAKEMASK1(0)
508#define M_SCD_TRACE_CFG_START_READ	_SB_MAKEMASK1(1)
509#define M_SCD_TRACE_CFG_START		_SB_MAKEMASK1(2)
510#define M_SCD_TRACE_CFG_STOP		_SB_MAKEMASK1(3)
511#define M_SCD_TRACE_CFG_FREEZE		_SB_MAKEMASK1(4)
512#define M_SCD_TRACE_CFG_FREEZE_FULL	_SB_MAKEMASK1(5)
513#define M_SCD_TRACE_CFG_DEBUG_FULL	_SB_MAKEMASK1(6)
514#define M_SCD_TRACE_CFG_FULL		_SB_MAKEMASK1(7)
515#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
516#define M_SCD_TRACE_CFG_FORCECNT	_SB_MAKEMASK1(8)
517#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
518
519/*
520 * This field is the same on the 1250/112x and 1480, just located in
521 * a slightly different place in the register.
522 */
523#if SIBYTE_HDR_FEATURE_1250_112x
524#define S_SCD_TRACE_CFG_CUR_ADDR	10
525#else
526#if SIBYTE_HDR_FEATURE_CHIP(1480)
527#define S_SCD_TRACE_CFG_CUR_ADDR	24
528#endif	/* 1480 */
529#endif	/* 1250/112x */
530
531#define M_SCD_TRACE_CFG_CUR_ADDR	_SB_MAKEMASK(8, S_SCD_TRACE_CFG_CUR_ADDR)
532#define V_SCD_TRACE_CFG_CUR_ADDR(x)	_SB_MAKEVALUE(x, S_SCD_TRACE_CFG_CUR_ADDR)
533#define G_SCD_TRACE_CFG_CUR_ADDR(x)	_SB_GETVALUE(x, S_SCD_TRACE_CFG_CUR_ADDR, M_SCD_TRACE_CFG_CUR_ADDR)
534
535/*
536 * Trace Event registers
537 */
538
539#define S_SCD_TREVT_ADDR_MATCH		0
540#define M_SCD_TREVT_ADDR_MATCH		_SB_MAKEMASK(4, S_SCD_TREVT_ADDR_MATCH)
541#define V_SCD_TREVT_ADDR_MATCH(x)	_SB_MAKEVALUE(x, S_SCD_TREVT_ADDR_MATCH)
542#define G_SCD_TREVT_ADDR_MATCH(x)	_SB_GETVALUE(x, S_SCD_TREVT_ADDR_MATCH, M_SCD_TREVT_ADDR_MATCH)
543
544#define M_SCD_TREVT_REQID_MATCH		_SB_MAKEMASK1(4)
545#define M_SCD_TREVT_DATAID_MATCH	_SB_MAKEMASK1(5)
546#define M_SCD_TREVT_RESPID_MATCH	_SB_MAKEMASK1(6)
547#define M_SCD_TREVT_INTERRUPT		_SB_MAKEMASK1(7)
548#define M_SCD_TREVT_DEBUG_PIN		_SB_MAKEMASK1(9)
549#define M_SCD_TREVT_WRITE		_SB_MAKEMASK1(10)
550#define M_SCD_TREVT_READ		_SB_MAKEMASK1(11)
551
552#define S_SCD_TREVT_REQID		12
553#define M_SCD_TREVT_REQID		_SB_MAKEMASK(4, S_SCD_TREVT_REQID)
554#define V_SCD_TREVT_REQID(x)		_SB_MAKEVALUE(x, S_SCD_TREVT_REQID)
555#define G_SCD_TREVT_REQID(x)		_SB_GETVALUE(x, S_SCD_TREVT_REQID, M_SCD_TREVT_REQID)
556
557#define S_SCD_TREVT_RESPID		16
558#define M_SCD_TREVT_RESPID		_SB_MAKEMASK(4, S_SCD_TREVT_RESPID)
559#define V_SCD_TREVT_RESPID(x)		_SB_MAKEVALUE(x, S_SCD_TREVT_RESPID)
560#define G_SCD_TREVT_RESPID(x)		_SB_GETVALUE(x, S_SCD_TREVT_RESPID, M_SCD_TREVT_RESPID)
561
562#define S_SCD_TREVT_DATAID		20
563#define M_SCD_TREVT_DATAID		_SB_MAKEMASK(4, S_SCD_TREVT_DATAID)
564#define V_SCD_TREVT_DATAID(x)		_SB_MAKEVALUE(x, S_SCD_TREVT_DATAID)
565#define G_SCD_TREVT_DATAID(x)		_SB_GETVALUE(x, S_SCD_TREVT_DATAID, M_SCD_TREVT_DATID)
566
567#define S_SCD_TREVT_COUNT		24
568#define M_SCD_TREVT_COUNT		_SB_MAKEMASK(8, S_SCD_TREVT_COUNT)
569#define V_SCD_TREVT_COUNT(x)		_SB_MAKEVALUE(x, S_SCD_TREVT_COUNT)
570#define G_SCD_TREVT_COUNT(x)		_SB_GETVALUE(x, S_SCD_TREVT_COUNT, M_SCD_TREVT_COUNT)
571
572/*
573 * Trace Sequence registers
574 */
575
576#define S_SCD_TRSEQ_EVENT4		0
577#define M_SCD_TRSEQ_EVENT4		_SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT4)
578#define V_SCD_TRSEQ_EVENT4(x)		_SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT4)
579#define G_SCD_TRSEQ_EVENT4(x)		_SB_GETVALUE(x, S_SCD_TRSEQ_EVENT4, M_SCD_TRSEQ_EVENT4)
580
581#define S_SCD_TRSEQ_EVENT3		4
582#define M_SCD_TRSEQ_EVENT3		_SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT3)
583#define V_SCD_TRSEQ_EVENT3(x)		_SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT3)
584#define G_SCD_TRSEQ_EVENT3(x)		_SB_GETVALUE(x, S_SCD_TRSEQ_EVENT3, M_SCD_TRSEQ_EVENT3)
585
586#define S_SCD_TRSEQ_EVENT2		8
587#define M_SCD_TRSEQ_EVENT2		_SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT2)
588#define V_SCD_TRSEQ_EVENT2(x)		_SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT2)
589#define G_SCD_TRSEQ_EVENT2(x)		_SB_GETVALUE(x, S_SCD_TRSEQ_EVENT2, M_SCD_TRSEQ_EVENT2)
590
591#define S_SCD_TRSEQ_EVENT1		12
592#define M_SCD_TRSEQ_EVENT1		_SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT1)
593#define V_SCD_TRSEQ_EVENT1(x)		_SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT1)
594#define G_SCD_TRSEQ_EVENT1(x)		_SB_GETVALUE(x, S_SCD_TRSEQ_EVENT1, M_SCD_TRSEQ_EVENT1)
595
596#define K_SCD_TRSEQ_E0			0
597#define K_SCD_TRSEQ_E1			1
598#define K_SCD_TRSEQ_E2			2
599#define K_SCD_TRSEQ_E3			3
600#define K_SCD_TRSEQ_E0_E1		4
601#define K_SCD_TRSEQ_E1_E2		5
602#define K_SCD_TRSEQ_E2_E3		6
603#define K_SCD_TRSEQ_E0_E1_E2		7
604#define K_SCD_TRSEQ_E0_E1_E2_E3		8
605#define K_SCD_TRSEQ_E0E1		9
606#define K_SCD_TRSEQ_E0E1E2		10
607#define K_SCD_TRSEQ_E0E1E2E3		11
608#define K_SCD_TRSEQ_E0E1_E2		12
609#define K_SCD_TRSEQ_E0E1_E2E3		13
610#define K_SCD_TRSEQ_E0E1_E2_E3		14
611#define K_SCD_TRSEQ_IGNORED		15
612
613#define K_SCD_TRSEQ_TRIGGER_ALL		(V_SCD_TRSEQ_EVENT1(K_SCD_TRSEQ_IGNORED) | \
614					 V_SCD_TRSEQ_EVENT2(K_SCD_TRSEQ_IGNORED) | \
615					 V_SCD_TRSEQ_EVENT3(K_SCD_TRSEQ_IGNORED) | \
616					 V_SCD_TRSEQ_EVENT4(K_SCD_TRSEQ_IGNORED))
617
618#define S_SCD_TRSEQ_FUNCTION		16
619#define M_SCD_TRSEQ_FUNCTION		_SB_MAKEMASK(4, S_SCD_TRSEQ_FUNCTION)
620#define V_SCD_TRSEQ_FUNCTION(x)		_SB_MAKEVALUE(x, S_SCD_TRSEQ_FUNCTION)
621#define G_SCD_TRSEQ_FUNCTION(x)		_SB_GETVALUE(x, S_SCD_TRSEQ_FUNCTION, M_SCD_TRSEQ_FUNCTION)
622
623#define K_SCD_TRSEQ_FUNC_NOP		0
624#define K_SCD_TRSEQ_FUNC_START		1
625#define K_SCD_TRSEQ_FUNC_STOP		2
626#define K_SCD_TRSEQ_FUNC_FREEZE		3
627
628#define V_SCD_TRSEQ_FUNC_NOP		V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_NOP)
629#define V_SCD_TRSEQ_FUNC_START		V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_START)
630#define V_SCD_TRSEQ_FUNC_STOP		V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_STOP)
631#define V_SCD_TRSEQ_FUNC_FREEZE		V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_FREEZE)
632
633#define M_SCD_TRSEQ_ASAMPLE		_SB_MAKEMASK1(18)
634#define M_SCD_TRSEQ_DSAMPLE		_SB_MAKEMASK1(19)
635#define M_SCD_TRSEQ_DEBUGPIN		_SB_MAKEMASK1(20)
636#define M_SCD_TRSEQ_DEBUGCPU		_SB_MAKEMASK1(21)
637#define M_SCD_TRSEQ_CLEARUSE		_SB_MAKEMASK1(22)
638#define M_SCD_TRSEQ_ALLD_A		_SB_MAKEMASK1(23)
639#define M_SCD_TRSEQ_ALL_A		_SB_MAKEMASK1(24)
640
641#endif