/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h

http://github.com/mirrors/linux · C Header · 106 lines · 72 code · 16 blank · 18 comment · 0 complexity · 203bb62d6886a3abf32e452c11d9248d MD5 · raw file 

    

  1. /* SPDX-License-Identifier: GPL-2.0-only */
    2. 

  2. /*
    3. 

  3.  *
    4. 

  4.  *  Copyright (C) 2010 John Crispin <john@phrozen.org>
    5. 

  5.  */
    6. 

  6. 

  7. #ifndef _LTQ_XWAY_H__
    8. 

  8. #define _LTQ_XWAY_H__
    9. 

  9. 

  10. #ifdef CONFIG_SOC_TYPE_XWAY
    11. 

  11. 

  12. #include <lantiq.h>
    13. 

  13. 

  14. /* Chip IDs */
    15. 

  15. #define SOC_ID_DANUBE1		0x129
    16. 

  16. #define SOC_ID_DANUBE2		0x12B
    17. 

  17. #define SOC_ID_TWINPASS		0x12D
    18. 

  18. #define SOC_ID_AMAZON_SE_1	0x152 /* 50601 */
    19. 

  19. #define SOC_ID_AMAZON_SE_2	0x153 /* 50600 */
    20. 

  20. #define SOC_ID_ARX188		0x16C
    21. 

  21. #define SOC_ID_ARX168_1		0x16D
    22. 

  22. #define SOC_ID_ARX168_2		0x16E
    23. 

  23. #define SOC_ID_ARX182		0x16F
    24. 

  24. #define SOC_ID_GRX188		0x170
    25. 

  25. #define SOC_ID_GRX168		0x171
    26. 

  26. 

  27. #define SOC_ID_VRX288		0x1C0 /* v1.1 */
    28. 

  28. #define SOC_ID_VRX282		0x1C1 /* v1.1 */
    29. 

  29. #define SOC_ID_VRX268		0x1C2 /* v1.1 */
    30. 

  30. #define SOC_ID_GRX268		0x1C8 /* v1.1 */
    31. 

  31. #define SOC_ID_GRX288		0x1C9 /* v1.1 */
    32. 

  32. #define SOC_ID_VRX288_2		0x00B /* v1.2 */
    33. 

  33. #define SOC_ID_VRX268_2		0x00C /* v1.2 */
    34. 

  34. #define SOC_ID_GRX288_2		0x00D /* v1.2 */
    35. 

  35. #define SOC_ID_GRX282_2		0x00E /* v1.2 */
    36. 

  36. #define SOC_ID_VRX220		0x000
    37. 

  37. 

  38. #define SOC_ID_ARX362		0x004
    39. 

  39. #define SOC_ID_ARX368		0x005
    40. 

  40. #define SOC_ID_ARX382		0x007
    41. 

  41. #define SOC_ID_ARX388		0x008
    42. 

  42. #define SOC_ID_URX388		0x009
    43. 

  43. #define SOC_ID_GRX383		0x010
    44. 

  44. #define SOC_ID_GRX369		0x011
    45. 

  45. #define SOC_ID_GRX387		0x00F
    46. 

  46. #define SOC_ID_GRX389		0x012
    47. 

  47. 

  48.  /* SoC Types */
    49. 

  49. #define SOC_TYPE_DANUBE		0x01
    50. 

  50. #define SOC_TYPE_TWINPASS	0x02
    51. 

  51. #define SOC_TYPE_AR9		0x03
    52. 

  52. #define SOC_TYPE_VR9		0x04 /* v1.1 */
    53. 

  53. #define SOC_TYPE_VR9_2		0x05 /* v1.2 */
    54. 

  54. #define SOC_TYPE_AMAZON_SE	0x06
    55. 

  55. #define SOC_TYPE_AR10		0x07
    56. 

  56. #define SOC_TYPE_GRX390		0x08
    57. 

  57. #define SOC_TYPE_VRX220		0x09
    58. 

  58. 

  59. /* BOOT_SEL - find what boot media we have */
    60. 

  60. #define BS_EXT_ROM		0x0
    61. 

  61. #define BS_FLASH		0x1
    62. 

  62. #define BS_MII0			0x2
    63. 

  63. #define BS_PCI			0x3
    64. 

  64. #define BS_UART1		0x4
    65. 

  65. #define BS_SPI			0x5
    66. 

  66. #define BS_NAND			0x6
    67. 

  67. #define BS_RMII0		0x7
    68. 

  68. 

  69. /* helpers used to access the cgu */
    70. 

  70. #define ltq_cgu_w32(x, y)	ltq_w32((x), ltq_cgu_membase + (y))
    71. 

  71. #define ltq_cgu_r32(x)		ltq_r32(ltq_cgu_membase + (x))
    72. 

  72. extern __iomem void *ltq_cgu_membase;
    73. 

  73. 

  74. /*
    75. 

  75.  * during early_printk no ioremap is possible
    76. 

  76.  * let's use KSEG1 instead
    77. 

  77.  */
    78. 

  78. #define LTQ_ASC1_BASE_ADDR	0x1E100C00
    79. 

  79. #define LTQ_EARLY_ASC		KSEG1ADDR(LTQ_ASC1_BASE_ADDR)
    80. 

  80. 

  81. /* EBU - external bus unit */
    82. 

  82. #define LTQ_EBU_BUSCON0		0x0060
    83. 

  83. #define LTQ_EBU_PCC_CON		0x0090
    84. 

  84. #define LTQ_EBU_PCC_IEN		0x00A4
    85. 

  85. #define LTQ_EBU_PCC_ISTAT	0x00A0
    86. 

  86. #define LTQ_EBU_BUSCON1		0x0064
    87. 

  87. #define LTQ_EBU_ADDRSEL1	0x0024
    88. 

  88. #define EBU_WRDIS		0x80000000
    89. 

  89. 

  90. /* WDT */
    91. 

  91. #define LTQ_RST_CAUSE_WDTRST	0x20
    92. 

  92. 

  93. /* MPS - multi processor unit (voice) */
    94. 

  94. #define LTQ_MPS_BASE_ADDR	(KSEG1 + 0x1F107000)
    95. 

  95. #define LTQ_MPS_CHIPID		((u32 *)(LTQ_MPS_BASE_ADDR + 0x0344))
    96. 

  96. 

  97. /* allow booting xrx200 phys */
    98. 

  98. int xrx200_gphy_boot(struct device *dev, unsigned int id, dma_addr_t dev_addr);
    99. 

  99. 

  100. /* request a non-gpio and set the PIO config */
    101. 

  101. #define PMU_PPE			 BIT(13)
    102. 

  102. extern void ltq_pmu_enable(unsigned int module);
    103. 

  103. extern void ltq_pmu_disable(unsigned int module);
    104. 

  104. 

  105. #endif /* CONFIG_SOC_TYPE_XWAY */
    106. 

  106. #endif /* _LTQ_XWAY_H__ */
    107.