/arch/mips/mti-malta/malta-setup.c

http://github.com/mirrors/linux · C · 250 lines · 199 code · 28 blank · 23 comment · 31 complexity · 1be75009a0433e098d4fa03c8c82faa0 MD5 · raw file

  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Carsten Langgaard, carstenl@mips.com
  4. * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
  5. * Copyright (C) 2008 Dmitri Vorobiev
  6. */
  7. #include <linux/cpu.h>
  8. #include <linux/init.h>
  9. #include <linux/sched.h>
  10. #include <linux/ioport.h>
  11. #include <linux/irq.h>
  12. #include <linux/of_fdt.h>
  13. #include <linux/pci.h>
  14. #include <linux/screen_info.h>
  15. #include <linux/time.h>
  16. #include <asm/dma-coherence.h>
  17. #include <asm/fw/fw.h>
  18. #include <asm/mach-malta/malta-dtshim.h>
  19. #include <asm/mips-cps.h>
  20. #include <asm/mips-boards/generic.h>
  21. #include <asm/mips-boards/malta.h>
  22. #include <asm/mips-boards/maltaint.h>
  23. #include <asm/dma.h>
  24. #include <asm/prom.h>
  25. #include <asm/traps.h>
  26. #ifdef CONFIG_VT
  27. #include <linux/console.h>
  28. #endif
  29. #define ROCIT_CONFIG_GEN0 0x1f403000
  30. #define ROCIT_CONFIG_GEN0_PCI_IOCU BIT(7)
  31. static struct resource standard_io_resources[] = {
  32. {
  33. .name = "dma1",
  34. .start = 0x00,
  35. .end = 0x1f,
  36. .flags = IORESOURCE_IO | IORESOURCE_BUSY
  37. },
  38. {
  39. .name = "timer",
  40. .start = 0x40,
  41. .end = 0x5f,
  42. .flags = IORESOURCE_IO | IORESOURCE_BUSY
  43. },
  44. {
  45. .name = "keyboard",
  46. .start = 0x60,
  47. .end = 0x6f,
  48. .flags = IORESOURCE_IO | IORESOURCE_BUSY
  49. },
  50. {
  51. .name = "dma page reg",
  52. .start = 0x80,
  53. .end = 0x8f,
  54. .flags = IORESOURCE_IO | IORESOURCE_BUSY
  55. },
  56. {
  57. .name = "dma2",
  58. .start = 0xc0,
  59. .end = 0xdf,
  60. .flags = IORESOURCE_IO | IORESOURCE_BUSY
  61. },
  62. };
  63. const char *get_system_type(void)
  64. {
  65. return "MIPS Malta";
  66. }
  67. #ifdef CONFIG_BLK_DEV_FD
  68. static void __init fd_activate(void)
  69. {
  70. /*
  71. * Activate Floppy Controller in the SMSC FDC37M817 Super I/O
  72. * Controller.
  73. * Done by YAMON 2.00 onwards
  74. */
  75. /* Entering config state. */
  76. SMSC_WRITE(SMSC_CONFIG_ENTER, SMSC_CONFIG_REG);
  77. /* Activate floppy controller. */
  78. SMSC_WRITE(SMSC_CONFIG_DEVNUM, SMSC_CONFIG_REG);
  79. SMSC_WRITE(SMSC_CONFIG_DEVNUM_FLOPPY, SMSC_DATA_REG);
  80. SMSC_WRITE(SMSC_CONFIG_ACTIVATE, SMSC_CONFIG_REG);
  81. SMSC_WRITE(SMSC_CONFIG_ACTIVATE_ENABLE, SMSC_DATA_REG);
  82. /* Exit config state. */
  83. SMSC_WRITE(SMSC_CONFIG_EXIT, SMSC_CONFIG_REG);
  84. }
  85. #endif
  86. static int __init plat_enable_iocoherency(void)
  87. {
  88. int supported = 0;
  89. u32 cfg;
  90. if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) {
  91. if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {
  92. BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN;
  93. pr_info("Enabled Bonito CPU coherency\n");
  94. supported = 1;
  95. }
  96. if (strstr(fw_getcmdline(), "iobcuncached")) {
  97. BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN;
  98. BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
  99. ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
  100. BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
  101. pr_info("Disabled Bonito IOBC coherency\n");
  102. } else {
  103. BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN;
  104. BONITO_PCIMEMBASECFG |=
  105. (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
  106. BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
  107. pr_info("Enabled Bonito IOBC coherency\n");
  108. }
  109. } else if (mips_cps_numiocu(0) != 0) {
  110. /* Nothing special needs to be done to enable coherency */
  111. pr_info("CMP IOCU detected\n");
  112. cfg = __raw_readl((u32 *)CKSEG1ADDR(ROCIT_CONFIG_GEN0));
  113. if (!(cfg & ROCIT_CONFIG_GEN0_PCI_IOCU)) {
  114. pr_crit("IOCU OPERATION DISABLED BY SWITCH - DEFAULTING TO SW IO COHERENCY\n");
  115. return 0;
  116. }
  117. supported = 1;
  118. }
  119. hw_coherentio = supported;
  120. return supported;
  121. }
  122. static void __init plat_setup_iocoherency(void)
  123. {
  124. if (plat_enable_iocoherency()) {
  125. if (coherentio == IO_COHERENCE_DISABLED)
  126. pr_info("Hardware DMA cache coherency disabled\n");
  127. else
  128. pr_info("Hardware DMA cache coherency enabled\n");
  129. } else {
  130. if (coherentio == IO_COHERENCE_ENABLED)
  131. pr_info("Hardware DMA cache coherency unsupported, but enabled from command line!\n");
  132. else
  133. pr_info("Software DMA cache coherency enabled\n");
  134. }
  135. }
  136. static void __init pci_clock_check(void)
  137. {
  138. unsigned int __iomem *jmpr_p =
  139. (unsigned int *) ioremap(MALTA_JMPRS_REG, sizeof(unsigned int));
  140. int jmpr = (__raw_readl(jmpr_p) >> 2) & 0x07;
  141. static const int pciclocks[] __initconst = {
  142. 33, 20, 25, 30, 12, 16, 37, 10
  143. };
  144. int pciclock = pciclocks[jmpr];
  145. char *optptr, *argptr = fw_getcmdline();
  146. /*
  147. * If user passed a pci_clock= option, don't tack on another one
  148. */
  149. optptr = strstr(argptr, "pci_clock=");
  150. if (optptr && (optptr == argptr || optptr[-1] == ' '))
  151. return;
  152. if (pciclock != 33) {
  153. pr_warn("WARNING: PCI clock is %dMHz, setting pci_clock\n",
  154. pciclock);
  155. argptr += strlen(argptr);
  156. sprintf(argptr, " pci_clock=%d", pciclock);
  157. if (pciclock < 20 || pciclock > 66)
  158. pr_warn("WARNING: IDE timing calculations will be "
  159. "incorrect\n");
  160. }
  161. }
  162. #if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
  163. static void __init screen_info_setup(void)
  164. {
  165. screen_info = (struct screen_info) {
  166. .orig_x = 0,
  167. .orig_y = 25,
  168. .ext_mem_k = 0,
  169. .orig_video_page = 0,
  170. .orig_video_mode = 0,
  171. .orig_video_cols = 80,
  172. .unused2 = 0,
  173. .orig_video_ega_bx = 0,
  174. .unused3 = 0,
  175. .orig_video_lines = 25,
  176. .orig_video_isVGA = VIDEO_TYPE_VGAC,
  177. .orig_video_points = 16
  178. };
  179. }
  180. #endif
  181. static void __init bonito_quirks_setup(void)
  182. {
  183. char *argptr;
  184. argptr = fw_getcmdline();
  185. if (strstr(argptr, "debug")) {
  186. BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE;
  187. pr_info("Enabled Bonito debug mode\n");
  188. } else
  189. BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE;
  190. }
  191. void __init *plat_get_fdt(void)
  192. {
  193. return (void *)__dtb_start;
  194. }
  195. void __init plat_mem_setup(void)
  196. {
  197. unsigned int i;
  198. void *fdt = plat_get_fdt();
  199. fdt = malta_dt_shim(fdt);
  200. __dt_setup_arch(fdt);
  201. if (IS_ENABLED(CONFIG_EVA))
  202. /* EVA has already been configured in mach-malta/kernel-init.h */
  203. pr_info("Enhanced Virtual Addressing (EVA) activated\n");
  204. mips_pcibios_init();
  205. /* Request I/O space for devices used on the Malta board. */
  206. for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
  207. request_resource(&ioport_resource, standard_io_resources+i);
  208. /*
  209. * Enable DMA channel 4 (cascade channel) in the PIIX4 south bridge.
  210. */
  211. enable_dma(4);
  212. if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO)
  213. bonito_quirks_setup();
  214. plat_setup_iocoherency();
  215. pci_clock_check();
  216. #ifdef CONFIG_BLK_DEV_FD
  217. fd_activate();
  218. #endif
  219. #if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
  220. screen_info_setup();
  221. #endif
  222. }