PageRenderTime 31ms CodeModel.GetById 15ms app.highlight 12ms RepoModel.GetById 2ms app.codeStats 0ms

/arch/mips/rb532/irq.c

http://github.com/mirrors/linux
C | 234 lines | 164 code | 39 blank | 31 comment | 18 complexity | 5323ec0e8dcb6b226f3e3c4f819ac39a MD5 | raw file
  1/*
  2 *  This program is free software; you can redistribute  it and/or modify it
  3 *  under  the terms of  the GNU General  Public License as published by the
  4 *  Free Software Foundation;  either version 2 of the  License, or (at your
  5 *  option) any later version.
  6 *
  7 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  8 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  9 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 10 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 11 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 12 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 13 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 14 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 15 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 16 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 17 *
 18 *  You should have received a copy of the  GNU General Public License along
 19 *  with this program; if not, write  to the Free Software Foundation, Inc.,
 20 *  675 Mass Ave, Cambridge, MA 02139, USA.
 21 *
 22 * Copyright 2002 MontaVista Software Inc.
 23 * Author: MontaVista Software, Inc.
 24 *		stevel@mvista.com or source@mvista.com
 25 */
 26
 27#include <linux/bitops.h>
 28#include <linux/errno.h>
 29#include <linux/init.h>
 30#include <linux/io.h>
 31#include <linux/kernel_stat.h>
 32#include <linux/signal.h>
 33#include <linux/sched.h>
 34#include <linux/types.h>
 35#include <linux/interrupt.h>
 36#include <linux/ioport.h>
 37#include <linux/timex.h>
 38#include <linux/random.h>
 39#include <linux/delay.h>
 40
 41#include <asm/bootinfo.h>
 42#include <asm/time.h>
 43#include <asm/mipsregs.h>
 44
 45#include <asm/mach-rc32434/irq.h>
 46#include <asm/mach-rc32434/gpio.h>
 47
 48struct intr_group {
 49	u32 mask;	/* mask of valid bits in pending/mask registers */
 50	volatile u32 *base_addr;
 51};
 52
 53#define RC32434_NR_IRQS	 (GROUP4_IRQ_BASE + 32)
 54
 55#if (NR_IRQS < RC32434_NR_IRQS)
 56#error Too little irqs defined. Did you override <asm/irq.h> ?
 57#endif
 58
 59static const struct intr_group intr_group[NUM_INTR_GROUPS] = {
 60	{
 61		.mask	= 0x0000efff,
 62		.base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 0 * IC_GROUP_OFFSET)},
 63	{
 64		.mask	= 0x00001fff,
 65		.base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 1 * IC_GROUP_OFFSET)},
 66	{
 67		.mask	= 0x00000007,
 68		.base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 2 * IC_GROUP_OFFSET)},
 69	{
 70		.mask	= 0x0003ffff,
 71		.base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 3 * IC_GROUP_OFFSET)},
 72	{
 73		.mask	= 0xffffffff,
 74		.base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 4 * IC_GROUP_OFFSET)}
 75};
 76
 77#define READ_PEND(base) (*(base))
 78#define READ_MASK(base) (*(base + 2))
 79#define WRITE_MASK(base, val) (*(base + 2) = (val))
 80
 81static inline int irq_to_group(unsigned int irq_nr)
 82{
 83	return (irq_nr - GROUP0_IRQ_BASE) >> 5;
 84}
 85
 86static inline int group_to_ip(unsigned int group)
 87{
 88	return group + 2;
 89}
 90
 91static inline void enable_local_irq(unsigned int ip)
 92{
 93	int ipnum = 0x100 << ip;
 94
 95	set_c0_status(ipnum);
 96}
 97
 98static inline void disable_local_irq(unsigned int ip)
 99{
100	int ipnum = 0x100 << ip;
101
102	clear_c0_status(ipnum);
103}
104
105static inline void ack_local_irq(unsigned int ip)
106{
107	int ipnum = 0x100 << ip;
108
109	clear_c0_cause(ipnum);
110}
111
112static void rb532_enable_irq(struct irq_data *d)
113{
114	unsigned int group, intr_bit, irq_nr = d->irq;
115	int ip = irq_nr - GROUP0_IRQ_BASE;
116	volatile unsigned int *addr;
117
118	if (ip < 0)
119		enable_local_irq(irq_nr);
120	else {
121		group = ip >> 5;
122
123		ip &= (1 << 5) - 1;
124		intr_bit = 1 << ip;
125
126		enable_local_irq(group_to_ip(group));
127
128		addr = intr_group[group].base_addr;
129		WRITE_MASK(addr, READ_MASK(addr) & ~intr_bit);
130	}
131}
132
133static void rb532_disable_irq(struct irq_data *d)
134{
135	unsigned int group, intr_bit, mask, irq_nr = d->irq;
136	int ip = irq_nr - GROUP0_IRQ_BASE;
137	volatile unsigned int *addr;
138
139	if (ip < 0) {
140		disable_local_irq(irq_nr);
141	} else {
142		group = ip >> 5;
143
144		ip &= (1 << 5) - 1;
145		intr_bit = 1 << ip;
146		addr = intr_group[group].base_addr;
147		mask = READ_MASK(addr);
148		mask |= intr_bit;
149		WRITE_MASK(addr, mask);
150
151		/* There is a maximum of 14 GPIO interrupts */
152		if (group == GPIO_MAPPED_IRQ_GROUP && irq_nr <= (GROUP4_IRQ_BASE + 13))
153			rb532_gpio_set_istat(0, irq_nr - GPIO_MAPPED_IRQ_BASE);
154
155		/*
156		 * if there are no more interrupts enabled in this
157		 * group, disable corresponding IP
158		 */
159		if (mask == intr_group[group].mask)
160			disable_local_irq(group_to_ip(group));
161	}
162}
163
164static void rb532_mask_and_ack_irq(struct irq_data *d)
165{
166	rb532_disable_irq(d);
167	ack_local_irq(group_to_ip(irq_to_group(d->irq)));
168}
169
170static int rb532_set_type(struct irq_data *d,  unsigned type)
171{
172	int gpio = d->irq - GPIO_MAPPED_IRQ_BASE;
173	int group = irq_to_group(d->irq);
174
175	if (group != GPIO_MAPPED_IRQ_GROUP || d->irq > (GROUP4_IRQ_BASE + 13))
176		return (type == IRQ_TYPE_LEVEL_HIGH) ? 0 : -EINVAL;
177
178	switch (type) {
179	case IRQ_TYPE_LEVEL_HIGH:
180		rb532_gpio_set_ilevel(1, gpio);
181		break;
182	case IRQ_TYPE_LEVEL_LOW:
183		rb532_gpio_set_ilevel(0, gpio);
184		break;
185	default:
186		return -EINVAL;
187	}
188
189	return 0;
190}
191
192static struct irq_chip rc32434_irq_type = {
193	.name		= "RB532",
194	.irq_ack	= rb532_disable_irq,
195	.irq_mask	= rb532_disable_irq,
196	.irq_mask_ack	= rb532_mask_and_ack_irq,
197	.irq_unmask	= rb532_enable_irq,
198	.irq_set_type	= rb532_set_type,
199};
200
201void __init arch_init_irq(void)
202{
203	int i;
204
205	pr_info("Initializing IRQ's: %d out of %d\n", RC32434_NR_IRQS, NR_IRQS);
206
207	for (i = 0; i < RC32434_NR_IRQS; i++)
208		irq_set_chip_and_handler(i, &rc32434_irq_type,
209					 handle_level_irq);
210}
211
212/* Main Interrupt dispatcher */
213asmlinkage void plat_irq_dispatch(void)
214{
215	unsigned int ip, pend, group;
216	volatile unsigned int *addr;
217	unsigned int cp0_cause = read_c0_cause() & read_c0_status();
218
219	if (cp0_cause & CAUSEF_IP7) {
220		do_IRQ(7);
221	} else {
222		ip = (cp0_cause & 0x7c00);
223		if (ip) {
224			group = 21 + (fls(ip) - 32);
225
226			addr = intr_group[group].base_addr;
227
228			pend = READ_PEND(addr);
229			pend &= ~READ_MASK(addr);	/* only unmasked interrupts */
230			pend = 39 + (fls(pend) - 32);
231			do_IRQ((group << 5) + pend);
232		}
233	}
234}