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/arch/powerpc/boot/dts/socrates.dts

http://github.com/mirrors/linux
Device Tree | 348 lines | 301 code | 37 blank | 10 comment | 0 complexity | bf852af5835b93de8bb6dff376085909 MD5 | raw file
  1// SPDX-License-Identifier: GPL-2.0-or-later
  2/*
  3 * Device Tree Source for the Socrates board (MPC8544).
  4 *
  5 * Copyright (c) 2008 Emcraft Systems.
  6 * Sergei Poselenov, <sposelenov@emcraft.com>
  7 */
  8
  9/dts-v1/;
 10
 11/ {
 12	model = "abb,socrates";
 13	compatible = "abb,socrates";
 14	#address-cells = <1>;
 15	#size-cells = <1>;
 16
 17	aliases {
 18		ethernet0 = &enet0;
 19		ethernet1 = &enet1;
 20		serial0 = &serial0;
 21		serial1 = &serial1;
 22		pci0 = &pci0;
 23	};
 24
 25	cpus {
 26		#address-cells = <1>;
 27		#size-cells = <0>;
 28
 29		PowerPC,8544@0 {
 30			device_type = "cpu";
 31			reg = <0>;
 32			d-cache-line-size = <32>;
 33			i-cache-line-size = <32>;
 34			d-cache-size = <0x8000>;	// L1, 32K
 35			i-cache-size = <0x8000>;	// L1, 32K
 36			timebase-frequency = <0>;
 37			bus-frequency = <0>;
 38			clock-frequency = <0>;
 39			next-level-cache = <&L2>;
 40		};
 41	};
 42
 43	memory {
 44		device_type = "memory";
 45		reg = <0x00000000 0x00000000>;	// Filled in by U-Boot
 46	};
 47
 48	soc8544@e0000000 {
 49		#address-cells = <1>;
 50		#size-cells = <1>;
 51		device_type = "soc";
 52
 53		ranges = <0x00000000 0xe0000000 0x00100000>;
 54		bus-frequency = <0>;		// Filled in by U-Boot
 55		compatible = "fsl,mpc8544-immr", "simple-bus";
 56
 57		ecm-law@0 {
 58			compatible = "fsl,ecm-law";
 59			reg = <0x0 0x1000>;
 60			fsl,num-laws = <10>;
 61		};
 62
 63		ecm@1000 {
 64			compatible = "fsl,mpc8544-ecm", "fsl,ecm";
 65			reg = <0x1000 0x1000>;
 66			interrupts = <17 2>;
 67			interrupt-parent = <&mpic>;
 68		};
 69
 70		memory-controller@2000 {
 71			compatible = "fsl,mpc8544-memory-controller";
 72			reg = <0x2000 0x1000>;
 73			interrupt-parent = <&mpic>;
 74			interrupts = <18 2>;
 75		};
 76
 77		L2: l2-cache-controller@20000 {
 78			compatible = "fsl,mpc8544-l2-cache-controller";
 79			reg = <0x20000 0x1000>;
 80			cache-line-size = <32>;
 81			cache-size = <0x40000>;	// L2, 256K
 82			interrupt-parent = <&mpic>;
 83			interrupts = <16 2>;
 84		};
 85
 86		i2c@3000 {
 87			#address-cells = <1>;
 88			#size-cells = <0>;
 89			cell-index = <0>;
 90			compatible = "fsl,mpc8544-i2c", "fsl-i2c";
 91			reg = <0x3000 0x100>;
 92			interrupts = <43 2>;
 93			interrupt-parent = <&mpic>;
 94			fsl,preserve-clocking;
 95
 96			dtt@28 {
 97				compatible = "winbond,w83782d";
 98				reg = <0x28>;
 99			};
100			rtc@32 {
101				compatible = "epson,rx8025";
102				reg = <0x32>;
103				interrupts = <7 1>;
104				interrupt-parent = <&mpic>;
105			};
106			dtt@4c {
107				compatible = "dallas,ds75";
108				reg = <0x4c>;
109			};
110			ts@4a {
111				compatible = "ti,tsc2003";
112				reg = <0x4a>;
113				interrupt-parent = <&mpic>;
114				interrupts = <8 1>;
115			};
116		};
117
118		i2c@3100 {
119			#address-cells = <1>;
120			#size-cells = <0>;
121			cell-index = <1>;
122			compatible = "fsl,mpc8544-i2c", "fsl-i2c";
123			reg = <0x3100 0x100>;
124			interrupts = <43 2>;
125			interrupt-parent = <&mpic>;
126			fsl,preserve-clocking;
127		};
128
129		enet0: ethernet@24000 {
130			#address-cells = <1>;
131			#size-cells = <1>;
132			cell-index = <0>;
133			device_type = "network";
134			model = "eTSEC";
135			compatible = "gianfar";
136			reg = <0x24000 0x1000>;
137			ranges = <0x0 0x24000 0x1000>;
138			local-mac-address = [ 00 00 00 00 00 00 ];
139			interrupts = <29 2 30 2 34 2>;
140			interrupt-parent = <&mpic>;
141			phy-handle = <&phy0>;
142			tbi-handle = <&tbi0>;
143			phy-connection-type = "rgmii-id";
144
145			mdio@520 {
146				#address-cells = <1>;
147				#size-cells = <0>;
148				compatible = "fsl,gianfar-mdio";
149				reg = <0x520 0x20>;
150
151				phy0: ethernet-phy@0 {
152					interrupt-parent = <&mpic>;
153					interrupts = <0 1>;
154					reg = <0>;
155				};
156				phy1: ethernet-phy@1 {
157					interrupt-parent = <&mpic>;
158					interrupts = <0 1>;
159					reg = <1>;
160				};
161				tbi0: tbi-phy@11 {
162					reg = <0x11>;
163				};
164			};
165		};
166
167		enet1: ethernet@26000 {
168			#address-cells = <1>;
169			#size-cells = <1>;
170			cell-index = <1>;
171			device_type = "network";
172			model = "eTSEC";
173			compatible = "gianfar";
174			reg = <0x26000 0x1000>;
175			ranges = <0x0 0x26000 0x1000>;
176			local-mac-address = [ 00 00 00 00 00 00 ];
177			interrupts = <31 2 32 2 33 2>;
178			interrupt-parent = <&mpic>;
179			phy-handle = <&phy1>;
180			tbi-handle = <&tbi1>;
181			phy-connection-type = "rgmii-id";
182
183			mdio@520 {
184				#address-cells = <1>;
185				#size-cells = <0>;
186				compatible = "fsl,gianfar-tbi";
187				reg = <0x520 0x20>;
188
189				tbi1: tbi-phy@11 {
190					reg = <0x11>;
191				};
192			};
193		};
194
195		serial0: serial@4500 {
196			cell-index = <0>;
197			device_type = "serial";
198			compatible = "fsl,ns16550", "ns16550";
199			reg = <0x4500 0x100>;
200			clock-frequency = <0>;
201			interrupts = <42 2>;
202			interrupt-parent = <&mpic>;
203		};
204
205		serial1: serial@4600 {
206			cell-index = <1>;
207			device_type = "serial";
208			compatible = "fsl,ns16550", "ns16550";
209			reg = <0x4600 0x100>;
210			clock-frequency = <0>;
211			interrupts = <42 2>;
212			interrupt-parent = <&mpic>;
213		};
214
215		global-utilities@e0000 {	//global utilities block
216			compatible = "fsl,mpc8548-guts";
217			reg = <0xe0000 0x1000>;
218			fsl,has-rstcr;
219		};
220
221		mpic: pic@40000 {
222			interrupt-controller;
223			#address-cells = <0>;
224			#interrupt-cells = <2>;
225			reg = <0x40000 0x40000>;
226			compatible = "chrp,open-pic";
227			device_type = "open-pic";
228		};
229	};
230
231
232	localbus {
233		compatible = "fsl,mpc8544-localbus",
234		             "fsl,pq3-localbus",
235			     "simple-bus";
236		#address-cells = <2>;
237		#size-cells = <1>;
238		reg = <0xe0005000 0x40>;
239		interrupt-parent = <&mpic>;
240		interrupts = <19 2>;
241
242		ranges = <0 0 0xfc000000 0x04000000
243			  2 0 0xc8000000 0x04000000
244			  3 0 0xc0000000 0x00100000
245			>; /* Overwritten by U-Boot */
246
247		nor_flash@0,0 {
248			compatible = "amd,s29gl256n", "cfi-flash";
249			bank-width = <2>;
250			reg = <0x0 0x000000 0x4000000>;
251			#address-cells = <1>;
252			#size-cells = <1>;
253			partition@0 {
254				label = "kernel";
255				reg = <0x0 0x1e0000>;
256				read-only;
257			};
258			partition@1e0000 {
259				label = "dtb";
260				reg = <0x1e0000 0x20000>;
261			};
262			partition@200000 {
263				label = "root";
264				reg = <0x200000 0x200000>;
265			};
266			partition@400000 {
267				label = "user";
268				reg = <0x400000 0x3b80000>;
269			};
270			partition@3f80000 {
271				label = "env";
272				reg = <0x3f80000 0x40000>;
273				read-only;
274			};
275			partition@3fc0000 {
276				label = "u-boot";
277				reg = <0x3fc0000 0x40000>;
278				read-only;
279			};
280		};
281
282		display@2,0 {
283			compatible = "fujitsu,lime";
284			reg = <2 0x0 0x4000000>;
285			interrupt-parent = <&mpic>;
286			interrupts = <6 1>;
287		};
288
289		fpga_pic: fpga-pic@3,10 {
290			compatible = "abb,socrates-fpga-pic";
291			reg = <3 0x10 0x10>;
292			interrupt-controller;
293			/* IRQs 2, 10, 11, active low, level-sensitive */
294			interrupts = <2 1 10 1 11 1>;
295			interrupt-parent = <&mpic>;
296			#interrupt-cells = <3>;
297		};
298
299		spi@3,60 {
300			compatible = "abb,socrates-spi";
301			reg = <3 0x60 0x10>;
302			interrupts = <8 4 0>;	// number, type, routing
303			interrupt-parent = <&fpga_pic>;
304		};
305
306		nand@3,70 {
307			compatible = "abb,socrates-nand";
308			reg = <3 0x70 0x04>;
309			bank-width = <1>;
310			#address-cells = <1>;
311			#size-cells = <1>;
312			data@0 {
313				label = "data";
314				reg = <0x0 0x40000000>;
315			};
316		};
317
318		can@3,100 {
319			compatible = "philips,sja1000";
320			reg = <3 0x100 0x80>;
321			interrupts = <2 8 1>;	// number, type, routing
322			interrupt-parent = <&fpga_pic>;
323		};
324	};
325
326	pci0: pci@e0008000 {
327		#interrupt-cells = <1>;
328		#size-cells = <2>;
329		#address-cells = <3>;
330		compatible = "fsl,mpc8540-pci";
331		device_type = "pci";
332		reg = <0xe0008000 0x1000>;
333		clock-frequency = <66666666>;
334
335		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
336		interrupt-map = <
337				/* IDSEL 0x11 */
338				 0x8800 0x0 0x0 1 &mpic 5 1
339				/* IDSEL 0x12 */
340				 0x9000 0x0 0x0 1 &mpic 4 1>;
341		interrupt-parent = <&mpic>;
342		interrupts = <24 2>;
343		bus-range = <0x0 0x0>;
344		ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
345			  0x01000000 0x0 0x00000000 0xe2000000 0x0 0x01000000>;
346	};
347
348};