/arch/powerpc/boot/dts/virtex440-ml510.dts

http://github.com/mirrors/linux · Device Tree · 466 lines · 387 code · 11 blank · 68 comment · 0 complexity · 519d46a58819bc16c27a0bd4dc4bdf16 MD5 · raw file

  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Xilinx ML510 Reference Design support
  4. *
  5. * This DTS file was created for the ml510_bsb1_pcores_ppc440 reference design.
  6. * The reference design contains a bug which prevent PCI DMA from working
  7. * properly. A description of the bug is given in the plbv46_pci section. It
  8. * needs to be fixed by the user until Xilinx updates their reference design.
  9. *
  10. * Copyright 2009, Roderick Colenbrander
  11. */
  12. /dts-v1/;
  13. / {
  14. #address-cells = <1>;
  15. #size-cells = <1>;
  16. compatible = "xlnx,ml510-ref-design", "xlnx,virtex440";
  17. dcr-parent = <&ppc440_0>;
  18. DDR2_SDRAM_DIMM0: memory@0 {
  19. device_type = "memory";
  20. reg = < 0x0 0x20000000 >;
  21. } ;
  22. alias {
  23. ethernet0 = &Hard_Ethernet_MAC;
  24. serial0 = &RS232_Uart_1;
  25. } ;
  26. chosen {
  27. bootargs = "console=ttyS0 root=/dev/ram";
  28. stdout-path = "/plb@0/serial@83e00000";
  29. } ;
  30. cpus {
  31. #address-cells = <1>;
  32. #cpus = <0x1>;
  33. #size-cells = <0>;
  34. ppc440_0: cpu@0 {
  35. #address-cells = <1>;
  36. #size-cells = <1>;
  37. clock-frequency = <300000000>;
  38. compatible = "PowerPC,440", "ibm,ppc440";
  39. d-cache-line-size = <0x20>;
  40. d-cache-size = <0x8000>;
  41. dcr-access-method = "native";
  42. dcr-controller ;
  43. device_type = "cpu";
  44. i-cache-line-size = <0x20>;
  45. i-cache-size = <0x8000>;
  46. model = "PowerPC,440";
  47. reg = <0>;
  48. timebase-frequency = <300000000>;
  49. xlnx,apu-control = <0x2000>;
  50. xlnx,apu-udi-0 = <0x0>;
  51. xlnx,apu-udi-1 = <0x0>;
  52. xlnx,apu-udi-10 = <0x0>;
  53. xlnx,apu-udi-11 = <0x0>;
  54. xlnx,apu-udi-12 = <0x0>;
  55. xlnx,apu-udi-13 = <0x0>;
  56. xlnx,apu-udi-14 = <0x0>;
  57. xlnx,apu-udi-15 = <0x0>;
  58. xlnx,apu-udi-2 = <0x0>;
  59. xlnx,apu-udi-3 = <0x0>;
  60. xlnx,apu-udi-4 = <0x0>;
  61. xlnx,apu-udi-5 = <0x0>;
  62. xlnx,apu-udi-6 = <0x0>;
  63. xlnx,apu-udi-7 = <0x0>;
  64. xlnx,apu-udi-8 = <0x0>;
  65. xlnx,apu-udi-9 = <0x0>;
  66. xlnx,dcr-autolock-enable = <0x1>;
  67. xlnx,dcu-rd-ld-cache-plb-prio = <0x0>;
  68. xlnx,dcu-rd-noncache-plb-prio = <0x0>;
  69. xlnx,dcu-rd-touch-plb-prio = <0x0>;
  70. xlnx,dcu-rd-urgent-plb-prio = <0x0>;
  71. xlnx,dcu-wr-flush-plb-prio = <0x0>;
  72. xlnx,dcu-wr-store-plb-prio = <0x0>;
  73. xlnx,dcu-wr-urgent-plb-prio = <0x0>;
  74. xlnx,dma0-control = <0x0>;
  75. xlnx,dma0-plb-prio = <0x0>;
  76. xlnx,dma0-rxchannelctrl = <0x1010000>;
  77. xlnx,dma0-rxirqtimer = <0x3ff>;
  78. xlnx,dma0-txchannelctrl = <0x1010000>;
  79. xlnx,dma0-txirqtimer = <0x3ff>;
  80. xlnx,dma1-control = <0x0>;
  81. xlnx,dma1-plb-prio = <0x0>;
  82. xlnx,dma1-rxchannelctrl = <0x1010000>;
  83. xlnx,dma1-rxirqtimer = <0x3ff>;
  84. xlnx,dma1-txchannelctrl = <0x1010000>;
  85. xlnx,dma1-txirqtimer = <0x3ff>;
  86. xlnx,dma2-control = <0x0>;
  87. xlnx,dma2-plb-prio = <0x0>;
  88. xlnx,dma2-rxchannelctrl = <0x1010000>;
  89. xlnx,dma2-rxirqtimer = <0x3ff>;
  90. xlnx,dma2-txchannelctrl = <0x1010000>;
  91. xlnx,dma2-txirqtimer = <0x3ff>;
  92. xlnx,dma3-control = <0x0>;
  93. xlnx,dma3-plb-prio = <0x0>;
  94. xlnx,dma3-rxchannelctrl = <0x1010000>;
  95. xlnx,dma3-rxirqtimer = <0x3ff>;
  96. xlnx,dma3-txchannelctrl = <0x1010000>;
  97. xlnx,dma3-txirqtimer = <0x3ff>;
  98. xlnx,endian-reset = <0x0>;
  99. xlnx,generate-plb-timespecs = <0x1>;
  100. xlnx,icu-rd-fetch-plb-prio = <0x0>;
  101. xlnx,icu-rd-spec-plb-prio = <0x0>;
  102. xlnx,icu-rd-touch-plb-prio = <0x0>;
  103. xlnx,interconnect-imask = <0xffffffff>;
  104. xlnx,mplb-allow-lock-xfer = <0x1>;
  105. xlnx,mplb-arb-mode = <0x0>;
  106. xlnx,mplb-awidth = <0x20>;
  107. xlnx,mplb-counter = <0x500>;
  108. xlnx,mplb-dwidth = <0x80>;
  109. xlnx,mplb-max-burst = <0x8>;
  110. xlnx,mplb-native-dwidth = <0x80>;
  111. xlnx,mplb-p2p = <0x0>;
  112. xlnx,mplb-prio-dcur = <0x2>;
  113. xlnx,mplb-prio-dcuw = <0x3>;
  114. xlnx,mplb-prio-icu = <0x4>;
  115. xlnx,mplb-prio-splb0 = <0x1>;
  116. xlnx,mplb-prio-splb1 = <0x0>;
  117. xlnx,mplb-read-pipe-enable = <0x1>;
  118. xlnx,mplb-sync-tattribute = <0x0>;
  119. xlnx,mplb-wdog-enable = <0x1>;
  120. xlnx,mplb-write-pipe-enable = <0x1>;
  121. xlnx,mplb-write-post-enable = <0x1>;
  122. xlnx,num-dma = <0x0>;
  123. xlnx,pir = <0xf>;
  124. xlnx,ppc440mc-addr-base = <0x0>;
  125. xlnx,ppc440mc-addr-high = <0x1fffffff>;
  126. xlnx,ppc440mc-arb-mode = <0x0>;
  127. xlnx,ppc440mc-bank-conflict-mask = <0x1800000>;
  128. xlnx,ppc440mc-control = <0xf810008f>;
  129. xlnx,ppc440mc-max-burst = <0x8>;
  130. xlnx,ppc440mc-prio-dcur = <0x2>;
  131. xlnx,ppc440mc-prio-dcuw = <0x3>;
  132. xlnx,ppc440mc-prio-icu = <0x4>;
  133. xlnx,ppc440mc-prio-splb0 = <0x1>;
  134. xlnx,ppc440mc-prio-splb1 = <0x0>;
  135. xlnx,ppc440mc-row-conflict-mask = <0x7ffe00>;
  136. xlnx,ppcdm-asyncmode = <0x0>;
  137. xlnx,ppcds-asyncmode = <0x0>;
  138. xlnx,user-reset = <0x0>;
  139. } ;
  140. } ;
  141. plb_v46_0: plb@0 {
  142. #address-cells = <1>;
  143. #size-cells = <1>;
  144. compatible = "xlnx,plb-v46-1.03.a", "simple-bus";
  145. ranges ;
  146. FLASH: flash@fc000000 {
  147. bank-width = <2>;
  148. compatible = "xlnx,xps-mch-emc-2.00.a", "cfi-flash";
  149. reg = < 0xfc000000 0x2000000 >;
  150. xlnx,family = "virtex5";
  151. xlnx,include-datawidth-matching-0 = <0x1>;
  152. xlnx,include-datawidth-matching-1 = <0x0>;
  153. xlnx,include-datawidth-matching-2 = <0x0>;
  154. xlnx,include-datawidth-matching-3 = <0x0>;
  155. xlnx,include-negedge-ioregs = <0x0>;
  156. xlnx,include-plb-ipif = <0x1>;
  157. xlnx,include-wrbuf = <0x1>;
  158. xlnx,max-mem-width = <0x10>;
  159. xlnx,mch-native-dwidth = <0x20>;
  160. xlnx,mch-plb-clk-period-ps = <0x2710>;
  161. xlnx,mch-splb-awidth = <0x20>;
  162. xlnx,mch0-accessbuf-depth = <0x10>;
  163. xlnx,mch0-protocol = <0x0>;
  164. xlnx,mch0-rddatabuf-depth = <0x10>;
  165. xlnx,mch1-accessbuf-depth = <0x10>;
  166. xlnx,mch1-protocol = <0x0>;
  167. xlnx,mch1-rddatabuf-depth = <0x10>;
  168. xlnx,mch2-accessbuf-depth = <0x10>;
  169. xlnx,mch2-protocol = <0x0>;
  170. xlnx,mch2-rddatabuf-depth = <0x10>;
  171. xlnx,mch3-accessbuf-depth = <0x10>;
  172. xlnx,mch3-protocol = <0x0>;
  173. xlnx,mch3-rddatabuf-depth = <0x10>;
  174. xlnx,mem0-width = <0x10>;
  175. xlnx,mem1-width = <0x20>;
  176. xlnx,mem2-width = <0x20>;
  177. xlnx,mem3-width = <0x20>;
  178. xlnx,num-banks-mem = <0x1>;
  179. xlnx,num-channels = <0x2>;
  180. xlnx,priority-mode = <0x0>;
  181. xlnx,synch-mem-0 = <0x0>;
  182. xlnx,synch-mem-1 = <0x0>;
  183. xlnx,synch-mem-2 = <0x0>;
  184. xlnx,synch-mem-3 = <0x0>;
  185. xlnx,synch-pipedelay-0 = <0x2>;
  186. xlnx,synch-pipedelay-1 = <0x2>;
  187. xlnx,synch-pipedelay-2 = <0x2>;
  188. xlnx,synch-pipedelay-3 = <0x2>;
  189. xlnx,tavdv-ps-mem-0 = <0x1adb0>;
  190. xlnx,tavdv-ps-mem-1 = <0x3a98>;
  191. xlnx,tavdv-ps-mem-2 = <0x3a98>;
  192. xlnx,tavdv-ps-mem-3 = <0x3a98>;
  193. xlnx,tcedv-ps-mem-0 = <0x1adb0>;
  194. xlnx,tcedv-ps-mem-1 = <0x3a98>;
  195. xlnx,tcedv-ps-mem-2 = <0x3a98>;
  196. xlnx,tcedv-ps-mem-3 = <0x3a98>;
  197. xlnx,thzce-ps-mem-0 = <0x88b8>;
  198. xlnx,thzce-ps-mem-1 = <0x1b58>;
  199. xlnx,thzce-ps-mem-2 = <0x1b58>;
  200. xlnx,thzce-ps-mem-3 = <0x1b58>;
  201. xlnx,thzoe-ps-mem-0 = <0x1b58>;
  202. xlnx,thzoe-ps-mem-1 = <0x1b58>;
  203. xlnx,thzoe-ps-mem-2 = <0x1b58>;
  204. xlnx,thzoe-ps-mem-3 = <0x1b58>;
  205. xlnx,tlzwe-ps-mem-0 = <0x88b8>;
  206. xlnx,tlzwe-ps-mem-1 = <0x0>;
  207. xlnx,tlzwe-ps-mem-2 = <0x0>;
  208. xlnx,tlzwe-ps-mem-3 = <0x0>;
  209. xlnx,twc-ps-mem-0 = <0x1adb0>;
  210. xlnx,twc-ps-mem-1 = <0x3a98>;
  211. xlnx,twc-ps-mem-2 = <0x3a98>;
  212. xlnx,twc-ps-mem-3 = <0x3a98>;
  213. xlnx,twp-ps-mem-0 = <0x11170>;
  214. xlnx,twp-ps-mem-1 = <0x2ee0>;
  215. xlnx,twp-ps-mem-2 = <0x2ee0>;
  216. xlnx,twp-ps-mem-3 = <0x2ee0>;
  217. xlnx,xcl0-linesize = <0x4>;
  218. xlnx,xcl0-writexfer = <0x1>;
  219. xlnx,xcl1-linesize = <0x4>;
  220. xlnx,xcl1-writexfer = <0x1>;
  221. xlnx,xcl2-linesize = <0x4>;
  222. xlnx,xcl2-writexfer = <0x1>;
  223. xlnx,xcl3-linesize = <0x4>;
  224. xlnx,xcl3-writexfer = <0x1>;
  225. } ;
  226. Hard_Ethernet_MAC: xps-ll-temac@81c00000 {
  227. #address-cells = <1>;
  228. #size-cells = <1>;
  229. compatible = "xlnx,compound";
  230. ethernet@81c00000 {
  231. compatible = "xlnx,xps-ll-temac-1.01.b";
  232. device_type = "network";
  233. interrupt-parent = <&xps_intc_0>;
  234. interrupts = < 8 2 >;
  235. llink-connected = <&Hard_Ethernet_MAC_fifo>;
  236. local-mac-address = [ 02 00 00 00 00 00 ];
  237. reg = < 0x81c00000 0x40 >;
  238. xlnx,bus2core-clk-ratio = <0x1>;
  239. xlnx,phy-type = <0x3>;
  240. xlnx,phyaddr = <0x1>;
  241. xlnx,rxcsum = <0x0>;
  242. xlnx,rxfifo = <0x8000>;
  243. xlnx,temac-type = <0x0>;
  244. xlnx,txcsum = <0x0>;
  245. xlnx,txfifo = <0x8000>;
  246. } ;
  247. } ;
  248. Hard_Ethernet_MAC_fifo: xps-ll-fifo@81a00000 {
  249. compatible = "xlnx,xps-ll-fifo-1.01.a";
  250. interrupt-parent = <&xps_intc_0>;
  251. interrupts = < 6 2 >;
  252. reg = < 0x81a00000 0x10000 >;
  253. xlnx,family = "virtex5";
  254. } ;
  255. IIC_EEPROM: i2c@81600000 {
  256. compatible = "xlnx,xps-iic-2.00.a";
  257. interrupt-parent = <&xps_intc_0>;
  258. interrupts = < 9 2 >;
  259. reg = < 0x81600000 0x10000 >;
  260. xlnx,clk-freq = <0x5f5e100>;
  261. xlnx,family = "virtex5";
  262. xlnx,gpo-width = <0x1>;
  263. xlnx,iic-freq = <0x186a0>;
  264. xlnx,scl-inertial-delay = <0x5>;
  265. xlnx,sda-inertial-delay = <0x5>;
  266. xlnx,ten-bit-adr = <0x0>;
  267. } ;
  268. LCD_OPTIONAL: gpio@81420000 {
  269. compatible = "xlnx,xps-gpio-1.00.a";
  270. reg = < 0x81420000 0x10000 >;
  271. xlnx,all-inputs = <0x0>;
  272. xlnx,all-inputs-2 = <0x0>;
  273. xlnx,dout-default = <0x0>;
  274. xlnx,dout-default-2 = <0x0>;
  275. xlnx,family = "virtex5";
  276. xlnx,gpio-width = <0xb>;
  277. xlnx,interrupt-present = <0x0>;
  278. xlnx,is-bidir = <0x1>;
  279. xlnx,is-bidir-2 = <0x1>;
  280. xlnx,is-dual = <0x0>;
  281. xlnx,tri-default = <0xffffffff>;
  282. xlnx,tri-default-2 = <0xffffffff>;
  283. } ;
  284. LEDs_4Bit: gpio@81400000 {
  285. compatible = "xlnx,xps-gpio-1.00.a";
  286. reg = < 0x81400000 0x10000 >;
  287. xlnx,all-inputs = <0x0>;
  288. xlnx,all-inputs-2 = <0x0>;
  289. xlnx,dout-default = <0x0>;
  290. xlnx,dout-default-2 = <0x0>;
  291. xlnx,family = "virtex5";
  292. xlnx,gpio-width = <0x4>;
  293. xlnx,interrupt-present = <0x0>;
  294. xlnx,is-bidir = <0x1>;
  295. xlnx,is-bidir-2 = <0x1>;
  296. xlnx,is-dual = <0x0>;
  297. xlnx,tri-default = <0xffffffff>;
  298. xlnx,tri-default-2 = <0xffffffff>;
  299. } ;
  300. RS232_Uart_1: serial@83e00000 {
  301. clock-frequency = <100000000>;
  302. compatible = "xlnx,xps-uart16550-2.00.b", "ns16550";
  303. current-speed = <9600>;
  304. device_type = "serial";
  305. interrupt-parent = <&xps_intc_0>;
  306. interrupts = < 11 2 >;
  307. reg = < 0x83e00000 0x10000 >;
  308. reg-offset = <0x1003>;
  309. reg-shift = <2>;
  310. xlnx,family = "virtex5";
  311. xlnx,has-external-rclk = <0x0>;
  312. xlnx,has-external-xin = <0x0>;
  313. xlnx,is-a-16550 = <0x1>;
  314. } ;
  315. SPI_EEPROM: xps-spi@feff8000 {
  316. compatible = "xlnx,xps-spi-2.00.b";
  317. interrupt-parent = <&xps_intc_0>;
  318. interrupts = < 10 2 >;
  319. reg = < 0xfeff8000 0x80 >;
  320. xlnx,family = "virtex5";
  321. xlnx,fifo-exist = <0x1>;
  322. xlnx,num-ss-bits = <0x1>;
  323. xlnx,num-transfer-bits = <0x8>;
  324. xlnx,sck-ratio = <0x80>;
  325. } ;
  326. SysACE_CompactFlash: sysace@83600000 {
  327. compatible = "xlnx,xps-sysace-1.00.a";
  328. interrupt-parent = <&xps_intc_0>;
  329. interrupts = < 7 2 >;
  330. reg = < 0x83600000 0x10000 >;
  331. xlnx,family = "virtex5";
  332. xlnx,mem-width = <0x10>;
  333. } ;
  334. plbv46_pci_0: plbv46-pci@85e00000 {
  335. #size-cells = <2>;
  336. #address-cells = <3>;
  337. compatible = "xlnx,plbv46-pci-1.03.a";
  338. device_type = "pci";
  339. reg = < 0x85e00000 0x10000 >;
  340. /*
  341. * The default ML510 BSB has C_IPIFBAR2PCIBAR_0 set to
  342. * 0 which means that a read/write to the memory mapped
  343. * i/o region (which starts at 0xa0000000) for pci
  344. * bar 0 on the plb side translates to 0.
  345. * It is important to set this value to 0xa0000000, so
  346. * that inbound and outbound pci transactions work
  347. * properly including DMA.
  348. */
  349. ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x20000000
  350. 0x01000000 0 0x00000000 0xf0000000 0 0x00010000>;
  351. #interrupt-cells = <1>;
  352. interrupt-parent = <&xps_intc_0>;
  353. interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
  354. interrupt-map = <
  355. /* IRQ mapping for pci slots and ALI M1533
  356. * periperhals. In total there are 5 interrupt
  357. * lines connected to a xps_intc controller.
  358. * Four of them are PCI IRQ A, B, C, D and
  359. * which correspond to respectively xpx_intc
  360. * 5, 4, 3 and 2. The fifth interrupt line is
  361. * connected to the south bridge and this one
  362. * uses irq 1 and is active high instead of
  363. * active low.
  364. *
  365. * The M1533 contains various peripherals
  366. * including AC97 audio, a modem, USB, IDE and
  367. * some power management stuff. The modem
  368. * isn't connected on the ML510 and the power
  369. * management core also isn't used.
  370. */
  371. /* IDSEL 0x16 / dev=6, bus=0 / PCI slot 3 */
  372. 0x3000 0 0 1 &xps_intc_0 3 2
  373. 0x3000 0 0 2 &xps_intc_0 2 2
  374. 0x3000 0 0 3 &xps_intc_0 5 2
  375. 0x3000 0 0 4 &xps_intc_0 4 2
  376. /* IDSEL 0x13 / dev=3, bus=1 / PCI slot 4 */
  377. /*
  378. 0x11800 0 0 1 &xps_intc_0 5 0 2
  379. 0x11800 0 0 2 &xps_intc_0 4 0 2
  380. 0x11800 0 0 3 &xps_intc_0 3 0 2
  381. 0x11800 0 0 4 &xps_intc_0 2 0 2
  382. */
  383. /* According to the datasheet + schematic
  384. * ABCD [FPGA] of slot 5 is mapped to DABC.
  385. * Testing showed that at least A maps to B,
  386. * the mapping of the other pins is a guess
  387. * and for that reason the lines have been
  388. * commented out.
  389. */
  390. /* IDSEL 0x15 / dev=5, bus=0 / PCI slot 5 */
  391. 0x2800 0 0 1 &xps_intc_0 4 2
  392. /*
  393. 0x2800 0 0 2 &xps_intc_0 3 2
  394. 0x2800 0 0 3 &xps_intc_0 2 2
  395. 0x2800 0 0 4 &xps_intc_0 5 2
  396. */
  397. /* IDSEL 0x12 / dev=2, bus=1 / PCI slot 6 */
  398. /*
  399. 0x11000 0 0 1 &xps_intc_0 4 0 2
  400. 0x11000 0 0 2 &xps_intc_0 3 0 2
  401. 0x11000 0 0 3 &xps_intc_0 2 0 2
  402. 0x11000 0 0 4 &xps_intc_0 5 0 2
  403. */
  404. /* IDSEL 0x11 / dev=1, bus=0 / AC97 audio */
  405. 0x0800 0 0 1 &i8259 7 2
  406. /* IDSEL 0x1b / dev=11, bus=0 / IDE */
  407. 0x5800 0 0 1 &i8259 14 2
  408. /* IDSEL 0x1f / dev 15, bus=0 / 2x USB 1.1 */
  409. 0x7800 0 0 1 &i8259 7 2
  410. >;
  411. ali_m1533 {
  412. #size-cells = <1>;
  413. #address-cells = <2>;
  414. i8259: interrupt-controller@20 {
  415. reg = <1 0x20 2
  416. 1 0xa0 2
  417. 1 0x4d0 2>;
  418. interrupt-controller;
  419. device_type = "interrupt-controller";
  420. #address-cells = <0>;
  421. #interrupt-cells = <2>;
  422. compatible = "chrp,iic";
  423. /* south bridge irq is active high */
  424. interrupts = <1 3>;
  425. interrupt-parent = <&xps_intc_0>;
  426. };
  427. };
  428. } ;
  429. xps_bram_if_cntlr_1: xps-bram-if-cntlr@ffff0000 {
  430. compatible = "xlnx,xps-bram-if-cntlr-1.00.a";
  431. reg = < 0xffff0000 0x10000 >;
  432. xlnx,family = "virtex5";
  433. } ;
  434. xps_intc_0: interrupt-controller@81800000 {
  435. #interrupt-cells = <0x2>;
  436. compatible = "xlnx,xps-intc-1.00.a";
  437. interrupt-controller ;
  438. reg = < 0x81800000 0x10000 >;
  439. xlnx,num-intr-inputs = <0xc>;
  440. } ;
  441. xps_tft_0: tft@86e00000 {
  442. compatible = "xlnx,xps-tft-1.00.a";
  443. reg = < 0x86e00000 0x10000 >;
  444. xlnx,dcr-splb-slave-if = <0x1>;
  445. xlnx,default-tft-base-addr = <0x0>;
  446. xlnx,family = "virtex5";
  447. xlnx,i2c-slave-addr = <0x76>;
  448. xlnx,mplb-awidth = <0x20>;
  449. xlnx,mplb-dwidth = <0x80>;
  450. xlnx,mplb-native-dwidth = <0x40>;
  451. xlnx,mplb-smallest-slave = <0x20>;
  452. xlnx,tft-interface = <0x1>;
  453. } ;
  454. } ;
  455. } ;