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/arch/powerpc/boot/dts/mpc8568mds.dts

http://github.com/mirrors/linux
Device Tree | 322 lines | 269 code | 36 blank | 17 comment | 0 complexity | 83eb24cdb2c0b8163b6d82bcbc5db49c MD5 | raw file
  1/*
  2 * MPC8568E MDS Device Tree Source
  3 *
  4 * Copyright 2007, 2008 Freescale Semiconductor Inc.
  5 *
  6 * This program is free software; you can redistribute  it and/or modify it
  7 * under  the terms of  the GNU General  Public License as published by the
  8 * Free Software Foundation;  either version 2 of the  License, or (at your
  9 * option) any later version.
 10 */
 11
 12/include/ "fsl/mpc8568si-pre.dtsi"
 13
 14/ {
 15	model = "MPC8568EMDS";
 16	compatible = "MPC8568EMDS", "MPC85xxMDS";
 17
 18	aliases {
 19		pci0 = &pci0;
 20		pci1 = &pci1;
 21		rapidio0 = &rio;
 22	};
 23
 24	memory {
 25		device_type = "memory";
 26		reg = <0x0 0x0 0x0 0x0>;
 27	};
 28
 29	lbc: localbus@e0005000 {
 30		reg = <0x0 0xe0005000 0x0 0x1000>;
 31		ranges = <0x0 0x0 0xfe000000 0x02000000
 32			  0x1 0x0 0xf8000000 0x00008000
 33			  0x2 0x0 0xf0000000 0x04000000
 34			  0x4 0x0 0xf8008000 0x00008000
 35			  0x5 0x0 0xf8010000 0x00008000>;
 36
 37		nor@0,0 {
 38			#address-cells = <1>;
 39			#size-cells = <1>;
 40			compatible = "cfi-flash";
 41			reg = <0x0 0x0 0x02000000>;
 42			bank-width = <2>;
 43			device-width = <2>;
 44		};
 45
 46		bcsr@1,0 {
 47			#address-cells = <1>;
 48			#size-cells = <1>;
 49			compatible = "fsl,mpc8568mds-bcsr";
 50			reg = <1 0 0x8000>;
 51			ranges = <0 1 0 0x8000>;
 52
 53			bcsr5: gpio-controller@11 {
 54				#gpio-cells = <2>;
 55				compatible = "fsl,mpc8568mds-bcsr-gpio";
 56				reg = <0x5 0x1>;
 57				gpio-controller;
 58			};
 59		};
 60
 61		pib@4,0 {
 62			compatible = "fsl,mpc8568mds-pib";
 63			reg = <4 0 0x8000>;
 64		};
 65
 66		pib@5,0 {
 67			compatible = "fsl,mpc8568mds-pib";
 68			reg = <5 0 0x8000>;
 69		};
 70	};
 71
 72	soc: soc8568@e0000000 {
 73		ranges = <0x0 0x0 0xe0000000 0x100000>;
 74
 75		i2c-sleep-nexus {
 76			i2c@3000 {
 77				rtc@68 {
 78					compatible = "dallas,ds1374";
 79					reg = <0x68>;
 80					interrupts = <3 1 0 0>;
 81				};
 82			};
 83		};
 84
 85		enet0: ethernet@24000 {
 86			tbi-handle = <&tbi0>;
 87			phy-handle = <&phy2>;
 88		};
 89
 90		mdio@24520 {
 91			phy0: ethernet-phy@7 {
 92				interrupts = <1 1 0 0>;
 93				reg = <0x7>;
 94				device_type = "ethernet-phy";
 95			};
 96			phy1: ethernet-phy@1 {
 97				interrupts = <2 1 0 0>;
 98				reg = <0x1>;
 99				device_type = "ethernet-phy";
100			};
101			phy2: ethernet-phy@2 {
102				interrupts = <1 1 0 0>;
103				reg = <0x2>;
104				device_type = "ethernet-phy";
105			};
106			phy3: ethernet-phy@3 {
107				interrupts = <2 1 0 0>;
108				reg = <0x3>;
109				device_type = "ethernet-phy";
110			};
111			tbi0: tbi-phy@11 {
112				reg = <0x11>;
113				device_type = "tbi-phy";
114			};
115		};
116
117		enet1: ethernet@25000 {
118			tbi-handle = <&tbi1>;
119			phy-handle = <&phy3>;
120			sleep = <&pmc 0x00000040>;
121		};
122
123		mdio@25520 {
124			tbi1: tbi-phy@11 {
125				reg = <0x11>;
126				device_type = "tbi-phy";
127			};
128		};
129
130		par_io@e0100 {
131			num-ports = <7>;
132
133			pio1: ucc_pin@01 {
134				pio-map = <
135			/* port  pin  dir  open_drain  assignment  has_irq */
136					0x4  0xa  0x1  0x0  0x2  0x0 	/* TxD0 */
137					0x4  0x9  0x1  0x0  0x2  0x0 	/* TxD1 */
138					0x4  0x8  0x1  0x0  0x2  0x0 	/* TxD2 */
139					0x4  0x7  0x1  0x0  0x2  0x0 	/* TxD3 */
140					0x4  0x17  0x1  0x0  0x2  0x0 	/* TxD4 */
141					0x4  0x16  0x1  0x0  0x2  0x0 	/* TxD5 */
142					0x4  0x15  0x1  0x0  0x2  0x0 	/* TxD6 */
143					0x4  0x14  0x1  0x0  0x2  0x0 	/* TxD7 */
144					0x4  0xf  0x2  0x0  0x2  0x0 	/* RxD0 */
145					0x4  0xe  0x2  0x0  0x2  0x0 	/* RxD1 */
146					0x4  0xd  0x2  0x0  0x2  0x0 	/* RxD2 */
147					0x4  0xc  0x2  0x0  0x2  0x0 	/* RxD3 */
148					0x4  0x1d  0x2  0x0  0x2  0x0 	/* RxD4 */
149					0x4  0x1c  0x2  0x0  0x2  0x0 	/* RxD5 */
150					0x4  0x1b  0x2  0x0  0x2  0x0 	/* RxD6 */
151					0x4  0x1a  0x2  0x0  0x2  0x0 	/* RxD7 */
152					0x4  0xb  0x1  0x0  0x2  0x0 	/* TX_EN */
153					0x4  0x18  0x1  0x0  0x2  0x0 	/* TX_ER */
154					0x4  0x10  0x2  0x0  0x2  0x0 	/* RX_DV */
155					0x4  0x1e  0x2  0x0  0x2  0x0 	/* RX_ER */
156					0x4  0x11  0x2  0x0  0x2  0x0 	/* RX_CLK */
157					0x4  0x13  0x1  0x0  0x2  0x0 	/* GTX_CLK */
158					0x1  0x1f  0x2  0x0  0x3  0x0>;	/* GTX125 */
159			};
160
161			pio2: ucc_pin@02 {
162				pio-map = <
163			/* port  pin  dir  open_drain  assignment  has_irq */
164					0x5  0xa 0x1  0x0  0x2  0x0   /* TxD0 */
165					0x5  0x9 0x1  0x0  0x2  0x0   /* TxD1 */
166					0x5  0x8 0x1  0x0  0x2  0x0   /* TxD2 */
167					0x5  0x7 0x1  0x0  0x2  0x0   /* TxD3 */
168					0x5  0x17 0x1  0x0  0x2  0x0   /* TxD4 */
169					0x5  0x16 0x1  0x0  0x2  0x0   /* TxD5 */
170					0x5  0x15 0x1  0x0  0x2  0x0   /* TxD6 */
171					0x5  0x14 0x1  0x0  0x2  0x0   /* TxD7 */
172					0x5  0xf 0x2  0x0  0x2  0x0   /* RxD0 */
173					0x5  0xe 0x2  0x0  0x2  0x0   /* RxD1 */
174					0x5  0xd 0x2  0x0  0x2  0x0   /* RxD2 */
175					0x5  0xc 0x2  0x0  0x2  0x0   /* RxD3 */
176					0x5  0x1d 0x2  0x0  0x2  0x0   /* RxD4 */
177					0x5  0x1c 0x2  0x0  0x2  0x0   /* RxD5 */
178					0x5  0x1b 0x2  0x0  0x2  0x0   /* RxD6 */
179					0x5  0x1a 0x2  0x0  0x2  0x0   /* RxD7 */
180					0x5  0xb 0x1  0x0  0x2  0x0   /* TX_EN */
181					0x5  0x18 0x1  0x0  0x2  0x0   /* TX_ER */
182					0x5  0x10 0x2  0x0  0x2  0x0   /* RX_DV */
183					0x5  0x1e 0x2  0x0  0x2  0x0   /* RX_ER */
184					0x5  0x11 0x2  0x0  0x2  0x0   /* RX_CLK */
185					0x5  0x13 0x1  0x0  0x2  0x0   /* GTX_CLK */
186					0x1  0x1f 0x2  0x0  0x3  0x0   /* GTX125 */
187					0x4  0x6 0x3  0x0  0x2  0x0   /* MDIO */
188					0x4  0x5 0x1  0x0  0x2  0x0>; /* MDC */
189			};
190		};
191	};
192
193	qe: qe@e0080000 {
194		ranges = <0x0 0x0 0xe0080000 0x40000>;
195		reg = <0x0 0xe0080000 0x0 0x480>;
196
197		spi@4c0 {
198			mode = "cpu";
199		};
200
201		spi@500 {
202			mode = "cpu";
203		};
204
205		enet2: ucc@2000 {
206			device_type = "network";
207			compatible = "ucc_geth";
208			local-mac-address = [ 00 00 00 00 00 00 ];
209			rx-clock-name = "none";
210			tx-clock-name = "clk16";
211			pio-handle = <&pio1>;
212			phy-handle = <&phy0>;
213			phy-connection-type = "rgmii-id";
214		};
215
216		enet3: ucc@3000 {
217			device_type = "network";
218			compatible = "ucc_geth";
219			local-mac-address = [ 00 00 00 00 00 00 ];
220			rx-clock-name = "none";
221			tx-clock-name = "clk16";
222			pio-handle = <&pio2>;
223			phy-handle = <&phy1>;
224			phy-connection-type = "rgmii-id";
225		};
226
227		mdio@2120 {
228			#address-cells = <1>;
229			#size-cells = <0>;
230			reg = <0x2120 0x18>;
231			compatible = "fsl,ucc-mdio";
232
233			/* These are the same PHYs as on
234			 * gianfar's MDIO bus */
235			qe_phy0: ethernet-phy@07 {
236				interrupt-parent = <&mpic>;
237				interrupts = <1 1 0 0>;
238				reg = <0x7>;
239				device_type = "ethernet-phy";
240			};
241			qe_phy1: ethernet-phy@01 {
242				interrupt-parent = <&mpic>;
243				interrupts = <2 1 0 0>;
244				reg = <0x1>;
245				device_type = "ethernet-phy";
246			};
247			qe_phy2: ethernet-phy@02 {
248				interrupt-parent = <&mpic>;
249				interrupts = <1 1 0 0>;
250				reg = <0x2>;
251				device_type = "ethernet-phy";
252			};
253			qe_phy3: ethernet-phy@03 {
254				interrupt-parent = <&mpic>;
255				interrupts = <2 1 0 0>;
256				reg = <0x3>;
257				device_type = "ethernet-phy";
258			};
259		};
260	};
261
262	pci0: pci@e0008000 {
263		reg = <0x0 0xe0008000 0x0 0x1000>;
264		ranges = <0x2000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000
265			  0x1000000 0x0 0x00000000 0x0 0xe2000000 0x0 0x800000>;
266		clock-frequency = <66666666>;
267		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
268		interrupt-map = <
269			/* IDSEL 0x12 AD18 */
270			0x9000 0x0 0x0 0x1 &mpic 0x5 0x1 0 0
271			0x9000 0x0 0x0 0x2 &mpic 0x6 0x1 0 0
272			0x9000 0x0 0x0 0x3 &mpic 0x7 0x1 0 0
273			0x9000 0x0 0x0 0x4 &mpic 0x4 0x1 0 0
274
275			/* IDSEL 0x13 AD19 */
276			0x9800 0x0 0x0 0x1 &mpic 0x6 0x1 0 0
277			0x9800 0x0 0x0 0x2 &mpic 0x7 0x1 0 0
278			0x9800 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
279			0x9800 0x0 0x0 0x4 &mpic 0x5 0x1 0 0>;
280	};
281
282	/* PCI Express */
283	pci1: pcie@e000a000 {
284		ranges = <0x2000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x10000000
285			  0x1000000 0x0 0x00000000 0x0 0xe2800000 0x0 0x800000>;
286		reg = <0x0 0xe000a000 0x0 0x1000>;
287		pcie@0 {
288			ranges = <0x2000000 0x0 0xa0000000
289				  0x2000000 0x0 0xa0000000
290				  0x0 0x10000000
291
292				  0x1000000 0x0 0x0
293				  0x1000000 0x0 0x0
294				  0x0 0x800000>;
295		};
296	};
297
298	rio: rapidio@e00c00000 {
299		reg = <0x0 0xe00c0000 0x0 0x20000>;
300		port1 {
301			ranges = <0x0 0x0 0x0 0xc0000000 0x0 0x20000000>;
302		};
303	};
304
305	leds {
306		compatible = "gpio-leds";
307
308		green {
309			gpios = <&bcsr5 1 0>;
310		};
311
312		amber {
313			gpios = <&bcsr5 2 0>;
314		};
315
316		red {
317			gpios = <&bcsr5 3 0>;
318		};
319	};
320};
321
322/include/ "fsl/mpc8568si-post.dtsi"