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/arch/powerpc/boot/dts/gef_ppc9a.dts

http://github.com/mirrors/linux
Device Tree | 427 lines | 346 code | 39 blank | 42 comment | 0 complexity | bd836775e426f255b0857fc491c6e56c MD5 | raw file
  1/*
  2 * GE PPC9A Device Tree Source
  3 *
  4 * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
  5 *
  6 * This program is free software; you can redistribute  it and/or modify it
  7 * under  the terms of  the GNU General  Public License as published by the
  8 * Free Software Foundation;  either version 2 of the  License, or (at your
  9 * option) any later version.
 10 *
 11 * Based on: SBS CM6 Device Tree Source
 12 * Copyright 2007 SBS Technologies GmbH & Co. KG
 13 * And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source)
 14 * Copyright 2006 Freescale Semiconductor Inc.
 15 */
 16
 17/*
 18 * Compiled with dtc -I dts -O dtb -o gef_ppc9a.dtb gef_ppc9a.dts
 19 */
 20
 21/dts-v1/;
 22
 23/ {
 24	model = "GEF_PPC9A";
 25	compatible = "gef,ppc9a";
 26	#address-cells = <1>;
 27	#size-cells = <1>;
 28
 29	aliases {
 30		ethernet0 = &enet0;
 31		ethernet1 = &enet1;
 32		serial0 = &serial0;
 33		serial1 = &serial1;
 34		pci0 = &pci0;
 35	};
 36
 37	cpus {
 38		#address-cells = <1>;
 39		#size-cells = <0>;
 40
 41		PowerPC,8641@0 {
 42			device_type = "cpu";
 43			reg = <0>;
 44			d-cache-line-size = <32>;	// 32 bytes
 45			i-cache-line-size = <32>;	// 32 bytes
 46			d-cache-size = <32768>;		// L1, 32K
 47			i-cache-size = <32768>;		// L1, 32K
 48			timebase-frequency = <0>;	// From uboot
 49			bus-frequency = <0>;		// From uboot
 50			clock-frequency = <0>;		// From uboot
 51		};
 52		PowerPC,8641@1 {
 53			device_type = "cpu";
 54			reg = <1>;
 55			d-cache-line-size = <32>;	// 32 bytes
 56			i-cache-line-size = <32>;	// 32 bytes
 57			d-cache-size = <32768>;		// L1, 32K
 58			i-cache-size = <32768>;		// L1, 32K
 59			timebase-frequency = <0>;	// From uboot
 60			bus-frequency = <0>;		// From uboot
 61			clock-frequency = <0>;		// From uboot
 62		};
 63	};
 64
 65	memory {
 66		device_type = "memory";
 67		reg = <0x0 0x40000000>;	// set by uboot
 68	};
 69
 70	localbus@fef05000 {
 71		#address-cells = <2>;
 72		#size-cells = <1>;
 73		compatible = "fsl,mpc8641-localbus", "simple-bus";
 74		reg = <0xfef05000 0x1000>;
 75		interrupts = <19 2>;
 76		interrupt-parent = <&mpic>;
 77
 78		ranges = <0 0 0xff000000 0x01000000	// 16MB Boot flash
 79			  1 0 0xe8000000 0x08000000	// Paged Flash 0
 80			  2 0 0xe0000000 0x08000000	// Paged Flash 1
 81			  3 0 0xfc100000 0x00020000	// NVRAM
 82			  4 0 0xfc000000 0x00008000	// FPGA
 83			  5 0 0xfc008000 0x00008000	// AFIX FPGA
 84			  6 0 0xfd000000 0x00800000	// IO FPGA (8-bit)
 85			  7 0 0xfd800000 0x00800000>;	// IO FPGA (32-bit)
 86
 87		/* flash@0,0 is a mirror of part of the memory in flash@1,0
 88		flash@0,0 {
 89			compatible = "gef,ppc9a-firmware-mirror", "cfi-flash";
 90			reg = <0x0 0x0 0x1000000>;
 91			bank-width = <4>;
 92			device-width = <2>;
 93			#address-cells = <1>;
 94			#size-cells = <1>;
 95			partition@0 {
 96				label = "firmware";
 97				reg = <0x0 0x1000000>;
 98				read-only;
 99			};
100		};
101		*/
102
103		flash@1,0 {
104			compatible = "gef,ppc9a-paged-flash", "cfi-flash";
105			reg = <0x1 0x0 0x8000000>;
106			bank-width = <4>;
107			device-width = <2>;
108			#address-cells = <1>;
109			#size-cells = <1>;
110			partition@0 {
111				label = "user";
112				reg = <0x0 0x7800000>;
113			};
114			partition@7800000 {
115				label = "firmware";
116				reg = <0x7800000 0x800000>;
117				read-only;
118			};
119		};
120
121		nvram@3,0 {
122			device_type = "nvram";
123			compatible = "simtek,stk14ca8";
124			reg = <0x3 0x0 0x20000>;
125		};
126
127		fpga@4,0 {
128			compatible = "gef,ppc9a-fpga-regs";
129			reg = <0x4 0x0 0x40>;
130		};
131
132		wdt@4,2000 {
133			compatible = "gef,ppc9a-fpga-wdt", "gef,fpga-wdt-1.00",
134				"gef,fpga-wdt";
135			reg = <0x4 0x2000 0x8>;
136			interrupts = <0x1a 0x4>;
137			interrupt-parent = <&gef_pic>;
138		};
139		/* Second watchdog available, driver currently supports one.
140		wdt@4,2010 {
141			compatible = "gef,ppc9a-fpga-wdt", "gef,fpga-wdt-1.00",
142				"gef,fpga-wdt";
143			reg = <0x4 0x2010 0x8>;
144			interrupts = <0x1b 0x4>;
145			interrupt-parent = <&gef_pic>;
146		};
147		*/
148		gef_pic: pic@4,4000 {
149			#interrupt-cells = <1>;
150			interrupt-controller;
151			compatible = "gef,ppc9a-fpga-pic", "gef,fpga-pic-1.00";
152			reg = <0x4 0x4000 0x20>;
153			interrupts = <0x8
154				      0x9>;
155			interrupt-parent = <&mpic>;
156
157		};
158		gef_gpio: gpio@7,14000 {
159			#gpio-cells = <2>;
160			compatible = "gef,ppc9a-gpio", "gef,sbc610-gpio";
161			reg = <0x7 0x14000 0x24>;
162			gpio-controller;
163		};
164	};
165
166	soc@fef00000 {
167		#address-cells = <1>;
168		#size-cells = <1>;
169		#interrupt-cells = <2>;
170		device_type = "soc";
171		compatible = "fsl,mpc8641-soc", "simple-bus";
172		ranges = <0x0 0xfef00000 0x00100000>;
173		bus-frequency = <33333333>;
174
175		mcm-law@0 {
176			compatible = "fsl,mcm-law";
177			reg = <0x0 0x1000>;
178			fsl,num-laws = <10>;
179		};
180
181		mcm@1000 {
182			compatible = "fsl,mpc8641-mcm", "fsl,mcm";
183			reg = <0x1000 0x1000>;
184			interrupts = <17 2>;
185			interrupt-parent = <&mpic>;
186		};
187
188		i2c1: i2c@3000 {
189			#address-cells = <1>;
190			#size-cells = <0>;
191			compatible = "fsl-i2c";
192			reg = <0x3000 0x100>;
193			interrupts = <0x2b 0x2>;
194			interrupt-parent = <&mpic>;
195			dfsrr;
196
197			hwmon@48 {
198				compatible = "national,lm92";
199				reg = <0x48>;
200			};
201
202			hwmon@4c {
203				compatible = "adi,adt7461";
204				reg = <0x4c>;
205			};
206
207			rtc@51 {
208				compatible = "epson,rx8581";
209				reg = <0x00000051>;
210			};
211
212			eti@6b {
213				compatible = "dallas,ds1682";
214				reg = <0x6b>;
215			};
216		};
217
218		i2c2: i2c@3100 {
219			#address-cells = <1>;
220			#size-cells = <0>;
221			compatible = "fsl-i2c";
222			reg = <0x3100 0x100>;
223			interrupts = <0x2b 0x2>;
224			interrupt-parent = <&mpic>;
225			dfsrr;
226		};
227
228		dma@21300 {
229			#address-cells = <1>;
230			#size-cells = <1>;
231			compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
232			reg = <0x21300 0x4>;
233			ranges = <0x0 0x21100 0x200>;
234			cell-index = <0>;
235			dma-channel@0 {
236				compatible = "fsl,mpc8641-dma-channel",
237					   "fsl,eloplus-dma-channel";
238				reg = <0x0 0x80>;
239				cell-index = <0>;
240				interrupt-parent = <&mpic>;
241				interrupts = <20 2>;
242			};
243			dma-channel@80 {
244				compatible = "fsl,mpc8641-dma-channel",
245					   "fsl,eloplus-dma-channel";
246				reg = <0x80 0x80>;
247				cell-index = <1>;
248				interrupt-parent = <&mpic>;
249				interrupts = <21 2>;
250			};
251			dma-channel@100 {
252				compatible = "fsl,mpc8641-dma-channel",
253					   "fsl,eloplus-dma-channel";
254				reg = <0x100 0x80>;
255				cell-index = <2>;
256				interrupt-parent = <&mpic>;
257				interrupts = <22 2>;
258			};
259			dma-channel@180 {
260				compatible = "fsl,mpc8641-dma-channel",
261					   "fsl,eloplus-dma-channel";
262				reg = <0x180 0x80>;
263				cell-index = <3>;
264				interrupt-parent = <&mpic>;
265				interrupts = <23 2>;
266			};
267		};
268
269		enet0: ethernet@24000 {
270			#address-cells = <1>;
271			#size-cells = <1>;
272			cell-index = <0>;
273			device_type = "network";
274			model = "TSEC";
275			compatible = "gianfar";
276			reg = <0x24000 0x1000>;
277			ranges = <0x0 0x24000 0x1000>;
278			local-mac-address = [ 00 00 00 00 00 00 ];
279			interrupts = <29 2 30  2 34 2>;
280			interrupt-parent = <&mpic>;
281			tbi-handle = <&tbi0>;
282			phy-handle = <&phy0>;
283			phy-connection-type = "gmii";
284
285			mdio@520 {
286				#address-cells = <1>;
287				#size-cells = <0>;
288				compatible = "fsl,gianfar-mdio";
289				reg = <0x520 0x20>;
290
291				phy0: ethernet-phy@0 {
292					interrupt-parent = <&gef_pic>;
293					interrupts = <0x9 0x4>;
294					reg = <1>;
295					device_type = "ethernet-phy";
296				};
297				phy2: ethernet-phy@2 {
298					interrupt-parent = <&gef_pic>;
299					interrupts = <0x8 0x4>;
300					reg = <3>;
301					device_type = "ethernet-phy";
302				};
303				tbi0: tbi-phy@11 {
304					reg = <0x11>;
305					device_type = "tbi-phy";
306				};
307			};
308		};
309
310		enet1: ethernet@26000 {
311			#address-cells = <1>;
312			#size-cells = <1>;
313			cell-index = <2>;
314			device_type = "network";
315			model = "TSEC";
316			compatible = "gianfar";
317			reg = <0x26000 0x1000>;
318			ranges = <0x0 0x26000 0x1000>;
319			local-mac-address = [ 00 00 00 00 00 00 ];
320			interrupts = <31 2 32 2 33 2>;
321			interrupt-parent = <&mpic>;
322			tbi-handle = <&tbi2>;
323			phy-handle = <&phy2>;
324			phy-connection-type = "gmii";
325
326			mdio@520 {
327				#address-cells = <1>;
328				#size-cells = <0>;
329				compatible = "fsl,gianfar-tbi";
330				reg = <0x520 0x20>;
331
332				tbi2: tbi-phy@11 {
333					reg = <0x11>;
334					device_type = "tbi-phy";
335				};
336			};
337		};
338
339		serial0: serial@4500 {
340			cell-index = <0>;
341			device_type = "serial";
342			compatible = "fsl,ns16550", "ns16550";
343			reg = <0x4500 0x100>;
344			clock-frequency = <0>;
345			interrupts = <0x2a 0x2>;
346			interrupt-parent = <&mpic>;
347		};
348
349		serial1: serial@4600 {
350			cell-index = <1>;
351			device_type = "serial";
352			compatible = "fsl,ns16550", "ns16550";
353			reg = <0x4600 0x100>;
354			clock-frequency = <0>;
355			interrupts = <0x1c 0x2>;
356			interrupt-parent = <&mpic>;
357		};
358
359		mpic: pic@40000 {
360			clock-frequency = <0>;
361			interrupt-controller;
362			#address-cells = <0>;
363			#interrupt-cells = <2>;
364			reg = <0x40000 0x40000>;
365			compatible = "chrp,open-pic";
366			device_type = "open-pic";
367		};
368
369		msi@41600 {
370			compatible = "fsl,mpc8641-msi", "fsl,mpic-msi";
371			reg = <0x41600 0x80>;
372			msi-available-ranges = <0 0x100>;
373			interrupts = <
374				0xe0 0
375				0xe1 0
376				0xe2 0
377				0xe3 0
378				0xe4 0
379				0xe5 0
380				0xe6 0
381				0xe7 0>;
382			interrupt-parent = <&mpic>;
383		};
384
385		global-utilities@e0000 {
386			compatible = "fsl,mpc8641-guts";
387			reg = <0xe0000 0x1000>;
388			fsl,has-rstcr;
389		};
390	};
391
392	pci0: pcie@fef08000 {
393		compatible = "fsl,mpc8641-pcie";
394		device_type = "pci";
395		#interrupt-cells = <1>;
396		#size-cells = <2>;
397		#address-cells = <3>;
398		reg = <0xfef08000 0x1000>;
399		bus-range = <0x0 0xff>;
400		ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000
401			  0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>;
402		clock-frequency = <33333333>;
403		interrupt-parent = <&mpic>;
404		interrupts = <0x18 0x2>;
405		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
406		interrupt-map = <
407			0x0000 0x0 0x0 0x1 &mpic 0x0 0x1
408			0x0000 0x0 0x0 0x2 &mpic 0x1 0x1
409			0x0000 0x0 0x0 0x3 &mpic 0x2 0x1
410			0x0000 0x0 0x0 0x4 &mpic 0x3 0x1
411		>;
412
413		pcie@0 {
414			reg = <0 0 0 0 0>;
415			#size-cells = <2>;
416			#address-cells = <3>;
417			device_type = "pci";
418			ranges = <0x02000000 0x0 0x80000000
419				  0x02000000 0x0 0x80000000
420				  0x0 0x40000000
421
422				  0x01000000 0x0 0x00000000
423				  0x01000000 0x0 0x00000000
424				  0x0 0x00400000>;
425		};
426	};
427};