/arch/powerpc/kernel/misc_64.S

http://github.com/mirrors/linux · Assembly · 532 lines · 335 code · 59 blank · 138 comment · 2 complexity · 9c83d936fa34d4ed7ee3bf4a3e857c2b MD5 · raw file

  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * This file contains miscellaneous low-level functions.
  4. * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  5. *
  6. * Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
  7. * and Paul Mackerras.
  8. * Adapted for iSeries by Mike Corrigan (mikejc@us.ibm.com)
  9. * PPC64 updates by Dave Engebretsen (engebret@us.ibm.com)
  10. */
  11. #include <linux/sys.h>
  12. #include <asm/unistd.h>
  13. #include <asm/errno.h>
  14. #include <asm/processor.h>
  15. #include <asm/page.h>
  16. #include <asm/cache.h>
  17. #include <asm/ppc_asm.h>
  18. #include <asm/asm-offsets.h>
  19. #include <asm/cputable.h>
  20. #include <asm/thread_info.h>
  21. #include <asm/kexec.h>
  22. #include <asm/ptrace.h>
  23. #include <asm/mmu.h>
  24. #include <asm/export.h>
  25. #include <asm/feature-fixups.h>
  26. .text
  27. _GLOBAL(call_do_softirq)
  28. mflr r0
  29. std r0,16(r1)
  30. stdu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r3)
  31. mr r1,r3
  32. bl __do_softirq
  33. ld r1,0(r1)
  34. ld r0,16(r1)
  35. mtlr r0
  36. blr
  37. _GLOBAL(call_do_irq)
  38. mflr r0
  39. std r0,16(r1)
  40. stdu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r4)
  41. mr r1,r4
  42. bl __do_irq
  43. ld r1,0(r1)
  44. ld r0,16(r1)
  45. mtlr r0
  46. blr
  47. _GLOBAL(__bswapdi2)
  48. EXPORT_SYMBOL(__bswapdi2)
  49. srdi r8,r3,32
  50. rlwinm r7,r3,8,0xffffffff
  51. rlwimi r7,r3,24,0,7
  52. rlwinm r9,r8,8,0xffffffff
  53. rlwimi r7,r3,24,16,23
  54. rlwimi r9,r8,24,0,7
  55. rlwimi r9,r8,24,16,23
  56. sldi r7,r7,32
  57. or r3,r7,r9
  58. blr
  59. #ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX
  60. _GLOBAL(rmci_on)
  61. sync
  62. isync
  63. li r3,0x100
  64. rldicl r3,r3,32,0
  65. mfspr r5,SPRN_HID4
  66. or r5,r5,r3
  67. sync
  68. mtspr SPRN_HID4,r5
  69. isync
  70. slbia
  71. isync
  72. sync
  73. blr
  74. _GLOBAL(rmci_off)
  75. sync
  76. isync
  77. li r3,0x100
  78. rldicl r3,r3,32,0
  79. mfspr r5,SPRN_HID4
  80. andc r5,r5,r3
  81. sync
  82. mtspr SPRN_HID4,r5
  83. isync
  84. slbia
  85. isync
  86. sync
  87. blr
  88. #endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */
  89. #if defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE)
  90. /*
  91. * Do an IO access in real mode
  92. */
  93. _GLOBAL(real_readb)
  94. mfmsr r7
  95. ori r0,r7,MSR_DR
  96. xori r0,r0,MSR_DR
  97. sync
  98. mtmsrd r0
  99. sync
  100. isync
  101. mfspr r6,SPRN_HID4
  102. rldicl r5,r6,32,0
  103. ori r5,r5,0x100
  104. rldicl r5,r5,32,0
  105. sync
  106. mtspr SPRN_HID4,r5
  107. isync
  108. slbia
  109. isync
  110. lbz r3,0(r3)
  111. sync
  112. mtspr SPRN_HID4,r6
  113. isync
  114. slbia
  115. isync
  116. mtmsrd r7
  117. sync
  118. isync
  119. blr
  120. /*
  121. * Do an IO access in real mode
  122. */
  123. _GLOBAL(real_writeb)
  124. mfmsr r7
  125. ori r0,r7,MSR_DR
  126. xori r0,r0,MSR_DR
  127. sync
  128. mtmsrd r0
  129. sync
  130. isync
  131. mfspr r6,SPRN_HID4
  132. rldicl r5,r6,32,0
  133. ori r5,r5,0x100
  134. rldicl r5,r5,32,0
  135. sync
  136. mtspr SPRN_HID4,r5
  137. isync
  138. slbia
  139. isync
  140. stb r3,0(r4)
  141. sync
  142. mtspr SPRN_HID4,r6
  143. isync
  144. slbia
  145. isync
  146. mtmsrd r7
  147. sync
  148. isync
  149. blr
  150. #endif /* defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE) */
  151. #ifdef CONFIG_PPC_PASEMI
  152. _GLOBAL(real_205_readb)
  153. mfmsr r7
  154. ori r0,r7,MSR_DR
  155. xori r0,r0,MSR_DR
  156. sync
  157. mtmsrd r0
  158. sync
  159. isync
  160. LBZCIX(R3,R0,R3)
  161. isync
  162. mtmsrd r7
  163. sync
  164. isync
  165. blr
  166. _GLOBAL(real_205_writeb)
  167. mfmsr r7
  168. ori r0,r7,MSR_DR
  169. xori r0,r0,MSR_DR
  170. sync
  171. mtmsrd r0
  172. sync
  173. isync
  174. STBCIX(R3,R0,R4)
  175. isync
  176. mtmsrd r7
  177. sync
  178. isync
  179. blr
  180. #endif /* CONFIG_PPC_PASEMI */
  181. #if defined(CONFIG_CPU_FREQ_PMAC64) || defined(CONFIG_CPU_FREQ_MAPLE)
  182. /*
  183. * SCOM access functions for 970 (FX only for now)
  184. *
  185. * unsigned long scom970_read(unsigned int address);
  186. * void scom970_write(unsigned int address, unsigned long value);
  187. *
  188. * The address passed in is the 24 bits register address. This code
  189. * is 970 specific and will not check the status bits, so you should
  190. * know what you are doing.
  191. */
  192. _GLOBAL(scom970_read)
  193. /* interrupts off */
  194. mfmsr r4
  195. ori r0,r4,MSR_EE
  196. xori r0,r0,MSR_EE
  197. mtmsrd r0,1
  198. /* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits
  199. * (including parity). On current CPUs they must be 0'd,
  200. * and finally or in RW bit
  201. */
  202. rlwinm r3,r3,8,0,15
  203. ori r3,r3,0x8000
  204. /* do the actual scom read */
  205. sync
  206. mtspr SPRN_SCOMC,r3
  207. isync
  208. mfspr r3,SPRN_SCOMD
  209. isync
  210. mfspr r0,SPRN_SCOMC
  211. isync
  212. /* XXX: fixup result on some buggy 970's (ouch ! we lost a bit, bah
  213. * that's the best we can do). Not implemented yet as we don't use
  214. * the scom on any of the bogus CPUs yet, but may have to be done
  215. * ultimately
  216. */
  217. /* restore interrupts */
  218. mtmsrd r4,1
  219. blr
  220. _GLOBAL(scom970_write)
  221. /* interrupts off */
  222. mfmsr r5
  223. ori r0,r5,MSR_EE
  224. xori r0,r0,MSR_EE
  225. mtmsrd r0,1
  226. /* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits
  227. * (including parity). On current CPUs they must be 0'd.
  228. */
  229. rlwinm r3,r3,8,0,15
  230. sync
  231. mtspr SPRN_SCOMD,r4 /* write data */
  232. isync
  233. mtspr SPRN_SCOMC,r3 /* write command */
  234. isync
  235. mfspr 3,SPRN_SCOMC
  236. isync
  237. /* restore interrupts */
  238. mtmsrd r5,1
  239. blr
  240. #endif /* CONFIG_CPU_FREQ_PMAC64 || CONFIG_CPU_FREQ_MAPLE */
  241. /* kexec_wait(phys_cpu)
  242. *
  243. * wait for the flag to change, indicating this kernel is going away but
  244. * the slave code for the next one is at addresses 0 to 100.
  245. *
  246. * This is used by all slaves, even those that did not find a matching
  247. * paca in the secondary startup code.
  248. *
  249. * Physical (hardware) cpu id should be in r3.
  250. */
  251. _GLOBAL(kexec_wait)
  252. bl 1f
  253. 1: mflr r5
  254. addi r5,r5,kexec_flag-1b
  255. 99: HMT_LOW
  256. #ifdef CONFIG_KEXEC_CORE /* use no memory without kexec */
  257. lwz r4,0(r5)
  258. cmpwi 0,r4,0
  259. beq 99b
  260. #ifdef CONFIG_PPC_BOOK3S_64
  261. li r10,0x60
  262. mfmsr r11
  263. clrrdi r11,r11,1 /* Clear MSR_LE */
  264. mtsrr0 r10
  265. mtsrr1 r11
  266. rfid
  267. #else
  268. /* Create TLB entry in book3e_secondary_core_init */
  269. li r4,0
  270. ba 0x60
  271. #endif
  272. #endif
  273. /* this can be in text because we won't change it until we are
  274. * running in real anyways
  275. */
  276. kexec_flag:
  277. .long 0
  278. #ifdef CONFIG_KEXEC_CORE
  279. #ifdef CONFIG_PPC_BOOK3E
  280. /*
  281. * BOOK3E has no real MMU mode, so we have to setup the initial TLB
  282. * for a core to identity map v:0 to p:0. This current implementation
  283. * assumes that 1G is enough for kexec.
  284. */
  285. kexec_create_tlb:
  286. /*
  287. * Invalidate all non-IPROT TLB entries to avoid any TLB conflict.
  288. * IPROT TLB entries should be >= PAGE_OFFSET and thus not conflict.
  289. */
  290. PPC_TLBILX_ALL(0,R0)
  291. sync
  292. isync
  293. mfspr r10,SPRN_TLB1CFG
  294. andi. r10,r10,TLBnCFG_N_ENTRY /* Extract # entries */
  295. subi r10,r10,1 /* Last entry: no conflict with kernel text */
  296. lis r9,MAS0_TLBSEL(1)@h
  297. rlwimi r9,r10,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r9) */
  298. /* Set up a temp identity mapping v:0 to p:0 and return to it. */
  299. mtspr SPRN_MAS0,r9
  300. lis r9,(MAS1_VALID|MAS1_IPROT)@h
  301. ori r9,r9,(MAS1_TSIZE(BOOK3E_PAGESZ_1GB))@l
  302. mtspr SPRN_MAS1,r9
  303. LOAD_REG_IMMEDIATE(r9, 0x0 | MAS2_M_IF_NEEDED)
  304. mtspr SPRN_MAS2,r9
  305. LOAD_REG_IMMEDIATE(r9, 0x0 | MAS3_SR | MAS3_SW | MAS3_SX)
  306. mtspr SPRN_MAS3,r9
  307. li r9,0
  308. mtspr SPRN_MAS7,r9
  309. tlbwe
  310. isync
  311. blr
  312. #endif
  313. /* kexec_smp_wait(void)
  314. *
  315. * call with interrupts off
  316. * note: this is a terminal routine, it does not save lr
  317. *
  318. * get phys id from paca
  319. * switch to real mode
  320. * mark the paca as no longer used
  321. * join other cpus in kexec_wait(phys_id)
  322. */
  323. _GLOBAL(kexec_smp_wait)
  324. lhz r3,PACAHWCPUID(r13)
  325. bl real_mode
  326. li r4,KEXEC_STATE_REAL_MODE
  327. stb r4,PACAKEXECSTATE(r13)
  328. SYNC
  329. b kexec_wait
  330. /*
  331. * switch to real mode (turn mmu off)
  332. * we use the early kernel trick that the hardware ignores bits
  333. * 0 and 1 (big endian) of the effective address in real mode
  334. *
  335. * don't overwrite r3 here, it is live for kexec_wait above.
  336. */
  337. real_mode: /* assume normal blr return */
  338. #ifdef CONFIG_PPC_BOOK3E
  339. /* Create an identity mapping. */
  340. b kexec_create_tlb
  341. #else
  342. 1: li r9,MSR_RI
  343. li r10,MSR_DR|MSR_IR
  344. mflr r11 /* return address to SRR0 */
  345. mfmsr r12
  346. andc r9,r12,r9
  347. andc r10,r12,r10
  348. mtmsrd r9,1
  349. mtspr SPRN_SRR1,r10
  350. mtspr SPRN_SRR0,r11
  351. rfid
  352. #endif
  353. /*
  354. * kexec_sequence(newstack, start, image, control, clear_all(),
  355. copy_with_mmu_off)
  356. *
  357. * does the grungy work with stack switching and real mode switches
  358. * also does simple calls to other code
  359. */
  360. _GLOBAL(kexec_sequence)
  361. mflr r0
  362. std r0,16(r1)
  363. /* switch stacks to newstack -- &kexec_stack.stack */
  364. stdu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r3)
  365. mr r1,r3
  366. li r0,0
  367. std r0,16(r1)
  368. BEGIN_FTR_SECTION
  369. /*
  370. * This is the best time to turn AMR/IAMR off.
  371. * key 0 is used in radix for supervisor<->user
  372. * protection, but on hash key 0 is reserved
  373. * ideally we want to enter with a clean state.
  374. * NOTE, we rely on r0 being 0 from above.
  375. */
  376. mtspr SPRN_IAMR,r0
  377. BEGIN_FTR_SECTION_NESTED(42)
  378. mtspr SPRN_AMOR,r0
  379. END_FTR_SECTION_NESTED_IFSET(CPU_FTR_HVMODE, 42)
  380. END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
  381. /* save regs for local vars on new stack.
  382. * yes, we won't go back, but ...
  383. */
  384. std r31,-8(r1)
  385. std r30,-16(r1)
  386. std r29,-24(r1)
  387. std r28,-32(r1)
  388. std r27,-40(r1)
  389. std r26,-48(r1)
  390. std r25,-56(r1)
  391. stdu r1,-STACK_FRAME_OVERHEAD-64(r1)
  392. /* save args into preserved regs */
  393. mr r31,r3 /* newstack (both) */
  394. mr r30,r4 /* start (real) */
  395. mr r29,r5 /* image (virt) */
  396. mr r28,r6 /* control, unused */
  397. mr r27,r7 /* clear_all() fn desc */
  398. mr r26,r8 /* copy_with_mmu_off */
  399. lhz r25,PACAHWCPUID(r13) /* get our phys cpu from paca */
  400. /* disable interrupts, we are overwriting kernel data next */
  401. #ifdef CONFIG_PPC_BOOK3E
  402. wrteei 0
  403. #else
  404. mfmsr r3
  405. rlwinm r3,r3,0,17,15
  406. mtmsrd r3,1
  407. #endif
  408. /* We need to turn the MMU off unless we are in hash mode
  409. * under a hypervisor
  410. */
  411. cmpdi r26,0
  412. beq 1f
  413. bl real_mode
  414. 1:
  415. /* copy dest pages, flush whole dest image */
  416. mr r3,r29
  417. bl kexec_copy_flush /* (image) */
  418. /* turn off mmu now if not done earlier */
  419. cmpdi r26,0
  420. bne 1f
  421. bl real_mode
  422. /* copy 0x100 bytes starting at start to 0 */
  423. 1: li r3,0
  424. mr r4,r30 /* start, aka phys mem offset */
  425. li r5,0x100
  426. li r6,0
  427. bl copy_and_flush /* (dest, src, copy limit, start offset) */
  428. 1: /* assume normal blr return */
  429. /* release other cpus to the new kernel secondary start at 0x60 */
  430. mflr r5
  431. li r6,1
  432. stw r6,kexec_flag-1b(5)
  433. cmpdi r27,0
  434. beq 1f
  435. /* clear out hardware hash page table and tlb */
  436. #ifdef PPC64_ELF_ABI_v1
  437. ld r12,0(r27) /* deref function descriptor */
  438. #else
  439. mr r12,r27
  440. #endif
  441. mtctr r12
  442. bctrl /* mmu_hash_ops.hpte_clear_all(void); */
  443. /*
  444. * kexec image calling is:
  445. * the first 0x100 bytes of the entry point are copied to 0
  446. *
  447. * all slaves branch to slave = 0x60 (absolute)
  448. * slave(phys_cpu_id);
  449. *
  450. * master goes to start = entry point
  451. * start(phys_cpu_id, start, 0);
  452. *
  453. *
  454. * a wrapper is needed to call existing kernels, here is an approximate
  455. * description of one method:
  456. *
  457. * v2: (2.6.10)
  458. * start will be near the boot_block (maybe 0x100 bytes before it?)
  459. * it will have a 0x60, which will b to boot_block, where it will wait
  460. * and 0 will store phys into struct boot-block and load r3 from there,
  461. * copy kernel 0-0x100 and tell slaves to back down to 0x60 again
  462. *
  463. * v1: (2.6.9)
  464. * boot block will have all cpus scanning device tree to see if they
  465. * are the boot cpu ?????
  466. * other device tree differences (prop sizes, va vs pa, etc)...
  467. */
  468. 1: mr r3,r25 # my phys cpu
  469. mr r4,r30 # start, aka phys mem offset
  470. mtlr 4
  471. li r5,0
  472. blr /* image->start(physid, image->start, 0); */
  473. #endif /* CONFIG_KEXEC_CORE */