/arch/powerpc/kernel/head_64.S

http://github.com/mirrors/linux · Assembly · 1025 lines · 560 code · 115 blank · 350 comment · 1 complexity · f89e31acae6ede66db2e8457b64a0f8c MD5 · raw file

  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * PowerPC version
  4. * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  5. *
  6. * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
  7. * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
  8. * Adapted for Power Macintosh by Paul Mackerras.
  9. * Low-level exception handlers and MMU support
  10. * rewritten by Paul Mackerras.
  11. * Copyright (C) 1996 Paul Mackerras.
  12. *
  13. * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
  14. * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
  15. *
  16. * This file contains the entry point for the 64-bit kernel along
  17. * with some early initialization code common to all 64-bit powerpc
  18. * variants.
  19. */
  20. #include <linux/threads.h>
  21. #include <linux/init.h>
  22. #include <asm/reg.h>
  23. #include <asm/page.h>
  24. #include <asm/mmu.h>
  25. #include <asm/ppc_asm.h>
  26. #include <asm/head-64.h>
  27. #include <asm/asm-offsets.h>
  28. #include <asm/bug.h>
  29. #include <asm/cputable.h>
  30. #include <asm/setup.h>
  31. #include <asm/hvcall.h>
  32. #include <asm/thread_info.h>
  33. #include <asm/firmware.h>
  34. #include <asm/page_64.h>
  35. #include <asm/irqflags.h>
  36. #include <asm/kvm_book3s_asm.h>
  37. #include <asm/ptrace.h>
  38. #include <asm/hw_irq.h>
  39. #include <asm/cputhreads.h>
  40. #include <asm/ppc-opcode.h>
  41. #include <asm/export.h>
  42. #include <asm/feature-fixups.h>
  43. /* The physical memory is laid out such that the secondary processor
  44. * spin code sits at 0x0000...0x00ff. On server, the vectors follow
  45. * using the layout described in exceptions-64s.S
  46. */
  47. /*
  48. * Entering into this code we make the following assumptions:
  49. *
  50. * For pSeries or server processors:
  51. * 1. The MMU is off & open firmware is running in real mode.
  52. * 2. The primary CPU enters at __start.
  53. * 3. If the RTAS supports "query-cpu-stopped-state", then secondary
  54. * CPUs will enter as directed by "start-cpu" RTAS call, which is
  55. * generic_secondary_smp_init, with PIR in r3.
  56. * 4. Else the secondary CPUs will enter at secondary_hold (0x60) as
  57. * directed by the "start-cpu" RTS call, with PIR in r3.
  58. * -or- For OPAL entry:
  59. * 1. The MMU is off, processor in HV mode.
  60. * 2. The primary CPU enters at 0 with device-tree in r3, OPAL base
  61. * in r8, and entry in r9 for debugging purposes.
  62. * 3. Secondary CPUs enter as directed by OPAL_START_CPU call, which
  63. * is at generic_secondary_smp_init, with PIR in r3.
  64. *
  65. * For Book3E processors:
  66. * 1. The MMU is on running in AS0 in a state defined in ePAPR
  67. * 2. The kernel is entered at __start
  68. */
  69. OPEN_FIXED_SECTION(first_256B, 0x0, 0x100)
  70. USE_FIXED_SECTION(first_256B)
  71. /*
  72. * Offsets are relative from the start of fixed section, and
  73. * first_256B starts at 0. Offsets are a bit easier to use here
  74. * than the fixed section entry macros.
  75. */
  76. . = 0x0
  77. _GLOBAL(__start)
  78. /* NOP this out unconditionally */
  79. BEGIN_FTR_SECTION
  80. FIXUP_ENDIAN
  81. b __start_initialization_multiplatform
  82. END_FTR_SECTION(0, 1)
  83. /* Catch branch to 0 in real mode */
  84. trap
  85. /* Secondary processors spin on this value until it becomes non-zero.
  86. * When non-zero, it contains the real address of the function the cpu
  87. * should jump to.
  88. */
  89. .balign 8
  90. .globl __secondary_hold_spinloop
  91. __secondary_hold_spinloop:
  92. .8byte 0x0
  93. /* Secondary processors write this value with their cpu # */
  94. /* after they enter the spin loop immediately below. */
  95. .globl __secondary_hold_acknowledge
  96. __secondary_hold_acknowledge:
  97. .8byte 0x0
  98. #ifdef CONFIG_RELOCATABLE
  99. /* This flag is set to 1 by a loader if the kernel should run
  100. * at the loaded address instead of the linked address. This
  101. * is used by kexec-tools to keep the the kdump kernel in the
  102. * crash_kernel region. The loader is responsible for
  103. * observing the alignment requirement.
  104. */
  105. #ifdef CONFIG_RELOCATABLE_TEST
  106. #define RUN_AT_LOAD_DEFAULT 1 /* Test relocation, do not copy to 0 */
  107. #else
  108. #define RUN_AT_LOAD_DEFAULT 0x72756e30 /* "run0" -- relocate to 0 by default */
  109. #endif
  110. /* Do not move this variable as kexec-tools knows about it. */
  111. . = 0x5c
  112. .globl __run_at_load
  113. __run_at_load:
  114. DEFINE_FIXED_SYMBOL(__run_at_load)
  115. .long RUN_AT_LOAD_DEFAULT
  116. #endif
  117. . = 0x60
  118. /*
  119. * The following code is used to hold secondary processors
  120. * in a spin loop after they have entered the kernel, but
  121. * before the bulk of the kernel has been relocated. This code
  122. * is relocated to physical address 0x60 before prom_init is run.
  123. * All of it must fit below the first exception vector at 0x100.
  124. * Use .globl here not _GLOBAL because we want __secondary_hold
  125. * to be the actual text address, not a descriptor.
  126. */
  127. .globl __secondary_hold
  128. __secondary_hold:
  129. FIXUP_ENDIAN
  130. #ifndef CONFIG_PPC_BOOK3E
  131. mfmsr r24
  132. ori r24,r24,MSR_RI
  133. mtmsrd r24 /* RI on */
  134. #endif
  135. /* Grab our physical cpu number */
  136. mr r24,r3
  137. /* stash r4 for book3e */
  138. mr r25,r4
  139. /* Tell the master cpu we're here */
  140. /* Relocation is off & we are located at an address less */
  141. /* than 0x100, so only need to grab low order offset. */
  142. std r24,(ABS_ADDR(__secondary_hold_acknowledge))(0)
  143. sync
  144. li r26,0
  145. #ifdef CONFIG_PPC_BOOK3E
  146. tovirt(r26,r26)
  147. #endif
  148. /* All secondary cpus wait here until told to start. */
  149. 100: ld r12,(ABS_ADDR(__secondary_hold_spinloop))(r26)
  150. cmpdi 0,r12,0
  151. beq 100b
  152. #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC_CORE)
  153. #ifdef CONFIG_PPC_BOOK3E
  154. tovirt(r12,r12)
  155. #endif
  156. mtctr r12
  157. mr r3,r24
  158. /*
  159. * it may be the case that other platforms have r4 right to
  160. * begin with, this gives us some safety in case it is not
  161. */
  162. #ifdef CONFIG_PPC_BOOK3E
  163. mr r4,r25
  164. #else
  165. li r4,0
  166. #endif
  167. /* Make sure that patched code is visible */
  168. isync
  169. bctr
  170. #else
  171. 0: trap
  172. EMIT_BUG_ENTRY 0b, __FILE__, __LINE__, 0
  173. #endif
  174. CLOSE_FIXED_SECTION(first_256B)
  175. /* This value is used to mark exception frames on the stack. */
  176. .section ".toc","aw"
  177. exception_marker:
  178. .tc ID_72656773_68657265[TC],0x7265677368657265
  179. .previous
  180. /*
  181. * On server, we include the exception vectors code here as it
  182. * relies on absolute addressing which is only possible within
  183. * this compilation unit
  184. */
  185. #ifdef CONFIG_PPC_BOOK3S
  186. #include "exceptions-64s.S"
  187. #else
  188. OPEN_TEXT_SECTION(0x100)
  189. #endif
  190. USE_TEXT_SECTION()
  191. #ifdef CONFIG_PPC_BOOK3E
  192. /*
  193. * The booting_thread_hwid holds the thread id we want to boot in cpu
  194. * hotplug case. It is set by cpu hotplug code, and is invalid by default.
  195. * The thread id is the same as the initial value of SPRN_PIR[THREAD_ID]
  196. * bit field.
  197. */
  198. .globl booting_thread_hwid
  199. booting_thread_hwid:
  200. .long INVALID_THREAD_HWID
  201. .align 3
  202. /*
  203. * start a thread in the same core
  204. * input parameters:
  205. * r3 = the thread physical id
  206. * r4 = the entry point where thread starts
  207. */
  208. _GLOBAL(book3e_start_thread)
  209. LOAD_REG_IMMEDIATE(r5, MSR_KERNEL)
  210. cmpwi r3, 0
  211. beq 10f
  212. cmpwi r3, 1
  213. beq 11f
  214. /* If the thread id is invalid, just exit. */
  215. b 13f
  216. 10:
  217. MTTMR(TMRN_IMSR0, 5)
  218. MTTMR(TMRN_INIA0, 4)
  219. b 12f
  220. 11:
  221. MTTMR(TMRN_IMSR1, 5)
  222. MTTMR(TMRN_INIA1, 4)
  223. 12:
  224. isync
  225. li r6, 1
  226. sld r6, r6, r3
  227. mtspr SPRN_TENS, r6
  228. 13:
  229. blr
  230. /*
  231. * stop a thread in the same core
  232. * input parameter:
  233. * r3 = the thread physical id
  234. */
  235. _GLOBAL(book3e_stop_thread)
  236. cmpwi r3, 0
  237. beq 10f
  238. cmpwi r3, 1
  239. beq 10f
  240. /* If the thread id is invalid, just exit. */
  241. b 13f
  242. 10:
  243. li r4, 1
  244. sld r4, r4, r3
  245. mtspr SPRN_TENC, r4
  246. 13:
  247. blr
  248. _GLOBAL(fsl_secondary_thread_init)
  249. mfspr r4,SPRN_BUCSR
  250. /* Enable branch prediction */
  251. lis r3,BUCSR_INIT@h
  252. ori r3,r3,BUCSR_INIT@l
  253. mtspr SPRN_BUCSR,r3
  254. isync
  255. /*
  256. * Fix PIR to match the linear numbering in the device tree.
  257. *
  258. * On e6500, the reset value of PIR uses the low three bits for
  259. * the thread within a core, and the upper bits for the core
  260. * number. There are two threads per core, so shift everything
  261. * but the low bit right by two bits so that the cpu numbering is
  262. * continuous.
  263. *
  264. * If the old value of BUCSR is non-zero, this thread has run
  265. * before. Thus, we assume we are coming from kexec or a similar
  266. * scenario, and PIR is already set to the correct value. This
  267. * is a bit of a hack, but there are limited opportunities for
  268. * getting information into the thread and the alternatives
  269. * seemed like they'd be overkill. We can't tell just by looking
  270. * at the old PIR value which state it's in, since the same value
  271. * could be valid for one thread out of reset and for a different
  272. * thread in Linux.
  273. */
  274. mfspr r3, SPRN_PIR
  275. cmpwi r4,0
  276. bne 1f
  277. rlwimi r3, r3, 30, 2, 30
  278. mtspr SPRN_PIR, r3
  279. 1:
  280. #endif
  281. _GLOBAL(generic_secondary_thread_init)
  282. mr r24,r3
  283. /* turn on 64-bit mode */
  284. bl enable_64b_mode
  285. /* get a valid TOC pointer, wherever we're mapped at */
  286. bl relative_toc
  287. tovirt(r2,r2)
  288. #ifdef CONFIG_PPC_BOOK3E
  289. /* Book3E initialization */
  290. mr r3,r24
  291. bl book3e_secondary_thread_init
  292. #endif
  293. b generic_secondary_common_init
  294. /*
  295. * On pSeries and most other platforms, secondary processors spin
  296. * in the following code.
  297. * At entry, r3 = this processor's number (physical cpu id)
  298. *
  299. * On Book3E, r4 = 1 to indicate that the initial TLB entry for
  300. * this core already exists (setup via some other mechanism such
  301. * as SCOM before entry).
  302. */
  303. _GLOBAL(generic_secondary_smp_init)
  304. FIXUP_ENDIAN
  305. mr r24,r3
  306. mr r25,r4
  307. /* turn on 64-bit mode */
  308. bl enable_64b_mode
  309. /* get a valid TOC pointer, wherever we're mapped at */
  310. bl relative_toc
  311. tovirt(r2,r2)
  312. #ifdef CONFIG_PPC_BOOK3E
  313. /* Book3E initialization */
  314. mr r3,r24
  315. mr r4,r25
  316. bl book3e_secondary_core_init
  317. /*
  318. * After common core init has finished, check if the current thread is the
  319. * one we wanted to boot. If not, start the specified thread and stop the
  320. * current thread.
  321. */
  322. LOAD_REG_ADDR(r4, booting_thread_hwid)
  323. lwz r3, 0(r4)
  324. li r5, INVALID_THREAD_HWID
  325. cmpw r3, r5
  326. beq 20f
  327. /*
  328. * The value of booting_thread_hwid has been stored in r3,
  329. * so make it invalid.
  330. */
  331. stw r5, 0(r4)
  332. /*
  333. * Get the current thread id and check if it is the one we wanted.
  334. * If not, start the one specified in booting_thread_hwid and stop
  335. * the current thread.
  336. */
  337. mfspr r8, SPRN_TIR
  338. cmpw r3, r8
  339. beq 20f
  340. /* start the specified thread */
  341. LOAD_REG_ADDR(r5, fsl_secondary_thread_init)
  342. ld r4, 0(r5)
  343. bl book3e_start_thread
  344. /* stop the current thread */
  345. mr r3, r8
  346. bl book3e_stop_thread
  347. 10:
  348. b 10b
  349. 20:
  350. #endif
  351. generic_secondary_common_init:
  352. /* Set up a paca value for this processor. Since we have the
  353. * physical cpu id in r24, we need to search the pacas to find
  354. * which logical id maps to our physical one.
  355. */
  356. #ifndef CONFIG_SMP
  357. b kexec_wait /* wait for next kernel if !SMP */
  358. #else
  359. LOAD_REG_ADDR(r8, paca_ptrs) /* Load paca_ptrs pointe */
  360. ld r8,0(r8) /* Get base vaddr of array */
  361. LOAD_REG_ADDR(r7, nr_cpu_ids) /* Load nr_cpu_ids address */
  362. lwz r7,0(r7) /* also the max paca allocated */
  363. li r5,0 /* logical cpu id */
  364. 1:
  365. sldi r9,r5,3 /* get paca_ptrs[] index from cpu id */
  366. ldx r13,r9,r8 /* r13 = paca_ptrs[cpu id] */
  367. lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */
  368. cmpw r6,r24 /* Compare to our id */
  369. beq 2f
  370. addi r5,r5,1
  371. cmpw r5,r7 /* Check if more pacas exist */
  372. blt 1b
  373. mr r3,r24 /* not found, copy phys to r3 */
  374. b kexec_wait /* next kernel might do better */
  375. 2: SET_PACA(r13)
  376. #ifdef CONFIG_PPC_BOOK3E
  377. addi r12,r13,PACA_EXTLB /* and TLB exc frame in another */
  378. mtspr SPRN_SPRG_TLB_EXFRAME,r12
  379. #endif
  380. /* From now on, r24 is expected to be logical cpuid */
  381. mr r24,r5
  382. /* See if we need to call a cpu state restore handler */
  383. LOAD_REG_ADDR(r23, cur_cpu_spec)
  384. ld r23,0(r23)
  385. ld r12,CPU_SPEC_RESTORE(r23)
  386. cmpdi 0,r12,0
  387. beq 3f
  388. #ifdef PPC64_ELF_ABI_v1
  389. ld r12,0(r12)
  390. #endif
  391. mtctr r12
  392. bctrl
  393. 3: LOAD_REG_ADDR(r3, spinning_secondaries) /* Decrement spinning_secondaries */
  394. lwarx r4,0,r3
  395. subi r4,r4,1
  396. stwcx. r4,0,r3
  397. bne 3b
  398. isync
  399. 4: HMT_LOW
  400. lbz r23,PACAPROCSTART(r13) /* Test if this processor should */
  401. /* start. */
  402. cmpwi 0,r23,0
  403. beq 4b /* Loop until told to go */
  404. sync /* order paca.run and cur_cpu_spec */
  405. isync /* In case code patching happened */
  406. /* Create a temp kernel stack for use before relocation is on. */
  407. ld r1,PACAEMERGSP(r13)
  408. subi r1,r1,STACK_FRAME_OVERHEAD
  409. b __secondary_start
  410. #endif /* SMP */
  411. /*
  412. * Turn the MMU off.
  413. * Assumes we're mapped EA == RA if the MMU is on.
  414. */
  415. #ifdef CONFIG_PPC_BOOK3S
  416. __mmu_off:
  417. mfmsr r3
  418. andi. r0,r3,MSR_IR|MSR_DR
  419. beqlr
  420. mflr r4
  421. andc r3,r3,r0
  422. mtspr SPRN_SRR0,r4
  423. mtspr SPRN_SRR1,r3
  424. sync
  425. rfid
  426. b . /* prevent speculative execution */
  427. #endif
  428. /*
  429. * Here is our main kernel entry point. We support currently 2 kind of entries
  430. * depending on the value of r5.
  431. *
  432. * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content
  433. * in r3...r7
  434. *
  435. * r5 == NULL -> kexec style entry. r3 is a physical pointer to the
  436. * DT block, r4 is a physical pointer to the kernel itself
  437. *
  438. */
  439. __start_initialization_multiplatform:
  440. /* Make sure we are running in 64 bits mode */
  441. bl enable_64b_mode
  442. /* Get TOC pointer (current runtime address) */
  443. bl relative_toc
  444. /* find out where we are now */
  445. bcl 20,31,$+4
  446. 0: mflr r26 /* r26 = runtime addr here */
  447. addis r26,r26,(_stext - 0b)@ha
  448. addi r26,r26,(_stext - 0b)@l /* current runtime base addr */
  449. /*
  450. * Are we booted from a PROM Of-type client-interface ?
  451. */
  452. cmpldi cr0,r5,0
  453. beq 1f
  454. b __boot_from_prom /* yes -> prom */
  455. 1:
  456. /* Save parameters */
  457. mr r31,r3
  458. mr r30,r4
  459. #ifdef CONFIG_PPC_EARLY_DEBUG_OPAL
  460. /* Save OPAL entry */
  461. mr r28,r8
  462. mr r29,r9
  463. #endif
  464. #ifdef CONFIG_PPC_BOOK3E
  465. bl start_initialization_book3e
  466. b __after_prom_start
  467. #else
  468. /* Setup some critical 970 SPRs before switching MMU off */
  469. mfspr r0,SPRN_PVR
  470. srwi r0,r0,16
  471. cmpwi r0,0x39 /* 970 */
  472. beq 1f
  473. cmpwi r0,0x3c /* 970FX */
  474. beq 1f
  475. cmpwi r0,0x44 /* 970MP */
  476. beq 1f
  477. cmpwi r0,0x45 /* 970GX */
  478. bne 2f
  479. 1: bl __cpu_preinit_ppc970
  480. 2:
  481. /* Switch off MMU if not already off */
  482. bl __mmu_off
  483. b __after_prom_start
  484. #endif /* CONFIG_PPC_BOOK3E */
  485. __REF
  486. __boot_from_prom:
  487. #ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE
  488. /* Save parameters */
  489. mr r31,r3
  490. mr r30,r4
  491. mr r29,r5
  492. mr r28,r6
  493. mr r27,r7
  494. /*
  495. * Align the stack to 16-byte boundary
  496. * Depending on the size and layout of the ELF sections in the initial
  497. * boot binary, the stack pointer may be unaligned on PowerMac
  498. */
  499. rldicr r1,r1,0,59
  500. #ifdef CONFIG_RELOCATABLE
  501. /* Relocate code for where we are now */
  502. mr r3,r26
  503. bl relocate
  504. #endif
  505. /* Restore parameters */
  506. mr r3,r31
  507. mr r4,r30
  508. mr r5,r29
  509. mr r6,r28
  510. mr r7,r27
  511. /* Do all of the interaction with OF client interface */
  512. mr r8,r26
  513. bl prom_init
  514. #endif /* #CONFIG_PPC_OF_BOOT_TRAMPOLINE */
  515. /* We never return. We also hit that trap if trying to boot
  516. * from OF while CONFIG_PPC_OF_BOOT_TRAMPOLINE isn't selected */
  517. trap
  518. .previous
  519. __after_prom_start:
  520. #ifdef CONFIG_RELOCATABLE
  521. /* process relocations for the final address of the kernel */
  522. lis r25,PAGE_OFFSET@highest /* compute virtual base of kernel */
  523. sldi r25,r25,32
  524. #if defined(CONFIG_PPC_BOOK3E)
  525. tovirt(r26,r26) /* on booke, we already run at PAGE_OFFSET */
  526. #endif
  527. lwz r7,(FIXED_SYMBOL_ABS_ADDR(__run_at_load))(r26)
  528. #if defined(CONFIG_PPC_BOOK3E)
  529. tophys(r26,r26)
  530. #endif
  531. cmplwi cr0,r7,1 /* flagged to stay where we are ? */
  532. bne 1f
  533. add r25,r25,r26
  534. 1: mr r3,r25
  535. bl relocate
  536. #if defined(CONFIG_PPC_BOOK3E)
  537. /* IVPR needs to be set after relocation. */
  538. bl init_core_book3e
  539. #endif
  540. #endif
  541. /*
  542. * We need to run with _stext at physical address PHYSICAL_START.
  543. * This will leave some code in the first 256B of
  544. * real memory, which are reserved for software use.
  545. *
  546. * Note: This process overwrites the OF exception vectors.
  547. */
  548. li r3,0 /* target addr */
  549. #ifdef CONFIG_PPC_BOOK3E
  550. tovirt(r3,r3) /* on booke, we already run at PAGE_OFFSET */
  551. #endif
  552. mr. r4,r26 /* In some cases the loader may */
  553. #if defined(CONFIG_PPC_BOOK3E)
  554. tovirt(r4,r4)
  555. #endif
  556. beq 9f /* have already put us at zero */
  557. li r6,0x100 /* Start offset, the first 0x100 */
  558. /* bytes were copied earlier. */
  559. #ifdef CONFIG_RELOCATABLE
  560. /*
  561. * Check if the kernel has to be running as relocatable kernel based on the
  562. * variable __run_at_load, if it is set the kernel is treated as relocatable
  563. * kernel, otherwise it will be moved to PHYSICAL_START
  564. */
  565. #if defined(CONFIG_PPC_BOOK3E)
  566. tovirt(r26,r26) /* on booke, we already run at PAGE_OFFSET */
  567. #endif
  568. lwz r7,(FIXED_SYMBOL_ABS_ADDR(__run_at_load))(r26)
  569. cmplwi cr0,r7,1
  570. bne 3f
  571. #ifdef CONFIG_PPC_BOOK3E
  572. LOAD_REG_ADDR(r5, __end_interrupts)
  573. LOAD_REG_ADDR(r11, _stext)
  574. sub r5,r5,r11
  575. #else
  576. /* just copy interrupts */
  577. LOAD_REG_IMMEDIATE_SYM(r5, r11, FIXED_SYMBOL_ABS_ADDR(__end_interrupts))
  578. #endif
  579. b 5f
  580. 3:
  581. #endif
  582. /* # bytes of memory to copy */
  583. lis r5,(ABS_ADDR(copy_to_here))@ha
  584. addi r5,r5,(ABS_ADDR(copy_to_here))@l
  585. bl copy_and_flush /* copy the first n bytes */
  586. /* this includes the code being */
  587. /* executed here. */
  588. /* Jump to the copy of this code that we just made */
  589. addis r8,r3,(ABS_ADDR(4f))@ha
  590. addi r12,r8,(ABS_ADDR(4f))@l
  591. mtctr r12
  592. bctr
  593. .balign 8
  594. p_end: .8byte _end - copy_to_here
  595. 4:
  596. /*
  597. * Now copy the rest of the kernel up to _end, add
  598. * _end - copy_to_here to the copy limit and run again.
  599. */
  600. addis r8,r26,(ABS_ADDR(p_end))@ha
  601. ld r8,(ABS_ADDR(p_end))@l(r8)
  602. add r5,r5,r8
  603. 5: bl copy_and_flush /* copy the rest */
  604. 9: b start_here_multiplatform
  605. /*
  606. * Copy routine used to copy the kernel to start at physical address 0
  607. * and flush and invalidate the caches as needed.
  608. * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
  609. * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
  610. *
  611. * Note: this routine *only* clobbers r0, r6 and lr
  612. */
  613. _GLOBAL(copy_and_flush)
  614. addi r5,r5,-8
  615. addi r6,r6,-8
  616. 4: li r0,8 /* Use the smallest common */
  617. /* denominator cache line */
  618. /* size. This results in */
  619. /* extra cache line flushes */
  620. /* but operation is correct. */
  621. /* Can't get cache line size */
  622. /* from NACA as it is being */
  623. /* moved too. */
  624. mtctr r0 /* put # words/line in ctr */
  625. 3: addi r6,r6,8 /* copy a cache line */
  626. ldx r0,r6,r4
  627. stdx r0,r6,r3
  628. bdnz 3b
  629. dcbst r6,r3 /* write it to memory */
  630. sync
  631. icbi r6,r3 /* flush the icache line */
  632. cmpld 0,r6,r5
  633. blt 4b
  634. sync
  635. addi r5,r5,8
  636. addi r6,r6,8
  637. isync
  638. blr
  639. .align 8
  640. copy_to_here:
  641. #ifdef CONFIG_SMP
  642. #ifdef CONFIG_PPC_PMAC
  643. /*
  644. * On PowerMac, secondary processors starts from the reset vector, which
  645. * is temporarily turned into a call to one of the functions below.
  646. */
  647. .section ".text";
  648. .align 2 ;
  649. .globl __secondary_start_pmac_0
  650. __secondary_start_pmac_0:
  651. /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
  652. li r24,0
  653. b 1f
  654. li r24,1
  655. b 1f
  656. li r24,2
  657. b 1f
  658. li r24,3
  659. 1:
  660. _GLOBAL(pmac_secondary_start)
  661. /* turn on 64-bit mode */
  662. bl enable_64b_mode
  663. li r0,0
  664. mfspr r3,SPRN_HID4
  665. rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */
  666. sync
  667. mtspr SPRN_HID4,r3
  668. isync
  669. sync
  670. slbia
  671. /* get TOC pointer (real address) */
  672. bl relative_toc
  673. tovirt(r2,r2)
  674. /* Copy some CPU settings from CPU 0 */
  675. bl __restore_cpu_ppc970
  676. /* pSeries do that early though I don't think we really need it */
  677. mfmsr r3
  678. ori r3,r3,MSR_RI
  679. mtmsrd r3 /* RI on */
  680. /* Set up a paca value for this processor. */
  681. LOAD_REG_ADDR(r4,paca_ptrs) /* Load paca pointer */
  682. ld r4,0(r4) /* Get base vaddr of paca_ptrs array */
  683. sldi r5,r24,3 /* get paca_ptrs[] index from cpu id */
  684. ldx r13,r5,r4 /* r13 = paca_ptrs[cpu id] */
  685. SET_PACA(r13) /* Save vaddr of paca in an SPRG*/
  686. /* Mark interrupts soft and hard disabled (they might be enabled
  687. * in the PACA when doing hotplug)
  688. */
  689. li r0,IRQS_DISABLED
  690. stb r0,PACAIRQSOFTMASK(r13)
  691. li r0,PACA_IRQ_HARD_DIS
  692. stb r0,PACAIRQHAPPENED(r13)
  693. /* Create a temp kernel stack for use before relocation is on. */
  694. ld r1,PACAEMERGSP(r13)
  695. subi r1,r1,STACK_FRAME_OVERHEAD
  696. b __secondary_start
  697. #endif /* CONFIG_PPC_PMAC */
  698. /*
  699. * This function is called after the master CPU has released the
  700. * secondary processors. The execution environment is relocation off.
  701. * The paca for this processor has the following fields initialized at
  702. * this point:
  703. * 1. Processor number
  704. * 2. Segment table pointer (virtual address)
  705. * On entry the following are set:
  706. * r1 = stack pointer (real addr of temp stack)
  707. * r24 = cpu# (in Linux terms)
  708. * r13 = paca virtual address
  709. * SPRG_PACA = paca virtual address
  710. */
  711. .section ".text";
  712. .align 2 ;
  713. .globl __secondary_start
  714. __secondary_start:
  715. /* Set thread priority to MEDIUM */
  716. HMT_MEDIUM
  717. /*
  718. * Do early setup for this CPU, in particular initialising the MMU so we
  719. * can turn it on below. This is a call to C, which is OK, we're still
  720. * running on the emergency stack.
  721. */
  722. bl early_setup_secondary
  723. /*
  724. * The primary has initialized our kernel stack for us in the paca, grab
  725. * it and put it in r1. We must *not* use it until we turn on the MMU
  726. * below, because it may not be inside the RMO.
  727. */
  728. ld r1, PACAKSAVE(r13)
  729. /* Clear backchain so we get nice backtraces */
  730. li r7,0
  731. mtlr r7
  732. /* Mark interrupts soft and hard disabled (they might be enabled
  733. * in the PACA when doing hotplug)
  734. */
  735. li r7,IRQS_DISABLED
  736. stb r7,PACAIRQSOFTMASK(r13)
  737. li r0,PACA_IRQ_HARD_DIS
  738. stb r0,PACAIRQHAPPENED(r13)
  739. /* enable MMU and jump to start_secondary */
  740. LOAD_REG_ADDR(r3, start_secondary_prolog)
  741. LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
  742. mtspr SPRN_SRR0,r3
  743. mtspr SPRN_SRR1,r4
  744. RFI
  745. b . /* prevent speculative execution */
  746. /*
  747. * Running with relocation on at this point. All we want to do is
  748. * zero the stack back-chain pointer and get the TOC virtual address
  749. * before going into C code.
  750. */
  751. start_secondary_prolog:
  752. ld r2,PACATOC(r13)
  753. li r3,0
  754. std r3,0(r1) /* Zero the stack frame pointer */
  755. bl start_secondary
  756. b .
  757. /*
  758. * Reset stack pointer and call start_secondary
  759. * to continue with online operation when woken up
  760. * from cede in cpu offline.
  761. */
  762. _GLOBAL(start_secondary_resume)
  763. ld r1,PACAKSAVE(r13) /* Reload kernel stack pointer */
  764. li r3,0
  765. std r3,0(r1) /* Zero the stack frame pointer */
  766. bl start_secondary
  767. b .
  768. #endif
  769. /*
  770. * This subroutine clobbers r11 and r12
  771. */
  772. enable_64b_mode:
  773. mfmsr r11 /* grab the current MSR */
  774. #ifdef CONFIG_PPC_BOOK3E
  775. oris r11,r11,0x8000 /* CM bit set, we'll set ICM later */
  776. mtmsr r11
  777. #else /* CONFIG_PPC_BOOK3E */
  778. li r12,(MSR_64BIT | MSR_ISF)@highest
  779. sldi r12,r12,48
  780. or r11,r11,r12
  781. mtmsrd r11
  782. isync
  783. #endif
  784. blr
  785. /*
  786. * This puts the TOC pointer into r2, offset by 0x8000 (as expected
  787. * by the toolchain). It computes the correct value for wherever we
  788. * are running at the moment, using position-independent code.
  789. *
  790. * Note: The compiler constructs pointers using offsets from the
  791. * TOC in -mcmodel=medium mode. After we relocate to 0 but before
  792. * the MMU is on we need our TOC to be a virtual address otherwise
  793. * these pointers will be real addresses which may get stored and
  794. * accessed later with the MMU on. We use tovirt() at the call
  795. * sites to handle this.
  796. */
  797. _GLOBAL(relative_toc)
  798. mflr r0
  799. bcl 20,31,$+4
  800. 0: mflr r11
  801. ld r2,(p_toc - 0b)(r11)
  802. add r2,r2,r11
  803. mtlr r0
  804. blr
  805. .balign 8
  806. p_toc: .8byte __toc_start + 0x8000 - 0b
  807. /*
  808. * This is where the main kernel code starts.
  809. */
  810. __REF
  811. start_here_multiplatform:
  812. /* set up the TOC */
  813. bl relative_toc
  814. tovirt(r2,r2)
  815. /* Clear out the BSS. It may have been done in prom_init,
  816. * already but that's irrelevant since prom_init will soon
  817. * be detached from the kernel completely. Besides, we need
  818. * to clear it now for kexec-style entry.
  819. */
  820. LOAD_REG_ADDR(r11,__bss_stop)
  821. LOAD_REG_ADDR(r8,__bss_start)
  822. sub r11,r11,r8 /* bss size */
  823. addi r11,r11,7 /* round up to an even double word */
  824. srdi. r11,r11,3 /* shift right by 3 */
  825. beq 4f
  826. addi r8,r8,-8
  827. li r0,0
  828. mtctr r11 /* zero this many doublewords */
  829. 3: stdu r0,8(r8)
  830. bdnz 3b
  831. 4:
  832. #ifdef CONFIG_PPC_EARLY_DEBUG_OPAL
  833. /* Setup OPAL entry */
  834. LOAD_REG_ADDR(r11, opal)
  835. std r28,0(r11);
  836. std r29,8(r11);
  837. #endif
  838. #ifndef CONFIG_PPC_BOOK3E
  839. mfmsr r6
  840. ori r6,r6,MSR_RI
  841. mtmsrd r6 /* RI on */
  842. #endif
  843. #ifdef CONFIG_RELOCATABLE
  844. /* Save the physical address we're running at in kernstart_addr */
  845. LOAD_REG_ADDR(r4, kernstart_addr)
  846. clrldi r0,r25,2
  847. std r0,0(r4)
  848. #endif
  849. /* The following gets the stack set up with the regs */
  850. /* pointing to the real addr of the kernel stack. This is */
  851. /* all done to support the C function call below which sets */
  852. /* up the htab. This is done because we have relocated the */
  853. /* kernel but are still running in real mode. */
  854. LOAD_REG_ADDR(r3,init_thread_union)
  855. /* set up a stack pointer */
  856. LOAD_REG_IMMEDIATE(r1,THREAD_SIZE)
  857. add r1,r3,r1
  858. li r0,0
  859. stdu r0,-STACK_FRAME_OVERHEAD(r1)
  860. /*
  861. * Do very early kernel initializations, including initial hash table
  862. * and SLB setup before we turn on relocation.
  863. */
  864. /* Restore parameters passed from prom_init/kexec */
  865. mr r3,r31
  866. LOAD_REG_ADDR(r12, DOTSYM(early_setup))
  867. mtctr r12
  868. bctrl /* also sets r13 and SPRG_PACA */
  869. LOAD_REG_ADDR(r3, start_here_common)
  870. ld r4,PACAKMSR(r13)
  871. mtspr SPRN_SRR0,r3
  872. mtspr SPRN_SRR1,r4
  873. RFI
  874. b . /* prevent speculative execution */
  875. /* This is where all platforms converge execution */
  876. start_here_common:
  877. /* relocation is on at this point */
  878. std r1,PACAKSAVE(r13)
  879. /* Load the TOC (virtual address) */
  880. ld r2,PACATOC(r13)
  881. /* Mark interrupts soft and hard disabled (they might be enabled
  882. * in the PACA when doing hotplug)
  883. */
  884. li r0,IRQS_DISABLED
  885. stb r0,PACAIRQSOFTMASK(r13)
  886. li r0,PACA_IRQ_HARD_DIS
  887. stb r0,PACAIRQHAPPENED(r13)
  888. /* Generic kernel entry */
  889. bl start_kernel
  890. /* Not reached */
  891. trap
  892. EMIT_BUG_ENTRY 0b, __FILE__, __LINE__, 0
  893. .previous
  894. /*
  895. * We put a few things here that have to be page-aligned.
  896. * This stuff goes at the beginning of the bss, which is page-aligned.
  897. */
  898. .section ".bss"
  899. /*
  900. * pgd dir should be aligned to PGD_TABLE_SIZE which is 64K.
  901. * We will need to find a better way to fix this
  902. */
  903. .align 16
  904. .globl swapper_pg_dir
  905. swapper_pg_dir:
  906. .space PGD_TABLE_SIZE
  907. .globl empty_zero_page
  908. empty_zero_page:
  909. .space PAGE_SIZE
  910. EXPORT_SYMBOL(empty_zero_page)