/arch/powerpc/kernel/setup_32.c

http://github.com/mirrors/linux · C · 228 lines · 163 code · 37 blank · 28 comment · 12 complexity · 153080c793e58af56e2edf0f9f4e23ee MD5 · raw file

  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Common prep/pmac/chrp boot and setup code.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/string.h>
  7. #include <linux/sched.h>
  8. #include <linux/init.h>
  9. #include <linux/kernel.h>
  10. #include <linux/reboot.h>
  11. #include <linux/delay.h>
  12. #include <linux/initrd.h>
  13. #include <linux/tty.h>
  14. #include <linux/seq_file.h>
  15. #include <linux/root_dev.h>
  16. #include <linux/cpu.h>
  17. #include <linux/console.h>
  18. #include <linux/memblock.h>
  19. #include <linux/export.h>
  20. #include <linux/nvram.h>
  21. #include <asm/io.h>
  22. #include <asm/prom.h>
  23. #include <asm/processor.h>
  24. #include <asm/pgtable.h>
  25. #include <asm/setup.h>
  26. #include <asm/smp.h>
  27. #include <asm/elf.h>
  28. #include <asm/cputable.h>
  29. #include <asm/bootx.h>
  30. #include <asm/btext.h>
  31. #include <asm/machdep.h>
  32. #include <linux/uaccess.h>
  33. #include <asm/pmac_feature.h>
  34. #include <asm/sections.h>
  35. #include <asm/nvram.h>
  36. #include <asm/xmon.h>
  37. #include <asm/time.h>
  38. #include <asm/serial.h>
  39. #include <asm/udbg.h>
  40. #include <asm/code-patching.h>
  41. #include <asm/cpu_has_feature.h>
  42. #include <asm/asm-prototypes.h>
  43. #include <asm/kdump.h>
  44. #include <asm/feature-fixups.h>
  45. #include <asm/early_ioremap.h>
  46. #include "setup.h"
  47. #define DBG(fmt...)
  48. extern void bootx_init(unsigned long r4, unsigned long phys);
  49. int boot_cpuid_phys;
  50. EXPORT_SYMBOL_GPL(boot_cpuid_phys);
  51. int smp_hw_index[NR_CPUS];
  52. EXPORT_SYMBOL(smp_hw_index);
  53. unsigned int DMA_MODE_READ;
  54. unsigned int DMA_MODE_WRITE;
  55. EXPORT_SYMBOL(DMA_MODE_READ);
  56. EXPORT_SYMBOL(DMA_MODE_WRITE);
  57. /*
  58. * This is run before start_kernel(), the kernel has been relocated
  59. * and we are running with enough of the MMU enabled to have our
  60. * proper kernel virtual addresses
  61. *
  62. * We do the initial parsing of the flat device-tree and prepares
  63. * for the MMU to be fully initialized.
  64. */
  65. notrace void __init machine_init(u64 dt_ptr)
  66. {
  67. unsigned int *addr = (unsigned int *)patch_site_addr(&patch__memset_nocache);
  68. unsigned long insn;
  69. /* Configure static keys first, now that we're relocated. */
  70. setup_feature_keys();
  71. early_ioremap_setup();
  72. /* Enable early debugging if any specified (see udbg.h) */
  73. udbg_early_init();
  74. patch_instruction_site(&patch__memcpy_nocache, PPC_INST_NOP);
  75. insn = create_cond_branch(addr, branch_target(addr), 0x820000);
  76. patch_instruction(addr, insn); /* replace b by bne cr0 */
  77. /* Do some early initialization based on the flat device tree */
  78. early_init_devtree(__va(dt_ptr));
  79. early_init_mmu();
  80. setup_kdump_trampoline();
  81. }
  82. /* Checks "l2cr=xxxx" command-line option */
  83. static int __init ppc_setup_l2cr(char *str)
  84. {
  85. if (cpu_has_feature(CPU_FTR_L2CR)) {
  86. unsigned long val = simple_strtoul(str, NULL, 0);
  87. printk(KERN_INFO "l2cr set to %lx\n", val);
  88. _set_L2CR(0); /* force invalidate by disable cache */
  89. _set_L2CR(val); /* and enable it */
  90. }
  91. return 1;
  92. }
  93. __setup("l2cr=", ppc_setup_l2cr);
  94. /* Checks "l3cr=xxxx" command-line option */
  95. static int __init ppc_setup_l3cr(char *str)
  96. {
  97. if (cpu_has_feature(CPU_FTR_L3CR)) {
  98. unsigned long val = simple_strtoul(str, NULL, 0);
  99. printk(KERN_INFO "l3cr set to %lx\n", val);
  100. _set_L3CR(val); /* and enable it */
  101. }
  102. return 1;
  103. }
  104. __setup("l3cr=", ppc_setup_l3cr);
  105. static int __init ppc_init(void)
  106. {
  107. /* clear the progress line */
  108. if (ppc_md.progress)
  109. ppc_md.progress(" ", 0xffff);
  110. /* call platform init */
  111. if (ppc_md.init != NULL) {
  112. ppc_md.init();
  113. }
  114. return 0;
  115. }
  116. arch_initcall(ppc_init);
  117. static void *__init alloc_stack(void)
  118. {
  119. void *ptr = memblock_alloc(THREAD_SIZE, THREAD_ALIGN);
  120. if (!ptr)
  121. panic("cannot allocate %d bytes for stack at %pS\n",
  122. THREAD_SIZE, (void *)_RET_IP_);
  123. return ptr;
  124. }
  125. void __init irqstack_early_init(void)
  126. {
  127. unsigned int i;
  128. if (IS_ENABLED(CONFIG_VMAP_STACK))
  129. return;
  130. /* interrupt stacks must be in lowmem, we get that for free on ppc32
  131. * as the memblock is limited to lowmem by default */
  132. for_each_possible_cpu(i) {
  133. softirq_ctx[i] = alloc_stack();
  134. hardirq_ctx[i] = alloc_stack();
  135. }
  136. }
  137. #ifdef CONFIG_VMAP_STACK
  138. void *emergency_ctx[NR_CPUS] __ro_after_init;
  139. void __init emergency_stack_init(void)
  140. {
  141. unsigned int i;
  142. for_each_possible_cpu(i)
  143. emergency_ctx[i] = alloc_stack();
  144. }
  145. #endif
  146. #if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
  147. void __init exc_lvl_early_init(void)
  148. {
  149. unsigned int i, hw_cpu;
  150. /* interrupt stacks must be in lowmem, we get that for free on ppc32
  151. * as the memblock is limited to lowmem by MEMBLOCK_REAL_LIMIT */
  152. for_each_possible_cpu(i) {
  153. #ifdef CONFIG_SMP
  154. hw_cpu = get_hard_smp_processor_id(i);
  155. #else
  156. hw_cpu = 0;
  157. #endif
  158. critirq_ctx[hw_cpu] = alloc_stack();
  159. #ifdef CONFIG_BOOKE
  160. dbgirq_ctx[hw_cpu] = alloc_stack();
  161. mcheckirq_ctx[hw_cpu] = alloc_stack();
  162. #endif
  163. }
  164. }
  165. #endif
  166. void __init setup_power_save(void)
  167. {
  168. #ifdef CONFIG_PPC_BOOK3S_32
  169. if (cpu_has_feature(CPU_FTR_CAN_DOZE) ||
  170. cpu_has_feature(CPU_FTR_CAN_NAP))
  171. ppc_md.power_save = ppc6xx_idle;
  172. #endif
  173. #ifdef CONFIG_E500
  174. if (cpu_has_feature(CPU_FTR_CAN_DOZE) ||
  175. cpu_has_feature(CPU_FTR_CAN_NAP))
  176. ppc_md.power_save = e500_idle;
  177. #endif
  178. }
  179. __init void initialize_cache_info(void)
  180. {
  181. /*
  182. * Set cache line size based on type of cpu as a default.
  183. * Systems with OF can look in the properties on the cpu node(s)
  184. * for a possibly more accurate value.
  185. */
  186. dcache_bsize = cur_cpu_spec->dcache_bsize;
  187. icache_bsize = cur_cpu_spec->icache_bsize;
  188. ucache_bsize = 0;
  189. if (IS_ENABLED(CONFIG_PPC_BOOK3S_601) || IS_ENABLED(CONFIG_E200))
  190. ucache_bsize = icache_bsize = dcache_bsize;
  191. }