/arch/powerpc/kernel/head_44x.S

http://github.com/mirrors/linux · Assembly · 1275 lines · 648 code · 196 blank · 431 comment · 0 complexity · fd519b388e9b1fc660cf403292a45297 MD5 · raw file

  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * Kernel execution entry point code.
  4. *
  5. * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
  6. * Initial PowerPC version.
  7. * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
  8. * Rewritten for PReP
  9. * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
  10. * Low-level exception handers, MMU support, and rewrite.
  11. * Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
  12. * PowerPC 8xx modifications.
  13. * Copyright (c) 1998-1999 TiVo, Inc.
  14. * PowerPC 403GCX modifications.
  15. * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
  16. * PowerPC 403GCX/405GP modifications.
  17. * Copyright 2000 MontaVista Software Inc.
  18. * PPC405 modifications
  19. * PowerPC 403GCX/405GP modifications.
  20. * Author: MontaVista Software, Inc.
  21. * frank_rowand@mvista.com or source@mvista.com
  22. * debbie_chu@mvista.com
  23. * Copyright 2002-2005 MontaVista Software, Inc.
  24. * PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org>
  25. */
  26. #include <linux/init.h>
  27. #include <asm/processor.h>
  28. #include <asm/page.h>
  29. #include <asm/mmu.h>
  30. #include <asm/pgtable.h>
  31. #include <asm/cputable.h>
  32. #include <asm/thread_info.h>
  33. #include <asm/ppc_asm.h>
  34. #include <asm/asm-offsets.h>
  35. #include <asm/ptrace.h>
  36. #include <asm/synch.h>
  37. #include <asm/export.h>
  38. #include <asm/code-patching-asm.h>
  39. #include "head_booke.h"
  40. /* As with the other PowerPC ports, it is expected that when code
  41. * execution begins here, the following registers contain valid, yet
  42. * optional, information:
  43. *
  44. * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
  45. * r4 - Starting address of the init RAM disk
  46. * r5 - Ending address of the init RAM disk
  47. * r6 - Start of kernel command line string (e.g. "mem=128")
  48. * r7 - End of kernel command line string
  49. *
  50. */
  51. __HEAD
  52. _ENTRY(_stext);
  53. _ENTRY(_start);
  54. /*
  55. * Reserve a word at a fixed location to store the address
  56. * of abatron_pteptrs
  57. */
  58. nop
  59. mr r31,r3 /* save device tree ptr */
  60. li r24,0 /* CPU number */
  61. #ifdef CONFIG_RELOCATABLE
  62. /*
  63. * Relocate ourselves to the current runtime address.
  64. * This is called only by the Boot CPU.
  65. * "relocate" is called with our current runtime virutal
  66. * address.
  67. * r21 will be loaded with the physical runtime address of _stext
  68. */
  69. bl 0f /* Get our runtime address */
  70. 0: mflr r21 /* Make it accessible */
  71. addis r21,r21,(_stext - 0b)@ha
  72. addi r21,r21,(_stext - 0b)@l /* Get our current runtime base */
  73. /*
  74. * We have the runtime (virutal) address of our base.
  75. * We calculate our shift of offset from a 256M page.
  76. * We could map the 256M page we belong to at PAGE_OFFSET and
  77. * get going from there.
  78. */
  79. lis r4,KERNELBASE@h
  80. ori r4,r4,KERNELBASE@l
  81. rlwinm r6,r21,0,4,31 /* r6 = PHYS_START % 256M */
  82. rlwinm r5,r4,0,4,31 /* r5 = KERNELBASE % 256M */
  83. subf r3,r5,r6 /* r3 = r6 - r5 */
  84. add r3,r4,r3 /* Required Virutal Address */
  85. bl relocate
  86. #endif
  87. bl init_cpu_state
  88. /*
  89. * This is where the main kernel code starts.
  90. */
  91. /* ptr to current */
  92. lis r2,init_task@h
  93. ori r2,r2,init_task@l
  94. /* ptr to current thread */
  95. addi r4,r2,THREAD /* init task's THREAD */
  96. mtspr SPRN_SPRG_THREAD,r4
  97. /* stack */
  98. lis r1,init_thread_union@h
  99. ori r1,r1,init_thread_union@l
  100. li r0,0
  101. stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
  102. bl early_init
  103. #ifdef CONFIG_RELOCATABLE
  104. /*
  105. * Relocatable kernel support based on processing of dynamic
  106. * relocation entries.
  107. *
  108. * r25 will contain RPN/ERPN for the start address of memory
  109. * r21 will contain the current offset of _stext
  110. */
  111. lis r3,kernstart_addr@ha
  112. la r3,kernstart_addr@l(r3)
  113. /*
  114. * Compute the kernstart_addr.
  115. * kernstart_addr => (r6,r8)
  116. * kernstart_addr & ~0xfffffff => (r6,r7)
  117. */
  118. rlwinm r6,r25,0,28,31 /* ERPN. Bits 32-35 of Address */
  119. rlwinm r7,r25,0,0,3 /* RPN - assuming 256 MB page size */
  120. rlwinm r8,r21,0,4,31 /* r8 = (_stext & 0xfffffff) */
  121. or r8,r7,r8 /* Compute the lower 32bit of kernstart_addr */
  122. /* Store kernstart_addr */
  123. stw r6,0(r3) /* higher 32bit */
  124. stw r8,4(r3) /* lower 32bit */
  125. /*
  126. * Compute the virt_phys_offset :
  127. * virt_phys_offset = stext.run - kernstart_addr
  128. *
  129. * stext.run = (KERNELBASE & ~0xfffffff) + (kernstart_addr & 0xfffffff)
  130. * When we relocate, we have :
  131. *
  132. * (kernstart_addr & 0xfffffff) = (stext.run & 0xfffffff)
  133. *
  134. * hence:
  135. * virt_phys_offset = (KERNELBASE & ~0xfffffff) - (kernstart_addr & ~0xfffffff)
  136. *
  137. */
  138. /* KERNELBASE&~0xfffffff => (r4,r5) */
  139. li r4, 0 /* higer 32bit */
  140. lis r5,KERNELBASE@h
  141. rlwinm r5,r5,0,0,3 /* Align to 256M, lower 32bit */
  142. /*
  143. * 64bit subtraction.
  144. */
  145. subfc r5,r7,r5
  146. subfe r4,r6,r4
  147. /* Store virt_phys_offset */
  148. lis r3,virt_phys_offset@ha
  149. la r3,virt_phys_offset@l(r3)
  150. stw r4,0(r3)
  151. stw r5,4(r3)
  152. #elif defined(CONFIG_DYNAMIC_MEMSTART)
  153. /*
  154. * Mapping based, page aligned dynamic kernel loading.
  155. *
  156. * r25 will contain RPN/ERPN for the start address of memory
  157. *
  158. * Add the difference between KERNELBASE and PAGE_OFFSET to the
  159. * start of physical memory to get kernstart_addr.
  160. */
  161. lis r3,kernstart_addr@ha
  162. la r3,kernstart_addr@l(r3)
  163. lis r4,KERNELBASE@h
  164. ori r4,r4,KERNELBASE@l
  165. lis r5,PAGE_OFFSET@h
  166. ori r5,r5,PAGE_OFFSET@l
  167. subf r4,r5,r4
  168. rlwinm r6,r25,0,28,31 /* ERPN */
  169. rlwinm r7,r25,0,0,3 /* RPN - assuming 256 MB page size */
  170. add r7,r7,r4
  171. stw r6,0(r3)
  172. stw r7,4(r3)
  173. #endif
  174. /*
  175. * Decide what sort of machine this is and initialize the MMU.
  176. */
  177. #ifdef CONFIG_KASAN
  178. bl kasan_early_init
  179. #endif
  180. li r3,0
  181. mr r4,r31
  182. bl machine_init
  183. bl MMU_init
  184. /* Setup PTE pointers for the Abatron bdiGDB */
  185. lis r6, swapper_pg_dir@h
  186. ori r6, r6, swapper_pg_dir@l
  187. lis r5, abatron_pteptrs@h
  188. ori r5, r5, abatron_pteptrs@l
  189. lis r4, KERNELBASE@h
  190. ori r4, r4, KERNELBASE@l
  191. stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */
  192. stw r6, 0(r5)
  193. /* Clear the Machine Check Syndrome Register */
  194. li r0,0
  195. mtspr SPRN_MCSR,r0
  196. /* Let's move on */
  197. lis r4,start_kernel@h
  198. ori r4,r4,start_kernel@l
  199. lis r3,MSR_KERNEL@h
  200. ori r3,r3,MSR_KERNEL@l
  201. mtspr SPRN_SRR0,r4
  202. mtspr SPRN_SRR1,r3
  203. rfi /* change context and jump to start_kernel */
  204. /*
  205. * Interrupt vector entry code
  206. *
  207. * The Book E MMUs are always on so we don't need to handle
  208. * interrupts in real mode as with previous PPC processors. In
  209. * this case we handle interrupts in the kernel virtual address
  210. * space.
  211. *
  212. * Interrupt vectors are dynamically placed relative to the
  213. * interrupt prefix as determined by the address of interrupt_base.
  214. * The interrupt vectors offsets are programmed using the labels
  215. * for each interrupt vector entry.
  216. *
  217. * Interrupt vectors must be aligned on a 16 byte boundary.
  218. * We align on a 32 byte cache line boundary for good measure.
  219. */
  220. interrupt_base:
  221. /* Critical Input Interrupt */
  222. CRITICAL_EXCEPTION(0x0100, CRITICAL, CriticalInput, unknown_exception)
  223. /* Machine Check Interrupt */
  224. CRITICAL_EXCEPTION(0x0200, MACHINE_CHECK, MachineCheck, \
  225. machine_check_exception)
  226. MCHECK_EXCEPTION(0x0210, MachineCheckA, machine_check_exception)
  227. /* Data Storage Interrupt */
  228. DATA_STORAGE_EXCEPTION
  229. /* Instruction Storage Interrupt */
  230. INSTRUCTION_STORAGE_EXCEPTION
  231. /* External Input Interrupt */
  232. EXCEPTION(0x0500, BOOKE_INTERRUPT_EXTERNAL, ExternalInput, \
  233. do_IRQ, EXC_XFER_LITE)
  234. /* Alignment Interrupt */
  235. ALIGNMENT_EXCEPTION
  236. /* Program Interrupt */
  237. PROGRAM_EXCEPTION
  238. /* Floating Point Unavailable Interrupt */
  239. #ifdef CONFIG_PPC_FPU
  240. FP_UNAVAILABLE_EXCEPTION
  241. #else
  242. EXCEPTION(0x2010, BOOKE_INTERRUPT_FP_UNAVAIL, \
  243. FloatingPointUnavailable, unknown_exception, EXC_XFER_STD)
  244. #endif
  245. /* System Call Interrupt */
  246. START_EXCEPTION(SystemCall)
  247. SYSCALL_ENTRY 0xc00 BOOKE_INTERRUPT_SYSCALL
  248. /* Auxiliary Processor Unavailable Interrupt */
  249. EXCEPTION(0x2020, BOOKE_INTERRUPT_AP_UNAVAIL, \
  250. AuxillaryProcessorUnavailable, unknown_exception, EXC_XFER_STD)
  251. /* Decrementer Interrupt */
  252. DECREMENTER_EXCEPTION
  253. /* Fixed Internal Timer Interrupt */
  254. /* TODO: Add FIT support */
  255. EXCEPTION(0x1010, BOOKE_INTERRUPT_FIT, FixedIntervalTimer, \
  256. unknown_exception, EXC_XFER_STD)
  257. /* Watchdog Timer Interrupt */
  258. /* TODO: Add watchdog support */
  259. #ifdef CONFIG_BOOKE_WDT
  260. CRITICAL_EXCEPTION(0x1020, WATCHDOG, WatchdogTimer, WatchdogException)
  261. #else
  262. CRITICAL_EXCEPTION(0x1020, WATCHDOG, WatchdogTimer, unknown_exception)
  263. #endif
  264. /* Data TLB Error Interrupt */
  265. START_EXCEPTION(DataTLBError44x)
  266. mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
  267. mtspr SPRN_SPRG_WSCRATCH1, r11
  268. mtspr SPRN_SPRG_WSCRATCH2, r12
  269. mtspr SPRN_SPRG_WSCRATCH3, r13
  270. mfcr r11
  271. mtspr SPRN_SPRG_WSCRATCH4, r11
  272. mfspr r10, SPRN_DEAR /* Get faulting address */
  273. /* If we are faulting a kernel address, we have to use the
  274. * kernel page tables.
  275. */
  276. lis r11, PAGE_OFFSET@h
  277. cmplw r10, r11
  278. blt+ 3f
  279. lis r11, swapper_pg_dir@h
  280. ori r11, r11, swapper_pg_dir@l
  281. mfspr r12,SPRN_MMUCR
  282. rlwinm r12,r12,0,0,23 /* Clear TID */
  283. b 4f
  284. /* Get the PGD for the current thread */
  285. 3:
  286. mfspr r11,SPRN_SPRG_THREAD
  287. lwz r11,PGDIR(r11)
  288. /* Load PID into MMUCR TID */
  289. mfspr r12,SPRN_MMUCR
  290. mfspr r13,SPRN_PID /* Get PID */
  291. rlwimi r12,r13,0,24,31 /* Set TID */
  292. 4:
  293. mtspr SPRN_MMUCR,r12
  294. /* Mask of required permission bits. Note that while we
  295. * do copy ESR:ST to _PAGE_RW position as trying to write
  296. * to an RO page is pretty common, we don't do it with
  297. * _PAGE_DIRTY. We could do it, but it's a fairly rare
  298. * event so I'd rather take the overhead when it happens
  299. * rather than adding an instruction here. We should measure
  300. * whether the whole thing is worth it in the first place
  301. * as we could avoid loading SPRN_ESR completely in the first
  302. * place...
  303. *
  304. * TODO: Is it worth doing that mfspr & rlwimi in the first
  305. * place or can we save a couple of instructions here ?
  306. */
  307. mfspr r12,SPRN_ESR
  308. li r13,_PAGE_PRESENT|_PAGE_ACCESSED
  309. rlwimi r13,r12,10,30,30
  310. /* Load the PTE */
  311. /* Compute pgdir/pmd offset */
  312. rlwinm r12, r10, PPC44x_PGD_OFF_SHIFT, PPC44x_PGD_OFF_MASK_BIT, 29
  313. lwzx r11, r12, r11 /* Get pgd/pmd entry */
  314. rlwinm. r12, r11, 0, 0, 20 /* Extract pt base address */
  315. beq 2f /* Bail if no table */
  316. /* Compute pte address */
  317. rlwimi r12, r10, PPC44x_PTE_ADD_SHIFT, PPC44x_PTE_ADD_MASK_BIT, 28
  318. lwz r11, 0(r12) /* Get high word of pte entry */
  319. lwz r12, 4(r12) /* Get low word of pte entry */
  320. lis r10,tlb_44x_index@ha
  321. andc. r13,r13,r12 /* Check permission */
  322. /* Load the next available TLB index */
  323. lwz r13,tlb_44x_index@l(r10)
  324. bne 2f /* Bail if permission mismach */
  325. /* Increment, rollover, and store TLB index */
  326. addi r13,r13,1
  327. patch_site 0f, patch__tlb_44x_hwater_D
  328. /* Compare with watermark (instruction gets patched) */
  329. 0: cmpwi 0,r13,1 /* reserve entries */
  330. ble 5f
  331. li r13,0
  332. 5:
  333. /* Store the next available TLB index */
  334. stw r13,tlb_44x_index@l(r10)
  335. /* Re-load the faulting address */
  336. mfspr r10,SPRN_DEAR
  337. /* Jump to common tlb load */
  338. b finish_tlb_load_44x
  339. 2:
  340. /* The bailout. Restore registers to pre-exception conditions
  341. * and call the heavyweights to help us out.
  342. */
  343. mfspr r11, SPRN_SPRG_RSCRATCH4
  344. mtcr r11
  345. mfspr r13, SPRN_SPRG_RSCRATCH3
  346. mfspr r12, SPRN_SPRG_RSCRATCH2
  347. mfspr r11, SPRN_SPRG_RSCRATCH1
  348. mfspr r10, SPRN_SPRG_RSCRATCH0
  349. b DataStorage
  350. /* Instruction TLB Error Interrupt */
  351. /*
  352. * Nearly the same as above, except we get our
  353. * information from different registers and bailout
  354. * to a different point.
  355. */
  356. START_EXCEPTION(InstructionTLBError44x)
  357. mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
  358. mtspr SPRN_SPRG_WSCRATCH1, r11
  359. mtspr SPRN_SPRG_WSCRATCH2, r12
  360. mtspr SPRN_SPRG_WSCRATCH3, r13
  361. mfcr r11
  362. mtspr SPRN_SPRG_WSCRATCH4, r11
  363. mfspr r10, SPRN_SRR0 /* Get faulting address */
  364. /* If we are faulting a kernel address, we have to use the
  365. * kernel page tables.
  366. */
  367. lis r11, PAGE_OFFSET@h
  368. cmplw r10, r11
  369. blt+ 3f
  370. lis r11, swapper_pg_dir@h
  371. ori r11, r11, swapper_pg_dir@l
  372. mfspr r12,SPRN_MMUCR
  373. rlwinm r12,r12,0,0,23 /* Clear TID */
  374. b 4f
  375. /* Get the PGD for the current thread */
  376. 3:
  377. mfspr r11,SPRN_SPRG_THREAD
  378. lwz r11,PGDIR(r11)
  379. /* Load PID into MMUCR TID */
  380. mfspr r12,SPRN_MMUCR
  381. mfspr r13,SPRN_PID /* Get PID */
  382. rlwimi r12,r13,0,24,31 /* Set TID */
  383. 4:
  384. mtspr SPRN_MMUCR,r12
  385. /* Make up the required permissions */
  386. li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
  387. /* Compute pgdir/pmd offset */
  388. rlwinm r12, r10, PPC44x_PGD_OFF_SHIFT, PPC44x_PGD_OFF_MASK_BIT, 29
  389. lwzx r11, r12, r11 /* Get pgd/pmd entry */
  390. rlwinm. r12, r11, 0, 0, 20 /* Extract pt base address */
  391. beq 2f /* Bail if no table */
  392. /* Compute pte address */
  393. rlwimi r12, r10, PPC44x_PTE_ADD_SHIFT, PPC44x_PTE_ADD_MASK_BIT, 28
  394. lwz r11, 0(r12) /* Get high word of pte entry */
  395. lwz r12, 4(r12) /* Get low word of pte entry */
  396. lis r10,tlb_44x_index@ha
  397. andc. r13,r13,r12 /* Check permission */
  398. /* Load the next available TLB index */
  399. lwz r13,tlb_44x_index@l(r10)
  400. bne 2f /* Bail if permission mismach */
  401. /* Increment, rollover, and store TLB index */
  402. addi r13,r13,1
  403. patch_site 0f, patch__tlb_44x_hwater_I
  404. /* Compare with watermark (instruction gets patched) */
  405. 0: cmpwi 0,r13,1 /* reserve entries */
  406. ble 5f
  407. li r13,0
  408. 5:
  409. /* Store the next available TLB index */
  410. stw r13,tlb_44x_index@l(r10)
  411. /* Re-load the faulting address */
  412. mfspr r10,SPRN_SRR0
  413. /* Jump to common TLB load point */
  414. b finish_tlb_load_44x
  415. 2:
  416. /* The bailout. Restore registers to pre-exception conditions
  417. * and call the heavyweights to help us out.
  418. */
  419. mfspr r11, SPRN_SPRG_RSCRATCH4
  420. mtcr r11
  421. mfspr r13, SPRN_SPRG_RSCRATCH3
  422. mfspr r12, SPRN_SPRG_RSCRATCH2
  423. mfspr r11, SPRN_SPRG_RSCRATCH1
  424. mfspr r10, SPRN_SPRG_RSCRATCH0
  425. b InstructionStorage
  426. /*
  427. * Both the instruction and data TLB miss get to this
  428. * point to load the TLB.
  429. * r10 - EA of fault
  430. * r11 - PTE high word value
  431. * r12 - PTE low word value
  432. * r13 - TLB index
  433. * MMUCR - loaded with proper value when we get here
  434. * Upon exit, we reload everything and RFI.
  435. */
  436. finish_tlb_load_44x:
  437. /* Combine RPN & ERPN an write WS 0 */
  438. rlwimi r11,r12,0,0,31-PAGE_SHIFT
  439. tlbwe r11,r13,PPC44x_TLB_XLAT
  440. /*
  441. * Create WS1. This is the faulting address (EPN),
  442. * page size, and valid flag.
  443. */
  444. li r11,PPC44x_TLB_VALID | PPC44x_TLBE_SIZE
  445. /* Insert valid and page size */
  446. rlwimi r10,r11,0,PPC44x_PTE_ADD_MASK_BIT,31
  447. tlbwe r10,r13,PPC44x_TLB_PAGEID /* Write PAGEID */
  448. /* And WS 2 */
  449. li r10,0xf85 /* Mask to apply from PTE */
  450. rlwimi r10,r12,29,30,30 /* DIRTY -> SW position */
  451. and r11,r12,r10 /* Mask PTE bits to keep */
  452. andi. r10,r12,_PAGE_USER /* User page ? */
  453. beq 1f /* nope, leave U bits empty */
  454. rlwimi r11,r11,3,26,28 /* yes, copy S bits to U */
  455. 1: tlbwe r11,r13,PPC44x_TLB_ATTRIB /* Write ATTRIB */
  456. /* Done...restore registers and get out of here.
  457. */
  458. mfspr r11, SPRN_SPRG_RSCRATCH4
  459. mtcr r11
  460. mfspr r13, SPRN_SPRG_RSCRATCH3
  461. mfspr r12, SPRN_SPRG_RSCRATCH2
  462. mfspr r11, SPRN_SPRG_RSCRATCH1
  463. mfspr r10, SPRN_SPRG_RSCRATCH0
  464. rfi /* Force context change */
  465. /* TLB error interrupts for 476
  466. */
  467. #ifdef CONFIG_PPC_47x
  468. START_EXCEPTION(DataTLBError47x)
  469. mtspr SPRN_SPRG_WSCRATCH0,r10 /* Save some working registers */
  470. mtspr SPRN_SPRG_WSCRATCH1,r11
  471. mtspr SPRN_SPRG_WSCRATCH2,r12
  472. mtspr SPRN_SPRG_WSCRATCH3,r13
  473. mfcr r11
  474. mtspr SPRN_SPRG_WSCRATCH4,r11
  475. mfspr r10,SPRN_DEAR /* Get faulting address */
  476. /* If we are faulting a kernel address, we have to use the
  477. * kernel page tables.
  478. */
  479. lis r11,PAGE_OFFSET@h
  480. cmplw cr0,r10,r11
  481. blt+ 3f
  482. lis r11,swapper_pg_dir@h
  483. ori r11,r11, swapper_pg_dir@l
  484. li r12,0 /* MMUCR = 0 */
  485. b 4f
  486. /* Get the PGD for the current thread and setup MMUCR */
  487. 3: mfspr r11,SPRN_SPRG3
  488. lwz r11,PGDIR(r11)
  489. mfspr r12,SPRN_PID /* Get PID */
  490. 4: mtspr SPRN_MMUCR,r12 /* Set MMUCR */
  491. /* Mask of required permission bits. Note that while we
  492. * do copy ESR:ST to _PAGE_RW position as trying to write
  493. * to an RO page is pretty common, we don't do it with
  494. * _PAGE_DIRTY. We could do it, but it's a fairly rare
  495. * event so I'd rather take the overhead when it happens
  496. * rather than adding an instruction here. We should measure
  497. * whether the whole thing is worth it in the first place
  498. * as we could avoid loading SPRN_ESR completely in the first
  499. * place...
  500. *
  501. * TODO: Is it worth doing that mfspr & rlwimi in the first
  502. * place or can we save a couple of instructions here ?
  503. */
  504. mfspr r12,SPRN_ESR
  505. li r13,_PAGE_PRESENT|_PAGE_ACCESSED
  506. rlwimi r13,r12,10,30,30
  507. /* Load the PTE */
  508. /* Compute pgdir/pmd offset */
  509. rlwinm r12,r10,PPC44x_PGD_OFF_SHIFT,PPC44x_PGD_OFF_MASK_BIT,29
  510. lwzx r11,r12,r11 /* Get pgd/pmd entry */
  511. /* Word 0 is EPN,V,TS,DSIZ */
  512. li r12,PPC47x_TLB0_VALID | PPC47x_TLBE_SIZE
  513. rlwimi r10,r12,0,32-PAGE_SHIFT,31 /* Insert valid and page size*/
  514. li r12,0
  515. tlbwe r10,r12,0
  516. /* XXX can we do better ? Need to make sure tlbwe has established
  517. * latch V bit in MMUCR0 before the PTE is loaded further down */
  518. #ifdef CONFIG_SMP
  519. isync
  520. #endif
  521. rlwinm. r12,r11,0,0,20 /* Extract pt base address */
  522. /* Compute pte address */
  523. rlwimi r12,r10,PPC44x_PTE_ADD_SHIFT,PPC44x_PTE_ADD_MASK_BIT,28
  524. beq 2f /* Bail if no table */
  525. lwz r11,0(r12) /* Get high word of pte entry */
  526. /* XXX can we do better ? maybe insert a known 0 bit from r11 into the
  527. * bottom of r12 to create a data dependency... We can also use r10
  528. * as destination nowadays
  529. */
  530. #ifdef CONFIG_SMP
  531. lwsync
  532. #endif
  533. lwz r12,4(r12) /* Get low word of pte entry */
  534. andc. r13,r13,r12 /* Check permission */
  535. /* Jump to common tlb load */
  536. beq finish_tlb_load_47x
  537. 2: /* The bailout. Restore registers to pre-exception conditions
  538. * and call the heavyweights to help us out.
  539. */
  540. mfspr r11,SPRN_SPRG_RSCRATCH4
  541. mtcr r11
  542. mfspr r13,SPRN_SPRG_RSCRATCH3
  543. mfspr r12,SPRN_SPRG_RSCRATCH2
  544. mfspr r11,SPRN_SPRG_RSCRATCH1
  545. mfspr r10,SPRN_SPRG_RSCRATCH0
  546. b DataStorage
  547. /* Instruction TLB Error Interrupt */
  548. /*
  549. * Nearly the same as above, except we get our
  550. * information from different registers and bailout
  551. * to a different point.
  552. */
  553. START_EXCEPTION(InstructionTLBError47x)
  554. mtspr SPRN_SPRG_WSCRATCH0,r10 /* Save some working registers */
  555. mtspr SPRN_SPRG_WSCRATCH1,r11
  556. mtspr SPRN_SPRG_WSCRATCH2,r12
  557. mtspr SPRN_SPRG_WSCRATCH3,r13
  558. mfcr r11
  559. mtspr SPRN_SPRG_WSCRATCH4,r11
  560. mfspr r10,SPRN_SRR0 /* Get faulting address */
  561. /* If we are faulting a kernel address, we have to use the
  562. * kernel page tables.
  563. */
  564. lis r11,PAGE_OFFSET@h
  565. cmplw cr0,r10,r11
  566. blt+ 3f
  567. lis r11,swapper_pg_dir@h
  568. ori r11,r11, swapper_pg_dir@l
  569. li r12,0 /* MMUCR = 0 */
  570. b 4f
  571. /* Get the PGD for the current thread and setup MMUCR */
  572. 3: mfspr r11,SPRN_SPRG_THREAD
  573. lwz r11,PGDIR(r11)
  574. mfspr r12,SPRN_PID /* Get PID */
  575. 4: mtspr SPRN_MMUCR,r12 /* Set MMUCR */
  576. /* Make up the required permissions */
  577. li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
  578. /* Load PTE */
  579. /* Compute pgdir/pmd offset */
  580. rlwinm r12,r10,PPC44x_PGD_OFF_SHIFT,PPC44x_PGD_OFF_MASK_BIT,29
  581. lwzx r11,r12,r11 /* Get pgd/pmd entry */
  582. /* Word 0 is EPN,V,TS,DSIZ */
  583. li r12,PPC47x_TLB0_VALID | PPC47x_TLBE_SIZE
  584. rlwimi r10,r12,0,32-PAGE_SHIFT,31 /* Insert valid and page size*/
  585. li r12,0
  586. tlbwe r10,r12,0
  587. /* XXX can we do better ? Need to make sure tlbwe has established
  588. * latch V bit in MMUCR0 before the PTE is loaded further down */
  589. #ifdef CONFIG_SMP
  590. isync
  591. #endif
  592. rlwinm. r12,r11,0,0,20 /* Extract pt base address */
  593. /* Compute pte address */
  594. rlwimi r12,r10,PPC44x_PTE_ADD_SHIFT,PPC44x_PTE_ADD_MASK_BIT,28
  595. beq 2f /* Bail if no table */
  596. lwz r11,0(r12) /* Get high word of pte entry */
  597. /* XXX can we do better ? maybe insert a known 0 bit from r11 into the
  598. * bottom of r12 to create a data dependency... We can also use r10
  599. * as destination nowadays
  600. */
  601. #ifdef CONFIG_SMP
  602. lwsync
  603. #endif
  604. lwz r12,4(r12) /* Get low word of pte entry */
  605. andc. r13,r13,r12 /* Check permission */
  606. /* Jump to common TLB load point */
  607. beq finish_tlb_load_47x
  608. 2: /* The bailout. Restore registers to pre-exception conditions
  609. * and call the heavyweights to help us out.
  610. */
  611. mfspr r11, SPRN_SPRG_RSCRATCH4
  612. mtcr r11
  613. mfspr r13, SPRN_SPRG_RSCRATCH3
  614. mfspr r12, SPRN_SPRG_RSCRATCH2
  615. mfspr r11, SPRN_SPRG_RSCRATCH1
  616. mfspr r10, SPRN_SPRG_RSCRATCH0
  617. b InstructionStorage
  618. /*
  619. * Both the instruction and data TLB miss get to this
  620. * point to load the TLB.
  621. * r10 - free to use
  622. * r11 - PTE high word value
  623. * r12 - PTE low word value
  624. * r13 - free to use
  625. * MMUCR - loaded with proper value when we get here
  626. * Upon exit, we reload everything and RFI.
  627. */
  628. finish_tlb_load_47x:
  629. /* Combine RPN & ERPN an write WS 1 */
  630. rlwimi r11,r12,0,0,31-PAGE_SHIFT
  631. tlbwe r11,r13,1
  632. /* And make up word 2 */
  633. li r10,0xf85 /* Mask to apply from PTE */
  634. rlwimi r10,r12,29,30,30 /* DIRTY -> SW position */
  635. and r11,r12,r10 /* Mask PTE bits to keep */
  636. andi. r10,r12,_PAGE_USER /* User page ? */
  637. beq 1f /* nope, leave U bits empty */
  638. rlwimi r11,r11,3,26,28 /* yes, copy S bits to U */
  639. 1: tlbwe r11,r13,2
  640. /* Done...restore registers and get out of here.
  641. */
  642. mfspr r11, SPRN_SPRG_RSCRATCH4
  643. mtcr r11
  644. mfspr r13, SPRN_SPRG_RSCRATCH3
  645. mfspr r12, SPRN_SPRG_RSCRATCH2
  646. mfspr r11, SPRN_SPRG_RSCRATCH1
  647. mfspr r10, SPRN_SPRG_RSCRATCH0
  648. rfi
  649. #endif /* CONFIG_PPC_47x */
  650. /* Debug Interrupt */
  651. /*
  652. * This statement needs to exist at the end of the IVPR
  653. * definition just in case you end up taking a debug
  654. * exception within another exception.
  655. */
  656. DEBUG_CRIT_EXCEPTION
  657. interrupt_end:
  658. /*
  659. * Global functions
  660. */
  661. /*
  662. * Adjust the machine check IVOR on 440A cores
  663. */
  664. _GLOBAL(__fixup_440A_mcheck)
  665. li r3,MachineCheckA@l
  666. mtspr SPRN_IVOR1,r3
  667. sync
  668. blr
  669. _GLOBAL(set_context)
  670. #ifdef CONFIG_BDI_SWITCH
  671. /* Context switch the PTE pointer for the Abatron BDI2000.
  672. * The PGDIR is the second parameter.
  673. */
  674. lis r5, abatron_pteptrs@h
  675. ori r5, r5, abatron_pteptrs@l
  676. stw r4, 0x4(r5)
  677. #endif
  678. mtspr SPRN_PID,r3
  679. isync /* Force context change */
  680. blr
  681. /*
  682. * Init CPU state. This is called at boot time or for secondary CPUs
  683. * to setup initial TLB entries, setup IVORs, etc...
  684. *
  685. */
  686. _GLOBAL(init_cpu_state)
  687. mflr r22
  688. #ifdef CONFIG_PPC_47x
  689. /* We use the PVR to differentiate 44x cores from 476 */
  690. mfspr r3,SPRN_PVR
  691. srwi r3,r3,16
  692. cmplwi cr0,r3,PVR_476FPE@h
  693. beq head_start_47x
  694. cmplwi cr0,r3,PVR_476@h
  695. beq head_start_47x
  696. cmplwi cr0,r3,PVR_476_ISS@h
  697. beq head_start_47x
  698. #endif /* CONFIG_PPC_47x */
  699. /*
  700. * In case the firmware didn't do it, we apply some workarounds
  701. * that are good for all 440 core variants here
  702. */
  703. mfspr r3,SPRN_CCR0
  704. rlwinm r3,r3,0,0,27 /* disable icache prefetch */
  705. isync
  706. mtspr SPRN_CCR0,r3
  707. isync
  708. sync
  709. /*
  710. * Set up the initial MMU state for 44x
  711. *
  712. * We are still executing code at the virtual address
  713. * mappings set by the firmware for the base of RAM.
  714. *
  715. * We first invalidate all TLB entries but the one
  716. * we are running from. We then load the KERNELBASE
  717. * mappings so we can begin to use kernel addresses
  718. * natively and so the interrupt vector locations are
  719. * permanently pinned (necessary since Book E
  720. * implementations always have translation enabled).
  721. *
  722. * TODO: Use the known TLB entry we are running from to
  723. * determine which physical region we are located
  724. * in. This can be used to determine where in RAM
  725. * (on a shared CPU system) or PCI memory space
  726. * (on a DRAMless system) we are located.
  727. * For now, we assume a perfect world which means
  728. * we are located at the base of DRAM (physical 0).
  729. */
  730. /*
  731. * Search TLB for entry that we are currently using.
  732. * Invalidate all entries but the one we are using.
  733. */
  734. /* Load our current PID->MMUCR TID and MSR IS->MMUCR STS */
  735. mfspr r3,SPRN_PID /* Get PID */
  736. mfmsr r4 /* Get MSR */
  737. andi. r4,r4,MSR_IS@l /* TS=1? */
  738. beq wmmucr /* If not, leave STS=0 */
  739. oris r3,r3,PPC44x_MMUCR_STS@h /* Set STS=1 */
  740. wmmucr: mtspr SPRN_MMUCR,r3 /* Put MMUCR */
  741. sync
  742. bl invstr /* Find our address */
  743. invstr: mflr r5 /* Make it accessible */
  744. tlbsx r23,0,r5 /* Find entry we are in */
  745. li r4,0 /* Start at TLB entry 0 */
  746. li r3,0 /* Set PAGEID inval value */
  747. 1: cmpw r23,r4 /* Is this our entry? */
  748. beq skpinv /* If so, skip the inval */
  749. tlbwe r3,r4,PPC44x_TLB_PAGEID /* If not, inval the entry */
  750. skpinv: addi r4,r4,1 /* Increment */
  751. cmpwi r4,64 /* Are we done? */
  752. bne 1b /* If not, repeat */
  753. isync /* If so, context change */
  754. /*
  755. * Configure and load pinned entry into TLB slot 63.
  756. */
  757. #ifdef CONFIG_NONSTATIC_KERNEL
  758. /*
  759. * In case of a NONSTATIC_KERNEL we reuse the TLB XLAT
  760. * entries of the initial mapping set by the boot loader.
  761. * The XLAT entry is stored in r25
  762. */
  763. /* Read the XLAT entry for our current mapping */
  764. tlbre r25,r23,PPC44x_TLB_XLAT
  765. lis r3,KERNELBASE@h
  766. ori r3,r3,KERNELBASE@l
  767. /* Use our current RPN entry */
  768. mr r4,r25
  769. #else
  770. lis r3,PAGE_OFFSET@h
  771. ori r3,r3,PAGE_OFFSET@l
  772. /* Kernel is at the base of RAM */
  773. li r4, 0 /* Load the kernel physical address */
  774. #endif
  775. /* Load the kernel PID = 0 */
  776. li r0,0
  777. mtspr SPRN_PID,r0
  778. sync
  779. /* Initialize MMUCR */
  780. li r5,0
  781. mtspr SPRN_MMUCR,r5
  782. sync
  783. /* pageid fields */
  784. clrrwi r3,r3,10 /* Mask off the effective page number */
  785. ori r3,r3,PPC44x_TLB_VALID | PPC44x_TLB_256M
  786. /* xlat fields */
  787. clrrwi r4,r4,10 /* Mask off the real page number */
  788. /* ERPN is 0 for first 4GB page */
  789. /* attrib fields */
  790. /* Added guarded bit to protect against speculative loads/stores */
  791. li r5,0
  792. ori r5,r5,(PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G)
  793. li r0,63 /* TLB slot 63 */
  794. tlbwe r3,r0,PPC44x_TLB_PAGEID /* Load the pageid fields */
  795. tlbwe r4,r0,PPC44x_TLB_XLAT /* Load the translation fields */
  796. tlbwe r5,r0,PPC44x_TLB_ATTRIB /* Load the attrib/access fields */
  797. /* Force context change */
  798. mfmsr r0
  799. mtspr SPRN_SRR1, r0
  800. lis r0,3f@h
  801. ori r0,r0,3f@l
  802. mtspr SPRN_SRR0,r0
  803. sync
  804. rfi
  805. /* If necessary, invalidate original entry we used */
  806. 3: cmpwi r23,63
  807. beq 4f
  808. li r6,0
  809. tlbwe r6,r23,PPC44x_TLB_PAGEID
  810. isync
  811. 4:
  812. #ifdef CONFIG_PPC_EARLY_DEBUG_44x
  813. /* Add UART mapping for early debug. */
  814. /* pageid fields */
  815. lis r3,PPC44x_EARLY_DEBUG_VIRTADDR@h
  816. ori r3,r3,PPC44x_TLB_VALID|PPC44x_TLB_TS|PPC44x_TLB_64K
  817. /* xlat fields */
  818. lis r4,CONFIG_PPC_EARLY_DEBUG_44x_PHYSLOW@h
  819. ori r4,r4,CONFIG_PPC_EARLY_DEBUG_44x_PHYSHIGH
  820. /* attrib fields */
  821. li r5,(PPC44x_TLB_SW|PPC44x_TLB_SR|PPC44x_TLB_I|PPC44x_TLB_G)
  822. li r0,62 /* TLB slot 0 */
  823. tlbwe r3,r0,PPC44x_TLB_PAGEID
  824. tlbwe r4,r0,PPC44x_TLB_XLAT
  825. tlbwe r5,r0,PPC44x_TLB_ATTRIB
  826. /* Force context change */
  827. isync
  828. #endif /* CONFIG_PPC_EARLY_DEBUG_44x */
  829. /* Establish the interrupt vector offsets */
  830. SET_IVOR(0, CriticalInput);
  831. SET_IVOR(1, MachineCheck);
  832. SET_IVOR(2, DataStorage);
  833. SET_IVOR(3, InstructionStorage);
  834. SET_IVOR(4, ExternalInput);
  835. SET_IVOR(5, Alignment);
  836. SET_IVOR(6, Program);
  837. SET_IVOR(7, FloatingPointUnavailable);
  838. SET_IVOR(8, SystemCall);
  839. SET_IVOR(9, AuxillaryProcessorUnavailable);
  840. SET_IVOR(10, Decrementer);
  841. SET_IVOR(11, FixedIntervalTimer);
  842. SET_IVOR(12, WatchdogTimer);
  843. SET_IVOR(13, DataTLBError44x);
  844. SET_IVOR(14, InstructionTLBError44x);
  845. SET_IVOR(15, DebugCrit);
  846. b head_start_common
  847. #ifdef CONFIG_PPC_47x
  848. #ifdef CONFIG_SMP
  849. /* Entry point for secondary 47x processors */
  850. _GLOBAL(start_secondary_47x)
  851. mr r24,r3 /* CPU number */
  852. bl init_cpu_state
  853. /* Now we need to bolt the rest of kernel memory which
  854. * is done in C code. We must be careful because our task
  855. * struct or our stack can (and will probably) be out
  856. * of reach of the initial 256M TLB entry, so we use a
  857. * small temporary stack in .bss for that. This works
  858. * because only one CPU at a time can be in this code
  859. */
  860. lis r1,temp_boot_stack@h
  861. ori r1,r1,temp_boot_stack@l
  862. addi r1,r1,1024-STACK_FRAME_OVERHEAD
  863. li r0,0
  864. stw r0,0(r1)
  865. bl mmu_init_secondary
  866. /* Now we can get our task struct and real stack pointer */
  867. /* Get current's stack and current */
  868. lis r2,secondary_current@ha
  869. lwz r2,secondary_current@l(r2)
  870. lwz r1,TASK_STACK(r2)
  871. /* Current stack pointer */
  872. addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
  873. li r0,0
  874. stw r0,0(r1)
  875. /* Kernel stack for exception entry in SPRG3 */
  876. addi r4,r2,THREAD /* init task's THREAD */
  877. mtspr SPRN_SPRG3,r4
  878. b start_secondary
  879. #endif /* CONFIG_SMP */
  880. /*
  881. * Set up the initial MMU state for 44x
  882. *
  883. * We are still executing code at the virtual address
  884. * mappings set by the firmware for the base of RAM.
  885. */
  886. head_start_47x:
  887. /* Load our current PID->MMUCR TID and MSR IS->MMUCR STS */
  888. mfspr r3,SPRN_PID /* Get PID */
  889. mfmsr r4 /* Get MSR */
  890. andi. r4,r4,MSR_IS@l /* TS=1? */
  891. beq 1f /* If not, leave STS=0 */
  892. oris r3,r3,PPC47x_MMUCR_STS@h /* Set STS=1 */
  893. 1: mtspr SPRN_MMUCR,r3 /* Put MMUCR */
  894. sync
  895. /* Find the entry we are running from */
  896. bl 1f
  897. 1: mflr r23
  898. tlbsx r23,0,r23
  899. tlbre r24,r23,0
  900. tlbre r25,r23,1
  901. tlbre r26,r23,2
  902. /*
  903. * Cleanup time
  904. */
  905. /* Initialize MMUCR */
  906. li r5,0
  907. mtspr SPRN_MMUCR,r5
  908. sync
  909. clear_all_utlb_entries:
  910. #; Set initial values.
  911. addis r3,0,0x8000
  912. addi r4,0,0
  913. addi r5,0,0
  914. b clear_utlb_entry
  915. #; Align the loop to speed things up.
  916. .align 6
  917. clear_utlb_entry:
  918. tlbwe r4,r3,0
  919. tlbwe r5,r3,1
  920. tlbwe r5,r3,2
  921. addis r3,r3,0x2000
  922. cmpwi r3,0
  923. bne clear_utlb_entry
  924. addis r3,0,0x8000
  925. addis r4,r4,0x100
  926. cmpwi r4,0
  927. bne clear_utlb_entry
  928. #; Restore original entry.
  929. oris r23,r23,0x8000 /* specify the way */
  930. tlbwe r24,r23,0
  931. tlbwe r25,r23,1
  932. tlbwe r26,r23,2
  933. /*
  934. * Configure and load pinned entry into TLB for the kernel core
  935. */
  936. lis r3,PAGE_OFFSET@h
  937. ori r3,r3,PAGE_OFFSET@l
  938. /* Load the kernel PID = 0 */
  939. li r0,0
  940. mtspr SPRN_PID,r0
  941. sync
  942. /* Word 0 */
  943. clrrwi r3,r3,12 /* Mask off the effective page number */
  944. ori r3,r3,PPC47x_TLB0_VALID | PPC47x_TLB0_256M
  945. /* Word 1 - use r25. RPN is the same as the original entry */
  946. /* Word 2 */
  947. li r5,0
  948. ori r5,r5,PPC47x_TLB2_S_RWX
  949. #ifdef CONFIG_SMP
  950. ori r5,r5,PPC47x_TLB2_M
  951. #endif
  952. /* We write to way 0 and bolted 0 */
  953. lis r0,0x8800
  954. tlbwe r3,r0,0
  955. tlbwe r25,r0,1
  956. tlbwe r5,r0,2
  957. /*
  958. * Configure SSPCR, ISPCR and USPCR for now to search everything, we can fix
  959. * them up later
  960. */
  961. LOAD_REG_IMMEDIATE(r3, 0x9abcdef0)
  962. mtspr SPRN_SSPCR,r3
  963. mtspr SPRN_USPCR,r3
  964. LOAD_REG_IMMEDIATE(r3, 0x12345670)
  965. mtspr SPRN_ISPCR,r3
  966. /* Force context change */
  967. mfmsr r0
  968. mtspr SPRN_SRR1, r0
  969. lis r0,3f@h
  970. ori r0,r0,3f@l
  971. mtspr SPRN_SRR0,r0
  972. sync
  973. rfi
  974. /* Invalidate original entry we used */
  975. 3:
  976. rlwinm r24,r24,0,21,19 /* clear the "valid" bit */
  977. tlbwe r24,r23,0
  978. addi r24,0,0
  979. tlbwe r24,r23,1
  980. tlbwe r24,r23,2
  981. isync /* Clear out the shadow TLB entries */
  982. #ifdef CONFIG_PPC_EARLY_DEBUG_44x
  983. /* Add UART mapping for early debug. */
  984. /* Word 0 */
  985. lis r3,PPC44x_EARLY_DEBUG_VIRTADDR@h
  986. ori r3,r3,PPC47x_TLB0_VALID | PPC47x_TLB0_TS | PPC47x_TLB0_1M
  987. /* Word 1 */
  988. lis r4,CONFIG_PPC_EARLY_DEBUG_44x_PHYSLOW@h
  989. ori r4,r4,CONFIG_PPC_EARLY_DEBUG_44x_PHYSHIGH
  990. /* Word 2 */
  991. li r5,(PPC47x_TLB2_S_RW | PPC47x_TLB2_IMG)
  992. /* Bolted in way 0, bolt slot 5, we -hope- we don't hit the same
  993. * congruence class as the kernel, we need to make sure of it at
  994. * some point
  995. */
  996. lis r0,0x8d00
  997. tlbwe r3,r0,0
  998. tlbwe r4,r0,1
  999. tlbwe r5,r0,2
  1000. /* Force context change */
  1001. isync
  1002. #endif /* CONFIG_PPC_EARLY_DEBUG_44x */
  1003. /* Establish the interrupt vector offsets */
  1004. SET_IVOR(0, CriticalInput);
  1005. SET_IVOR(1, MachineCheckA);
  1006. SET_IVOR(2, DataStorage);
  1007. SET_IVOR(3, InstructionStorage);
  1008. SET_IVOR(4, ExternalInput);
  1009. SET_IVOR(5, Alignment);
  1010. SET_IVOR(6, Program);
  1011. SET_IVOR(7, FloatingPointUnavailable);
  1012. SET_IVOR(8, SystemCall);
  1013. SET_IVOR(9, AuxillaryProcessorUnavailable);
  1014. SET_IVOR(10, Decrementer);
  1015. SET_IVOR(11, FixedIntervalTimer);
  1016. SET_IVOR(12, WatchdogTimer);
  1017. SET_IVOR(13, DataTLBError47x);
  1018. SET_IVOR(14, InstructionTLBError47x);
  1019. SET_IVOR(15, DebugCrit);
  1020. /* We configure icbi to invalidate 128 bytes at a time since the
  1021. * current 32-bit kernel code isn't too happy with icache != dcache
  1022. * block size. We also disable the BTAC as this can cause errors
  1023. * in some circumstances (see IBM Erratum 47).
  1024. */
  1025. mfspr r3,SPRN_CCR0
  1026. oris r3,r3,0x0020
  1027. ori r3,r3,0x0040
  1028. mtspr SPRN_CCR0,r3
  1029. isync
  1030. #endif /* CONFIG_PPC_47x */
  1031. /*
  1032. * Here we are back to code that is common between 44x and 47x
  1033. *
  1034. * We proceed to further kernel initialization and return to the
  1035. * main kernel entry
  1036. */
  1037. head_start_common:
  1038. /* Establish the interrupt vector base */
  1039. lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
  1040. mtspr SPRN_IVPR,r4
  1041. /*
  1042. * If the kernel was loaded at a non-zero 256 MB page, we need to
  1043. * mask off the most significant 4 bits to get the relative address
  1044. * from the start of physical memory
  1045. */
  1046. rlwinm r22,r22,0,4,31
  1047. addis r22,r22,PAGE_OFFSET@h
  1048. mtlr r22
  1049. isync
  1050. blr
  1051. /*
  1052. * We put a few things here that have to be page-aligned. This stuff
  1053. * goes at the beginning of the data segment, which is page-aligned.
  1054. */
  1055. .data
  1056. .align PAGE_SHIFT
  1057. .globl sdata
  1058. sdata:
  1059. .globl empty_zero_page
  1060. empty_zero_page:
  1061. .space PAGE_SIZE
  1062. EXPORT_SYMBOL(empty_zero_page)
  1063. /*
  1064. * To support >32-bit physical addresses, we use an 8KB pgdir.
  1065. */
  1066. .globl swapper_pg_dir
  1067. swapper_pg_dir:
  1068. .space PGD_TABLE_SIZE
  1069. /*
  1070. * Room for two PTE pointers, usually the kernel and current user pointers
  1071. * to their respective root page table.
  1072. */
  1073. abatron_pteptrs:
  1074. .space 8
  1075. #ifdef CONFIG_SMP
  1076. .align 12
  1077. temp_boot_stack:
  1078. .space 1024
  1079. #endif /* CONFIG_SMP */