/arch/powerpc/include/asm/mmu.h

http://github.com/mirrors/linux · C Header · 379 lines · 231 code · 61 blank · 87 comment · 3 complexity · cf6f3ba1404c4653b9cc9f3355d62bf1 MD5 · raw file

  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. #ifndef _ASM_POWERPC_MMU_H_
  3. #define _ASM_POWERPC_MMU_H_
  4. #ifdef __KERNEL__
  5. #include <linux/types.h>
  6. #include <asm/asm-const.h>
  7. /*
  8. * MMU features bit definitions
  9. */
  10. /*
  11. * MMU families
  12. */
  13. #define MMU_FTR_HPTE_TABLE ASM_CONST(0x00000001)
  14. #define MMU_FTR_TYPE_8xx ASM_CONST(0x00000002)
  15. #define MMU_FTR_TYPE_40x ASM_CONST(0x00000004)
  16. #define MMU_FTR_TYPE_44x ASM_CONST(0x00000008)
  17. #define MMU_FTR_TYPE_FSL_E ASM_CONST(0x00000010)
  18. #define MMU_FTR_TYPE_47x ASM_CONST(0x00000020)
  19. /* Radix page table supported and enabled */
  20. #define MMU_FTR_TYPE_RADIX ASM_CONST(0x00000040)
  21. /*
  22. * Individual features below.
  23. */
  24. /*
  25. * Support for 68 bit VA space. We added that from ISA 2.05
  26. */
  27. #define MMU_FTR_68_BIT_VA ASM_CONST(0x00002000)
  28. /*
  29. * Kernel read only support.
  30. * We added the ppp value 0b110 in ISA 2.04.
  31. */
  32. #define MMU_FTR_KERNEL_RO ASM_CONST(0x00004000)
  33. /*
  34. * We need to clear top 16bits of va (from the remaining 64 bits )in
  35. * tlbie* instructions
  36. */
  37. #define MMU_FTR_TLBIE_CROP_VA ASM_CONST(0x00008000)
  38. /* Enable use of high BAT registers */
  39. #define MMU_FTR_USE_HIGH_BATS ASM_CONST(0x00010000)
  40. /* Enable >32-bit physical addresses on 32-bit processor, only used
  41. * by CONFIG_PPC_BOOK3S_32 currently as BookE supports that from day 1
  42. */
  43. #define MMU_FTR_BIG_PHYS ASM_CONST(0x00020000)
  44. /* Enable use of broadcast TLB invalidations. We don't always set it
  45. * on processors that support it due to other constraints with the
  46. * use of such invalidations
  47. */
  48. #define MMU_FTR_USE_TLBIVAX_BCAST ASM_CONST(0x00040000)
  49. /* Enable use of tlbilx invalidate instructions.
  50. */
  51. #define MMU_FTR_USE_TLBILX ASM_CONST(0x00080000)
  52. /* This indicates that the processor cannot handle multiple outstanding
  53. * broadcast tlbivax or tlbsync. This makes the code use a spinlock
  54. * around such invalidate forms.
  55. */
  56. #define MMU_FTR_LOCK_BCAST_INVAL ASM_CONST(0x00100000)
  57. /* This indicates that the processor doesn't handle way selection
  58. * properly and needs SW to track and update the LRU state. This
  59. * is specific to an errata on e300c2/c3/c4 class parts
  60. */
  61. #define MMU_FTR_NEED_DTLB_SW_LRU ASM_CONST(0x00200000)
  62. /* Enable use of TLB reservation. Processor should support tlbsrx.
  63. * instruction and MAS0[WQ].
  64. */
  65. #define MMU_FTR_USE_TLBRSRV ASM_CONST(0x00800000)
  66. /* Use paired MAS registers (MAS7||MAS3, etc.)
  67. */
  68. #define MMU_FTR_USE_PAIRED_MAS ASM_CONST(0x01000000)
  69. /* Doesn't support the B bit (1T segment) in SLBIE
  70. */
  71. #define MMU_FTR_NO_SLBIE_B ASM_CONST(0x02000000)
  72. /* Support 16M large pages
  73. */
  74. #define MMU_FTR_16M_PAGE ASM_CONST(0x04000000)
  75. /* Supports TLBIEL variant
  76. */
  77. #define MMU_FTR_TLBIEL ASM_CONST(0x08000000)
  78. /* Supports tlbies w/o locking
  79. */
  80. #define MMU_FTR_LOCKLESS_TLBIE ASM_CONST(0x10000000)
  81. /* Large pages can be marked CI
  82. */
  83. #define MMU_FTR_CI_LARGE_PAGE ASM_CONST(0x20000000)
  84. /* 1T segments available
  85. */
  86. #define MMU_FTR_1T_SEGMENT ASM_CONST(0x40000000)
  87. /*
  88. * Supports KUAP (key 0 controlling userspace addresses) on radix
  89. */
  90. #define MMU_FTR_RADIX_KUAP ASM_CONST(0x80000000)
  91. /* MMU feature bit sets for various CPUs */
  92. #define MMU_FTRS_DEFAULT_HPTE_ARCH_V2 \
  93. MMU_FTR_HPTE_TABLE | MMU_FTR_PPCAS_ARCH_V2
  94. #define MMU_FTRS_POWER MMU_FTRS_DEFAULT_HPTE_ARCH_V2
  95. #define MMU_FTRS_PPC970 MMU_FTRS_POWER | MMU_FTR_TLBIE_CROP_VA
  96. #define MMU_FTRS_POWER5 MMU_FTRS_POWER | MMU_FTR_LOCKLESS_TLBIE
  97. #define MMU_FTRS_POWER6 MMU_FTRS_POWER5 | MMU_FTR_KERNEL_RO | MMU_FTR_68_BIT_VA
  98. #define MMU_FTRS_POWER7 MMU_FTRS_POWER6
  99. #define MMU_FTRS_POWER8 MMU_FTRS_POWER6
  100. #define MMU_FTRS_POWER9 MMU_FTRS_POWER6
  101. #define MMU_FTRS_CELL MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
  102. MMU_FTR_CI_LARGE_PAGE
  103. #define MMU_FTRS_PA6T MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
  104. MMU_FTR_CI_LARGE_PAGE | MMU_FTR_NO_SLBIE_B
  105. #ifndef __ASSEMBLY__
  106. #include <linux/bug.h>
  107. #include <asm/cputable.h>
  108. #include <asm/page.h>
  109. typedef pte_t *pgtable_t;
  110. #ifdef CONFIG_PPC_FSL_BOOK3E
  111. #include <asm/percpu.h>
  112. DECLARE_PER_CPU(int, next_tlbcam_idx);
  113. #endif
  114. enum {
  115. MMU_FTRS_POSSIBLE =
  116. #ifdef CONFIG_PPC_BOOK3S
  117. MMU_FTR_HPTE_TABLE |
  118. #endif
  119. #ifdef CONFIG_PPC_8xx
  120. MMU_FTR_TYPE_8xx |
  121. #endif
  122. #ifdef CONFIG_40x
  123. MMU_FTR_TYPE_40x |
  124. #endif
  125. #ifdef CONFIG_44x
  126. MMU_FTR_TYPE_44x |
  127. #endif
  128. #if defined(CONFIG_E200) || defined(CONFIG_E500)
  129. MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS | MMU_FTR_USE_TLBILX |
  130. #endif
  131. #ifdef CONFIG_PPC_47x
  132. MMU_FTR_TYPE_47x | MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL |
  133. #endif
  134. #ifdef CONFIG_PPC_BOOK3S_32
  135. MMU_FTR_USE_HIGH_BATS | MMU_FTR_NEED_DTLB_SW_LRU |
  136. #endif
  137. #ifdef CONFIG_PPC_BOOK3E_64
  138. MMU_FTR_USE_TLBRSRV | MMU_FTR_USE_PAIRED_MAS |
  139. #endif
  140. #ifdef CONFIG_PPC_BOOK3S_64
  141. MMU_FTR_NO_SLBIE_B | MMU_FTR_16M_PAGE | MMU_FTR_TLBIEL |
  142. MMU_FTR_LOCKLESS_TLBIE | MMU_FTR_CI_LARGE_PAGE |
  143. MMU_FTR_1T_SEGMENT | MMU_FTR_TLBIE_CROP_VA |
  144. MMU_FTR_KERNEL_RO | MMU_FTR_68_BIT_VA |
  145. #endif
  146. #ifdef CONFIG_PPC_RADIX_MMU
  147. MMU_FTR_TYPE_RADIX |
  148. #ifdef CONFIG_PPC_KUAP
  149. MMU_FTR_RADIX_KUAP |
  150. #endif /* CONFIG_PPC_KUAP */
  151. #endif /* CONFIG_PPC_RADIX_MMU */
  152. 0,
  153. };
  154. static inline bool early_mmu_has_feature(unsigned long feature)
  155. {
  156. return !!(MMU_FTRS_POSSIBLE & cur_cpu_spec->mmu_features & feature);
  157. }
  158. #ifdef CONFIG_JUMP_LABEL_FEATURE_CHECKS
  159. #include <linux/jump_label.h>
  160. #define NUM_MMU_FTR_KEYS 32
  161. extern struct static_key_true mmu_feature_keys[NUM_MMU_FTR_KEYS];
  162. extern void mmu_feature_keys_init(void);
  163. static __always_inline bool mmu_has_feature(unsigned long feature)
  164. {
  165. int i;
  166. #ifndef __clang__ /* clang can't cope with this */
  167. BUILD_BUG_ON(!__builtin_constant_p(feature));
  168. #endif
  169. #ifdef CONFIG_JUMP_LABEL_FEATURE_CHECK_DEBUG
  170. if (!static_key_initialized) {
  171. printk("Warning! mmu_has_feature() used prior to jump label init!\n");
  172. dump_stack();
  173. return early_mmu_has_feature(feature);
  174. }
  175. #endif
  176. if (!(MMU_FTRS_POSSIBLE & feature))
  177. return false;
  178. i = __builtin_ctzl(feature);
  179. return static_branch_likely(&mmu_feature_keys[i]);
  180. }
  181. static inline void mmu_clear_feature(unsigned long feature)
  182. {
  183. int i;
  184. i = __builtin_ctzl(feature);
  185. cur_cpu_spec->mmu_features &= ~feature;
  186. static_branch_disable(&mmu_feature_keys[i]);
  187. }
  188. #else
  189. static inline void mmu_feature_keys_init(void)
  190. {
  191. }
  192. static inline bool mmu_has_feature(unsigned long feature)
  193. {
  194. return early_mmu_has_feature(feature);
  195. }
  196. static inline void mmu_clear_feature(unsigned long feature)
  197. {
  198. cur_cpu_spec->mmu_features &= ~feature;
  199. }
  200. #endif /* CONFIG_JUMP_LABEL */
  201. extern unsigned int __start___mmu_ftr_fixup, __stop___mmu_ftr_fixup;
  202. #ifdef CONFIG_PPC64
  203. /* This is our real memory area size on ppc64 server, on embedded, we
  204. * make it match the size our of bolted TLB area
  205. */
  206. extern u64 ppc64_rma_size;
  207. /* Cleanup function used by kexec */
  208. extern void mmu_cleanup_all(void);
  209. extern void radix__mmu_cleanup_all(void);
  210. /* Functions for creating and updating partition table on POWER9 */
  211. extern void mmu_partition_table_init(void);
  212. extern void mmu_partition_table_set_entry(unsigned int lpid, unsigned long dw0,
  213. unsigned long dw1, bool flush);
  214. #endif /* CONFIG_PPC64 */
  215. struct mm_struct;
  216. #ifdef CONFIG_DEBUG_VM
  217. extern void assert_pte_locked(struct mm_struct *mm, unsigned long addr);
  218. #else /* CONFIG_DEBUG_VM */
  219. static inline void assert_pte_locked(struct mm_struct *mm, unsigned long addr)
  220. {
  221. }
  222. #endif /* !CONFIG_DEBUG_VM */
  223. #ifdef CONFIG_PPC_RADIX_MMU
  224. static inline bool radix_enabled(void)
  225. {
  226. return mmu_has_feature(MMU_FTR_TYPE_RADIX);
  227. }
  228. static inline bool early_radix_enabled(void)
  229. {
  230. return early_mmu_has_feature(MMU_FTR_TYPE_RADIX);
  231. }
  232. #else
  233. static inline bool radix_enabled(void)
  234. {
  235. return false;
  236. }
  237. static inline bool early_radix_enabled(void)
  238. {
  239. return false;
  240. }
  241. #endif
  242. #ifdef CONFIG_PPC_MEM_KEYS
  243. extern u16 get_mm_addr_key(struct mm_struct *mm, unsigned long address);
  244. #else
  245. static inline u16 get_mm_addr_key(struct mm_struct *mm, unsigned long address)
  246. {
  247. return 0;
  248. }
  249. #endif /* CONFIG_PPC_MEM_KEYS */
  250. #ifdef CONFIG_STRICT_KERNEL_RWX
  251. static inline bool strict_kernel_rwx_enabled(void)
  252. {
  253. return rodata_enabled;
  254. }
  255. #else
  256. static inline bool strict_kernel_rwx_enabled(void)
  257. {
  258. return false;
  259. }
  260. #endif
  261. #endif /* !__ASSEMBLY__ */
  262. /* The kernel use the constants below to index in the page sizes array.
  263. * The use of fixed constants for this purpose is better for performances
  264. * of the low level hash refill handlers.
  265. *
  266. * A non supported page size has a "shift" field set to 0
  267. *
  268. * Any new page size being implemented can get a new entry in here. Whether
  269. * the kernel will use it or not is a different matter though. The actual page
  270. * size used by hugetlbfs is not defined here and may be made variable
  271. *
  272. * Note: This array ended up being a false good idea as it's growing to the
  273. * point where I wonder if we should replace it with something different,
  274. * to think about, feedback welcome. --BenH.
  275. */
  276. /* These are #defines as they have to be used in assembly */
  277. #define MMU_PAGE_4K 0
  278. #define MMU_PAGE_16K 1
  279. #define MMU_PAGE_64K 2
  280. #define MMU_PAGE_64K_AP 3 /* "Admixed pages" (hash64 only) */
  281. #define MMU_PAGE_256K 4
  282. #define MMU_PAGE_512K 5
  283. #define MMU_PAGE_1M 6
  284. #define MMU_PAGE_2M 7
  285. #define MMU_PAGE_4M 8
  286. #define MMU_PAGE_8M 9
  287. #define MMU_PAGE_16M 10
  288. #define MMU_PAGE_64M 11
  289. #define MMU_PAGE_256M 12
  290. #define MMU_PAGE_1G 13
  291. #define MMU_PAGE_16G 14
  292. #define MMU_PAGE_64G 15
  293. /*
  294. * N.B. we need to change the type of hpte_page_sizes if this gets to be > 16
  295. * Also we need to change he type of mm_context.low/high_slices_psize.
  296. */
  297. #define MMU_PAGE_COUNT 16
  298. #ifdef CONFIG_PPC_BOOK3S_64
  299. #include <asm/book3s/64/mmu.h>
  300. #else /* CONFIG_PPC_BOOK3S_64 */
  301. #ifndef __ASSEMBLY__
  302. /* MMU initialization */
  303. extern void early_init_mmu(void);
  304. extern void early_init_mmu_secondary(void);
  305. extern void setup_initial_memory_limit(phys_addr_t first_memblock_base,
  306. phys_addr_t first_memblock_size);
  307. static inline void mmu_early_init_devtree(void) { }
  308. extern void *abatron_pteptrs[2];
  309. #endif /* __ASSEMBLY__ */
  310. #endif
  311. #if defined(CONFIG_PPC_BOOK3S_32)
  312. /* 32-bit classic hash table MMU */
  313. #include <asm/book3s/32/mmu-hash.h>
  314. #elif defined(CONFIG_PPC_MMU_NOHASH)
  315. #include <asm/nohash/mmu.h>
  316. #endif
  317. #endif /* __KERNEL__ */
  318. #endif /* _ASM_POWERPC_MMU_H_ */