/arch/powerpc/include/asm/exception-64s.h

  1/* SPDX-License-Identifier: GPL-2.0-or-later */
  2#ifndef _ASM_POWERPC_EXCEPTION_H
  3#define _ASM_POWERPC_EXCEPTION_H
  4/*
  5 * Extracted from head_64.S
  6 *
  7 *  PowerPC version
  8 *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  9 *
 10 *  Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
 11 *    Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
 12 *  Adapted for Power Macintosh by Paul Mackerras.
 13 *  Low-level exception handlers and MMU support
 14 *  rewritten by Paul Mackerras.
 15 *    Copyright (C) 1996 Paul Mackerras.
 16 *
 17 *  Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
 18 *    Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
 19 *
 20 *  This file contains the low-level support and setup for the
 21 *  PowerPC-64 platform, including trap and interrupt dispatch.
 22 */
 23/*
 24 * The following macros define the code that appears as
 25 * the prologue to each of the exception handlers.  They
 26 * are split into two parts to allow a single kernel binary
 27 * to be used for pSeries and iSeries.
 28 *
 29 * We make as much of the exception code common between native
 30 * exception handlers (including pSeries LPAR) and iSeries LPAR
 31 * implementations as possible.
 32 */
 33#include <asm/feature-fixups.h>
 34
 35/* PACA save area size in u64 units (exgen, exmc, etc) */
 36#define EX_SIZE		10
 37
 38/*
 39 * maximum recursive depth of MCE exceptions
 40 */
 41#define MAX_MCE_DEPTH	4
 42
 43#ifdef __ASSEMBLY__
 44
 45#define STF_ENTRY_BARRIER_SLOT						\
 46	STF_ENTRY_BARRIER_FIXUP_SECTION;				\
 47	nop;								\
 48	nop;								\
 49	nop
 50
 51#define STF_EXIT_BARRIER_SLOT						\
 52	STF_EXIT_BARRIER_FIXUP_SECTION;					\
 53	nop;								\
 54	nop;								\
 55	nop;								\
 56	nop;								\
 57	nop;								\
 58	nop
 59
 60/*
 61 * r10 must be free to use, r13 must be paca
 62 */
 63#define INTERRUPT_TO_KERNEL						\
 64	STF_ENTRY_BARRIER_SLOT
 65
 66/*
 67 * Macros for annotating the expected destination of (h)rfid
 68 *
 69 * The nop instructions allow us to insert one or more instructions to flush the
 70 * L1-D cache when returning to userspace or a guest.
 71 */
 72#define RFI_FLUSH_SLOT							\
 73	RFI_FLUSH_FIXUP_SECTION;					\
 74	nop;								\
 75	nop;								\
 76	nop
 77
 78#define RFI_TO_KERNEL							\
 79	rfid
 80
 81#define RFI_TO_USER							\
 82	STF_EXIT_BARRIER_SLOT;						\
 83	RFI_FLUSH_SLOT;							\
 84	rfid;								\
 85	b	rfi_flush_fallback
 86
 87#define RFI_TO_USER_OR_KERNEL						\
 88	STF_EXIT_BARRIER_SLOT;						\
 89	RFI_FLUSH_SLOT;							\
 90	rfid;								\
 91	b	rfi_flush_fallback
 92
 93#define RFI_TO_GUEST							\
 94	STF_EXIT_BARRIER_SLOT;						\
 95	RFI_FLUSH_SLOT;							\
 96	rfid;								\
 97	b	rfi_flush_fallback
 98
 99#define HRFI_TO_KERNEL							\
100	hrfid
101
102#define HRFI_TO_USER							\
103	STF_EXIT_BARRIER_SLOT;						\
104	RFI_FLUSH_SLOT;							\
105	hrfid;								\
106	b	hrfi_flush_fallback
107
108#define HRFI_TO_USER_OR_KERNEL						\
109	STF_EXIT_BARRIER_SLOT;						\
110	RFI_FLUSH_SLOT;							\
111	hrfid;								\
112	b	hrfi_flush_fallback
113
114#define HRFI_TO_GUEST							\
115	STF_EXIT_BARRIER_SLOT;						\
116	RFI_FLUSH_SLOT;							\
117	hrfid;								\
118	b	hrfi_flush_fallback
119
120#define HRFI_TO_UNKNOWN							\
121	STF_EXIT_BARRIER_SLOT;						\
122	RFI_FLUSH_SLOT;							\
123	hrfid;								\
124	b	hrfi_flush_fallback
125
126#endif /* __ASSEMBLY__ */
127
128#endif	/* _ASM_POWERPC_EXCEPTION_H */